[deliverable/linux.git] / arch / sh / mm / tlb-sh4.c

/*
 * arch/sh/mm/tlb-sh4.c
 *
 * SH-4 specific TLB operations
 *
 * Copyright (C) 1999  Niibe Yutaka
 * Copyright (C) 2002 - 2007 Paul Mundt
 *
 * Released under the terms of the GNU GPL v2.0.
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>

void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
	unsigned long flags, pteval, vpn;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (vma && current->active_mm != vma->vm_mm)
		return;

	local_irq_save(flags);

	/* Set PTEH register */
	vpn = (address & MMU_VPN_MASK) | get_asid();
	__raw_writel(vpn, MMU_PTEH);

	pteval = pte.pte_low;

	/* Set PTEA register */
#ifdef CONFIG_X2TLB
	/*
	 * For the extended mode TLB this is trivial, only the ESZ and
	 * EPR bits need to be written out to PTEA, with the remainder of
	 * the protection bits (with the exception of the compat-mode SZ
	 * and PR bits, which are cleared) being written out in PTEL.
	 */
	__raw_writel(pte.pte_high, MMU_PTEA);
#else
	if (cpu_data->flags & CPU_HAS_PTEA) {
		/* The last 3 bits and the first one of pteval contains
		 * the PTEA timing control and space attribute bits
		 */
		__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
	}
#endif

	/* Set PTEL register */
	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
#ifdef CONFIG_CACHE_WRITETHROUGH
	pteval |= _PAGE_WT;
#endif
	/* conveniently, we want all the software flags to be 0 anyway */
	__raw_writel(pteval, MMU_PTEL);

	/* Load the TLB */
	asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
	local_irq_restore(flags);
}

void local_flush_tlb_one(unsigned long asid, unsigned long page)
{
	unsigned long addr, data;

	/*
	 * NOTE: PTEH.ASID should be set to this MM
	 *       _AND_ we need to write ASID to the array.
	 *
	 * It would be simple if we didn't need to set PTEH.ASID...
	 */
	addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
	data = page | asid; /* VALID bit is off */
	jump_to_uncached();
	__raw_writel(data, addr);
	back_to_cached();
}

void local_flush_tlb_all(void)
{
	unsigned long flags, status;
	int i;

	/*
	 * Flush all the TLB.
	 */
	local_irq_save(flags);
	jump_to_uncached();

	status = __raw_readl(MMUCR);
	status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);

	if (status == 0)
		status = MMUCR_URB_NENTRIES;

	for (i = 0; i < status; i++)
		__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));

	for (i = 0; i < 4; i++)
		__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));

	back_to_cached();
	ctrl_barrier();
	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/sh/mm/tlb-sh4.c
	3	*
	4	* SH-4 specific TLB operations
	5	*
	6	* Copyright (C) 1999 Niibe Yutaka
d04a0f79	7	* Copyright (C) 2002 - 2007 Paul Mundt
1da177e4 LT	8	*
	9	* Released under the terms of the GNU GPL v2.0.
	10	*/
39e688a9	11	#include <linux/kernel.h>
39e688a9	12	#include <linux/mm.h>
d04a0f79	13	#include <linux/io.h>
1da177e4	14	#include <asm/mmu_context.h>
39e688a9 PM	15	#include <asm/cacheflush.h>
39e688a9 PM	16
9cef7492	17	void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
39e688a9	18	{
9cef7492	19	unsigned long flags, pteval, vpn;
39e688a9	20
9cef7492 PM	21	/*
	22	* Handle debugger faulting in for debugee.
	23	*/
3ed6e129	24	if (vma && current->active_mm != vma->vm_mm)
39e688a9 PM	25	return;
39e688a9 PM	26
39e688a9 PM	27	local_irq_save(flags);
	28
	29	/* Set PTEH register */
	30	vpn = (address & MMU_VPN_MASK) \| get_asid();
9d56dd3b	31	__raw_writel(vpn, MMU_PTEH);
39e688a9	32
d04a0f79	33	pteval = pte.pte_low;
39e688a9 PM	34
39e688a9 PM	35	/* Set PTEA register */
d04a0f79 PM	36	#ifdef CONFIG_X2TLB
	37	/*
	38	* For the extended mode TLB this is trivial, only the ESZ and
	39	* EPR bits need to be written out to PTEA, with the remainder of
	40	* the protection bits (with the exception of the compat-mode SZ
	41	* and PR bits, which are cleared) being written out in PTEL.
	42	*/
9d56dd3b	43	__raw_writel(pte.pte_high, MMU_PTEA);
d04a0f79	44	#else
6503fe4a MT	45	if (cpu_data->flags & CPU_HAS_PTEA) {
	46	/* The last 3 bits and the first one of pteval contains
	47	* the PTEA timing control and space attribute bits
	48	*/
9d56dd3b	49	__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
6503fe4a	50	}
d04a0f79	51	#endif
39e688a9 PM	52
	53	/* Set PTEL register */
	54	pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
e7bd34a1	55	#ifdef CONFIG_CACHE_WRITETHROUGH
39e688a9 PM	56	pteval \|= _PAGE_WT;
	57	#endif
	58	/* conveniently, we want all the software flags to be 0 anyway */
9d56dd3b	59	__raw_writel(pteval, MMU_PTEL);
39e688a9 PM	60
	61	/* Load the TLB */
	62	asm volatile("ldtlb": /* no output / : / no input */ : "memory");
	63	local_irq_restore(flags);
	64	}
1da177e4	65
2dc2f8e0	66	void local_flush_tlb_one(unsigned long asid, unsigned long page)
1da177e4 LT	67	{
	68	unsigned long addr, data;
	69
	70	/*
	71	* NOTE: PTEH.ASID should be set to this MM
	72	* _AND_ we need to write ASID to the array.
	73	*
	74	* It would be simple if we didn't need to set PTEH.ASID...
	75	*/
	76	addr = MMU_UTLB_ADDRESS_ARRAY \| MMU_PAGE_ASSOC_BIT;
	77	data = page \| asid; /* VALID bit is off */
cbaa118e	78	jump_to_uncached();
9d56dd3b	79	__raw_writel(data, addr);
cbaa118e	80	back_to_cached();
1da177e4	81	}
be97d758 PM	82
	83	void local_flush_tlb_all(void)
	84	{
	85	unsigned long flags, status;
	86	int i;
	87
	88	/*
	89	* Flush all the TLB.
	90	*/
	91	local_irq_save(flags);
	92	jump_to_uncached();
	93
	94	status = __raw_readl(MMUCR);
	95	status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
	96
	97	if (status == 0)
	98	status = MMUCR_URB_NENTRIES;
	99
	100	for (i = 0; i < status; i++)
	101	__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY \| (i << 8));
	102
	103	for (i = 0; i < 4; i++)
	104	__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY \| (i << 8));
	105
	106	back_to_cached();
	107	ctrl_barrier();
	108	local_irq_restore(flags);
	109	}