[deliverable/linux.git] / arch / sparc / include / asm / cache.h

/* cache.h:  Cache specific code for the Sparc.  These include flushing
 *           and direct tag/data line access.
 *
 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
 */

#ifndef _SPARC_CACHE_H
#define _SPARC_CACHE_H

#define ARCH_SLAB_MINALIGN	__alignof__(unsigned long long)

#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES 32

#ifdef CONFIG_SPARC32
#define SMP_CACHE_BYTES_SHIFT 5
#else
#define SMP_CACHE_BYTES_SHIFT 6
#endif

#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)

#define __read_mostly __attribute__((__section__(".data..read_mostly")))

#ifdef CONFIG_SPARC32
#include <asm/asi.h>

/* Direct access to the instruction cache is provided through and
 * alternate address space.  The IDC bit must be off in the ICCR on
 * HyperSparcs for these accesses to work.  The code below does not do
 * any checking, the caller must do so.  These routines are for
 * diagnostics only, but could end up being useful.  Use with care.
 * Also, you are asking for trouble if you execute these in one of the
 * three instructions following a %asr/%psr access or modification.
 */

/* First, cache-tag access. */
static inline unsigned int get_icache_tag(int setnum, int tagnum)
{
	unsigned int vaddr, retval;

	vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
			     "=r" (retval) :
			     "r" (vaddr), "i" (ASI_M_TXTC_TAG));
	return retval;
}

static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
{
	unsigned int vaddr;

	vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
			     "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
			     "memory");
}

/* Second cache-data access.  The data is returned two-32bit quantities
 * at a time.
 */
static inline void get_icache_data(int setnum, int tagnum, int subblock,
				       unsigned int *data)
{
	unsigned int value1, value2, vaddr;

	vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
		((subblock&0x3) << 3);
	__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
			     "or %%g0, %%g2, %0\n\t"
			     "or %%g0, %%g3, %1\n\t" :
			     "=r" (value1), "=r" (value2) :
			     "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
			     "g2", "g3");
	data[0] = value1; data[1] = value2;
}

static inline void put_icache_data(int setnum, int tagnum, int subblock,
				       unsigned int *data)
{
	unsigned int value1, value2, vaddr;

	vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
		((subblock&0x3) << 3);
	value1 = data[0]; value2 = data[1];
	__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
			     "or %%g0, %1, %%g3\n\t"
			     "stda %%g2, [%2] %3\n\t" : :
			     "r" (value1), "r" (value2), 
			     "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
			     "g2", "g3", "memory" /* no joke */);
}

/* Different types of flushes with the ICACHE.  Some of the flushes
 * affect both the ICACHE and the external cache.  Others only clear
 * the ICACHE entries on the cpu itself.  V8's (most) allow
 * granularity of flushes on the packet (element in line), whole line,
 * and entire cache (ie. all lines) level.  The ICACHE only flushes are
 * ROSS HyperSparc specific and are in ross.h
 */

/* Flushes which clear out both the on-chip and external caches */
static inline void flush_ei_page(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
			     "memory");
}

static inline void flush_ei_seg(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_SEG) :
			     "memory");
}

static inline void flush_ei_region(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_REGION) :
			     "memory");
}

static inline void flush_ei_ctx(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_CTX) :
			     "memory");
}

static inline void flush_ei_user(unsigned int addr)
{
	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
			     "r" (addr), "i" (ASI_M_FLUSH_USER) :
			     "memory");
}
#endif /* CONFIG_SPARC32 */

#endif /* !(_SPARC_CACHE_H) */
Commit	Line	Data
d113fcd9	1	/* cache.h: Cache specific code for the Sparc. These include flushing
1da177e4 LT	2	* and direct tag/data line access.
1da177e4 LT	3	*
d113fcd9	4	* Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
1da177e4 LT	5	*/
	6
	7	#ifndef _SPARC_CACHE_H
	8	#define _SPARC_CACHE_H
	9
273fca0e DM	10	#define ARCH_SLAB_MINALIGN __alignof__(unsigned long long)
273fca0e DM	11
1da177e4 LT	12	#define L1_CACHE_SHIFT 5
1da177e4 LT	13	#define L1_CACHE_BYTES 32
1da177e4	14
d113fcd9 DM	15	#ifdef CONFIG_SPARC32
	16	#define SMP_CACHE_BYTES_SHIFT 5
	17	#else
	18	#define SMP_CACHE_BYTES_SHIFT 6
	19	#endif
	20
	21	#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
	22
54cb27a7	23	#define __read_mostly __attribute__((__section__(".data..read_mostly")))
d113fcd9 DM	24
	25	#ifdef CONFIG_SPARC32
	26	#include <asm/asi.h>
1da177e4 LT	27
	28	/* Direct access to the instruction cache is provided through and
	29	* alternate address space. The IDC bit must be off in the ICCR on
	30	* HyperSparcs for these accesses to work. The code below does not do
	31	* any checking, the caller must do so. These routines are for
	32	* diagnostics only, but could end up being useful. Use with care.
	33	* Also, you are asking for trouble if you execute these in one of the
	34	* three instructions following a %asr/%psr access or modification.
	35	*/
	36
	37	/* First, cache-tag access. */
3115624e	38	static inline unsigned int get_icache_tag(int setnum, int tagnum)
1da177e4 LT	39	{
	40	unsigned int vaddr, retval;
	41
	42	vaddr = ((setnum&1) << 12) \| ((tagnum&0x7f) << 5);
	43	__asm__ __volatile__("lda [%1] %2, %0\n\t" :
	44	"=r" (retval) :
	45	"r" (vaddr), "i" (ASI_M_TXTC_TAG));
	46	return retval;
	47	}
	48
3115624e	49	static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
1da177e4 LT	50	{
	51	unsigned int vaddr;
	52
	53	vaddr = ((setnum&1) << 12) \| ((tagnum&0x7f) << 5);
	54	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
	55	"r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
	56	"memory");
	57	}
	58
	59	/* Second cache-data access. The data is returned two-32bit quantities
	60	* at a time.
	61	*/
3115624e	62	static inline void get_icache_data(int setnum, int tagnum, int subblock,
1da177e4 LT	63	unsigned int *data)
	64	{
	65	unsigned int value1, value2, vaddr;
	66
	67	vaddr = ((setnum&0x1) << 12) \| ((tagnum&0x7f) << 5) \|
	68	((subblock&0x3) << 3);
	69	__asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
	70	"or %%g0, %%g2, %0\n\t"
	71	"or %%g0, %%g3, %1\n\t" :
	72	"=r" (value1), "=r" (value2) :
	73	"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
	74	"g2", "g3");
	75	data[0] = value1; data[1] = value2;
	76	}
	77
3115624e	78	static inline void put_icache_data(int setnum, int tagnum, int subblock,
1da177e4 LT	79	unsigned int *data)
	80	{
	81	unsigned int value1, value2, vaddr;
	82
	83	vaddr = ((setnum&0x1) << 12) \| ((tagnum&0x7f) << 5) \|
	84	((subblock&0x3) << 3);
	85	value1 = data[0]; value2 = data[1];
	86	__asm__ __volatile__("or %%g0, %0, %%g2\n\t"
	87	"or %%g0, %1, %%g3\n\t"
	88	"stda %%g2, [%2] %3\n\t" : :
	89	"r" (value1), "r" (value2),
	90	"r" (vaddr), "i" (ASI_M_TXTC_DATA) :
	91	"g2", "g3", "memory" /* no joke */);
	92	}
	93
	94	/* Different types of flushes with the ICACHE. Some of the flushes
	95	* affect both the ICACHE and the external cache. Others only clear
	96	* the ICACHE entries on the cpu itself. V8's (most) allow
	97	* granularity of flushes on the packet (element in line), whole line,
	98	* and entire cache (ie. all lines) level. The ICACHE only flushes are
	99	* ROSS HyperSparc specific and are in ross.h
	100	*/
	101
	102	/* Flushes which clear out both the on-chip and external caches */
3115624e	103	static inline void flush_ei_page(unsigned int addr)
1da177e4 LT	104	{
	105	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	106	"r" (addr), "i" (ASI_M_FLUSH_PAGE) :
	107	"memory");
	108	}
	109
3115624e	110	static inline void flush_ei_seg(unsigned int addr)
1da177e4 LT	111	{
	112	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	113	"r" (addr), "i" (ASI_M_FLUSH_SEG) :
	114	"memory");
	115	}
	116
3115624e	117	static inline void flush_ei_region(unsigned int addr)
1da177e4 LT	118	{
	119	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	120	"r" (addr), "i" (ASI_M_FLUSH_REGION) :
	121	"memory");
	122	}
	123
3115624e	124	static inline void flush_ei_ctx(unsigned int addr)
1da177e4 LT	125	{
	126	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	127	"r" (addr), "i" (ASI_M_FLUSH_CTX) :
	128	"memory");
	129	}
	130
3115624e	131	static inline void flush_ei_user(unsigned int addr)
1da177e4 LT	132	{
	133	__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
	134	"r" (addr), "i" (ASI_M_FLUSH_USER) :
	135	"memory");
	136	}
d113fcd9	137	#endif /* CONFIG_SPARC32 */
1da177e4 LT	138
1da177e4 LT	139	#endif /* !(_SPARC_CACHE_H) */