Commit | Line | Data |
---|---|---|
a00736e9 SR |
1 | #ifndef _SPARC64_DCU_H |
2 | #define _SPARC64_DCU_H | |
3 | ||
4 | #include <linux/const.h> | |
5 | ||
6 | /* UltraSparc-III Data Cache Unit Control Register */ | |
7 | #define DCU_CP _AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu */ | |
8 | #define DCU_CV _AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu */ | |
9 | #define DCU_ME _AC(0x0000800000000000,UL) /* NC-store Merging Enable */ | |
10 | #define DCU_RE _AC(0x0000400000000000,UL) /* RAW bypass Enable */ | |
11 | #define DCU_PE _AC(0x0000200000000000,UL) /* PCache Enable */ | |
12 | #define DCU_HPE _AC(0x0000100000000000,UL) /* HW prefetch Enable */ | |
13 | #define DCU_SPE _AC(0x0000080000000000,UL) /* SW prefetch Enable */ | |
14 | #define DCU_SL _AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/ | |
15 | #define DCU_WE _AC(0x0000020000000000,UL) /* WCache enable */ | |
16 | #define DCU_PM _AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask */ | |
17 | #define DCU_VM _AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask */ | |
18 | #define DCU_PR _AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable */ | |
19 | #define DCU_PW _AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/ | |
20 | #define DCU_VR _AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable */ | |
21 | #define DCU_VW _AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/ | |
22 | #define DCU_DM _AC(0x0000000000000008,UL) /* DMMU Enable */ | |
23 | #define DCU_IM _AC(0x0000000000000004,UL) /* IMMU Enable */ | |
24 | #define DCU_DC _AC(0x0000000000000002,UL) /* Data Cache Enable */ | |
25 | #define DCU_IC _AC(0x0000000000000001,UL) /* Instruction Cache Enable */ | |
26 | ||
27 | #endif /* _SPARC64_DCU_H */ |