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f5e706ad SR |
1 | #ifndef ___ASM_SPARC_DMA_MAPPING_H |
2 | #define ___ASM_SPARC_DMA_MAPPING_H | |
d6986415 FT |
3 | |
4 | #include <linux/scatterlist.h> | |
5 | #include <linux/mm.h> | |
02f7a189 | 6 | #include <linux/dma-debug.h> |
b9f69f4f FT |
7 | |
8 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | |
9 | ||
10 | extern int dma_supported(struct device *dev, u64 mask); | |
11 | extern int dma_set_mask(struct device *dev, u64 dma_mask); | |
12 | ||
d6986415 FT |
13 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
14 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | |
15 | #define dma_is_consistent(d, h) (1) | |
16 | ||
ee664a92 FT |
17 | extern struct dma_map_ops *dma_ops, pci32_dma_ops; |
18 | extern struct bus_type pci_bus_type; | |
d6986415 | 19 | |
02f7a189 | 20 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) |
d6986415 | 21 | { |
ee664a92 FT |
22 | #if defined(CONFIG_SPARC32) && defined(CONFIG_PCI) |
23 | if (dev->bus == &pci_bus_type) | |
24 | return &pci32_dma_ops; | |
25 | #endif | |
02f7a189 | 26 | return dma_ops; |
d6986415 FT |
27 | } |
28 | ||
02f7a189 | 29 | #include <asm-generic/dma-mapping-common.h> |
d6986415 | 30 | |
02f7a189 FT |
31 | static inline void *dma_alloc_coherent(struct device *dev, size_t size, |
32 | dma_addr_t *dma_handle, gfp_t flag) | |
d6986415 | 33 | { |
02f7a189 | 34 | struct dma_map_ops *ops = get_dma_ops(dev); |
451d7400 | 35 | void *cpu_addr; |
d6986415 | 36 | |
451d7400 FT |
37 | cpu_addr = ops->alloc_coherent(dev, size, dma_handle, flag); |
38 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
39 | return cpu_addr; | |
d6986415 | 40 | } |
b9f69f4f | 41 | |
02f7a189 FT |
42 | static inline void dma_free_coherent(struct device *dev, size_t size, |
43 | void *cpu_addr, dma_addr_t dma_handle) | |
b9f69f4f | 44 | { |
02f7a189 | 45 | struct dma_map_ops *ops = get_dma_ops(dev); |
b9f69f4f | 46 | |
451d7400 | 47 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); |
02f7a189 | 48 | ops->free_coherent(dev, size, cpu_addr, dma_handle); |
b9f69f4f FT |
49 | } |
50 | ||
d6986415 FT |
51 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
52 | { | |
53 | return (dma_addr == DMA_ERROR_CODE); | |
54 | } | |
55 | ||
56 | static inline int dma_get_cache_alignment(void) | |
57 | { | |
58 | /* | |
59 | * no easy way to get cache size on all processors, so return | |
60 | * the maximum possible, to be safe | |
61 | */ | |
62 | return (1 << INTERNODE_CACHE_SHIFT); | |
63 | } | |
64 | ||
f5e706ad | 65 | #endif |