projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b69416b5 | 1 | /* fhc.h: FHC and Clock board register definitions. |
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2 | * |
| 3 | * Copyright (C) 1997, 1999 David S. Miller (davem@redhat.com) | |
| 4 | */ | |
| 5 | ||
| 6 | #ifndef _SPARC64_FHC_H | |
| 7 | #define _SPARC64_FHC_H | |
| 8 | ||
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9 | /* Clock board register offsets. */ |
| 10 | #define CLOCK_CTRL 0x00UL /* Main control */ | |
| 11 | #define CLOCK_STAT1 0x10UL /* Status one */ | |
| 12 | #define CLOCK_STAT2 0x20UL /* Status two */ | |
| 13 | #define CLOCK_PWRSTAT 0x30UL /* Power status */ | |
| 14 | #define CLOCK_PWRPRES 0x40UL /* Power presence */ | |
| 15 | #define CLOCK_TEMP 0x50UL /* Temperature */ | |
| 16 | #define CLOCK_IRQDIAG 0x60UL /* IRQ diagnostics */ | |
| 17 | #define CLOCK_PWRSTAT2 0x70UL /* Power status two */ | |
| 18 | ||
| 19 | #define CLOCK_CTRL_LLED 0x04 /* Left LED, 0 == on */ | |
| 20 | #define CLOCK_CTRL_MLED 0x02 /* Mid LED, 1 == on */ | |
| 21 | #define CLOCK_CTRL_RLED 0x01 /* RIght LED, 1 == on */ | |
| 22 | ||
| a00736e9 | 23 | /* Firehose controller register offsets */ |
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24 | #define FHC_PREGS_ID 0x00UL /* FHC ID */ |
| 25 | #define FHC_ID_VERS 0xf0000000 /* Version of this FHC */ | |
| 26 | #define FHC_ID_PARTID 0x0ffff000 /* Part ID code (0x0f9f == FHC) */ | |
| 27 | #define FHC_ID_MANUF 0x0000007e /* Manufacturer (0x3e == SUN's JEDEC)*/ | |
| 28 | #define FHC_ID_RESV 0x00000001 /* Read as one */ | |
| 29 | #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */ | |
| 30 | #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */ | |
| 31 | #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */ | |
| 32 | #define FHC_RCS_SXIR 0x20000000 /* Last reset was sw XIR reset */ | |
| 33 | #define FHC_RCS_BPOR 0x10000000 /* Last reset was due to POR button */ | |
| 34 | #define FHC_RCS_BXIR 0x08000000 /* Last reset was due to XIR button */ | |
| 35 | #define FHC_RCS_WEVENT 0x04000000 /* CPU reset was due to wakeup event */ | |
| 36 | #define FHC_RCS_CFATAL 0x02000000 /* Centerplane Fatal Error signalled */ | |
| 37 | #define FHC_RCS_FENAB 0x01000000 /* Fatal errors elicit system reset */ | |
| 38 | #define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */ | |
| 39 | #define FHC_CONTROL_ICS 0x00100000 /* Ignore Centerplane Signals */ | |
| 40 | #define FHC_CONTROL_FRST 0x00080000 /* Fatal Error Reset Enable */ | |
| 41 | #define FHC_CONTROL_LFAT 0x00040000 /* AC/DC signalled a local error */ | |
| 42 | #define FHC_CONTROL_SLINE 0x00010000 /* Firmware Synchronization Line */ | |
| 43 | #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */ | |
| 44 | #define FHC_CONTROL_POFF 0x00004000 /* AC/DC Controller PLL Disable */ | |
| 45 | #define FHC_CONTROL_FOFF 0x00002000 /* FHC Controller PLL Disable */ | |
| 46 | #define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */ | |
| 47 | #define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */ | |
| 48 | #define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */ | |
| 49 | #define FHC_CONTROL_IXIST 0x00000200 /* 0=FHC tells clock board it exists */ | |
| 50 | #define FHC_CONTROL_XMSTR 0x00000100 /* 1=Causes this FHC to be XIR master*/ | |
| 51 | #define FHC_CONTROL_LLED 0x00000040 /* 0=Left LED ON */ | |
| 52 | #define FHC_CONTROL_MLED 0x00000020 /* 1=Middle LED ON */ | |
| 53 | #define FHC_CONTROL_RLED 0x00000010 /* 1=Right LED */ | |
| 54 | #define FHC_CONTROL_BPINS 0x00000003 /* Spare Bidirectional Pins */ | |
| 55 | #define FHC_PREGS_BSR 0x30UL /* FHC Board Status Register */ | |
| 56 | #define FHC_BSR_DA64 0x00040000 /* Port A: 0=128bit 1=64bit data path */ | |
| 57 | #define FHC_BSR_DB64 0x00020000 /* Port B: 0=128bit 1=64bit data path */ | |
| 58 | #define FHC_BSR_BID 0x0001e000 /* Board ID */ | |
| 59 | #define FHC_BSR_SA 0x00001c00 /* Port A UPA Speed (from the pins) */ | |
| 60 | #define FHC_BSR_SB 0x00000380 /* Port B UPA Speed (from the pins) */ | |
| 61 | #define FHC_BSR_NDIAG 0x00000040 /* Not in Diag Mode */ | |
| 62 | #define FHC_BSR_NTBED 0x00000020 /* Not in TestBED Mode */ | |
| 63 | #define FHC_BSR_NIA 0x0000001c /* Jumper, bit 18 in PROM space */ | |
| 64 | #define FHC_BSR_SI 0x00000001 /* Spare input pin value */ | |
| 65 | #define FHC_PREGS_ECC 0x40UL /* FHC ECC Control Register (16 bits) */ | |
| 66 | #define FHC_PREGS_JCTRL 0xf0UL /* FHC JTAG Control Register */ | |
| 67 | #define FHC_JTAG_CTRL_MENAB 0x80000000 /* Indicates this is JTAG Master */ | |
| 68 | #define FHC_JTAG_CTRL_MNONE 0x40000000 /* Indicates no JTAG Master present */ | |
| 69 | #define FHC_PREGS_JCMD 0x100UL /* FHC JTAG Command Register */ | |
| a00736e9 | 70 | #define FHC_IREG_IGN 0x00UL /* This FHC's IGN */ |
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71 | #define FHC_FFREGS_IMAP 0x00UL /* FHC Fanfail IMAP */ |
| 72 | #define FHC_FFREGS_ICLR 0x10UL /* FHC Fanfail ICLR */ | |
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73 | #define FHC_SREGS_IMAP 0x00UL /* FHC System IMAP */ |
| 74 | #define FHC_SREGS_ICLR 0x10UL /* FHC System ICLR */ | |
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75 | #define FHC_UREGS_IMAP 0x00UL /* FHC Uart IMAP */ |
| 76 | #define FHC_UREGS_ICLR 0x10UL /* FHC Uart ICLR */ | |
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77 | #define FHC_TREGS_IMAP 0x00UL /* FHC TOD IMAP */ |
| 78 | #define FHC_TREGS_ICLR 0x10UL /* FHC TOD ICLR */ | |
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79 | |
| 80 | #endif /* !(_SPARC64_FHC_H) */ |