[deliverable/linux.git] / arch / sparc / include / asm / io_64.h

#ifndef __SPARC64_IO_H
#define __SPARC64_IO_H

#include <linux/kernel.h>
#include <linux/compiler.h>
#include <linux/types.h>

#include <asm/page.h>      /* IO address mapping routines need this */
#include <asm/asi.h>
#include <asm-generic/pci_iomap.h>

/* PC crapola... */
#define __SLOW_DOWN_IO	do { } while (0)
#define SLOW_DOWN_IO	do { } while (0)

/* BIO layer definitions. */
extern unsigned long kern_base, kern_size;

static inline u8 _inb(unsigned long addr)
{
	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

static inline u16 _inw(unsigned long addr)
{
	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

static inline u32 _inl(unsigned long addr)
{
	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

static inline void _outb(u8 b, unsigned long addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

static inline void _outw(u16 w, unsigned long addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

static inline void _outl(u32 l, unsigned long addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

#define inb(__addr)		(_inb((unsigned long)(__addr)))
#define inw(__addr)		(_inw((unsigned long)(__addr)))
#define inl(__addr)		(_inl((unsigned long)(__addr)))
#define outb(__b, __addr)	(_outb((u8)(__b), (unsigned long)(__addr)))
#define outw(__w, __addr)	(_outw((u16)(__w), (unsigned long)(__addr)))
#define outl(__l, __addr)	(_outl((u32)(__l), (unsigned long)(__addr)))

#define inb_p(__addr) 		inb(__addr)
#define outb_p(__b, __addr)	outb(__b, __addr)
#define inw_p(__addr)		inw(__addr)
#define outw_p(__w, __addr)	outw(__w, __addr)
#define inl_p(__addr)		inl(__addr)
#define outl_p(__l, __addr)	outl(__l, __addr)

void outsb(unsigned long, const void *, unsigned long);
void outsw(unsigned long, const void *, unsigned long);
void outsl(unsigned long, const void *, unsigned long);
void insb(unsigned long, void *, unsigned long);
void insw(unsigned long, void *, unsigned long);
void insl(unsigned long, void *, unsigned long);

static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
{
	insb((unsigned long __force)port, buf, count);
}
static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
{
	insw((unsigned long __force)port, buf, count);
}

static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
{
	insl((unsigned long __force)port, buf, count);
}

static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsb((unsigned long __force)port, buf, count);
}

static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsw((unsigned long __force)port, buf, count);
}

static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
{
	outsl((unsigned long __force)port, buf, count);
}

/* Memory functions, same as I/O accesses on Ultra. */
static inline u8 _readb(const volatile void __iomem *addr)
{	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
	return ret;
}

static inline u16 _readw(const volatile void __iomem *addr)
{	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

static inline u32 _readl(const volatile void __iomem *addr)
{	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

static inline u64 _readq(const volatile void __iomem *addr)
{	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");

	return ret;
}

static inline void _writeb(u8 b, volatile void __iomem *addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

static inline void _writew(u16 w, volatile void __iomem *addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

static inline void _writel(u32 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

static inline void _writeq(u64 q, volatile void __iomem *addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
			     : "memory");
}

#define readb(__addr)		_readb(__addr)
#define readw(__addr)		_readw(__addr)
#define readl(__addr)		_readl(__addr)
#define readq(__addr)		_readq(__addr)
#define readb_relaxed(__addr)	_readb(__addr)
#define readw_relaxed(__addr)	_readw(__addr)
#define readl_relaxed(__addr)	_readl(__addr)
#define readq_relaxed(__addr)	_readq(__addr)
#define writeb(__b, __addr)	_writeb(__b, __addr)
#define writew(__w, __addr)	_writew(__w, __addr)
#define writel(__l, __addr)	_writel(__l, __addr)
#define writeq(__q, __addr)	_writeq(__q, __addr)

/* Now versions without byte-swapping. */
static inline u8 _raw_readb(unsigned long addr)
{
	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline u16 _raw_readw(unsigned long addr)
{
	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline u32 _raw_readl(unsigned long addr)
{
	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline u64 _raw_readq(unsigned long addr)
{
	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));

	return ret;
}

static inline void _raw_writeb(u8 b, unsigned long addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static inline void _raw_writew(u16 w, unsigned long addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static inline void _raw_writel(u32 l, unsigned long addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

static inline void _raw_writeq(u64 q, unsigned long addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
			     : /* no outputs */
			     : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}

#define __raw_readb(__addr)		(_raw_readb((unsigned long)(__addr)))
#define __raw_readw(__addr)		(_raw_readw((unsigned long)(__addr)))
#define __raw_readl(__addr)		(_raw_readl((unsigned long)(__addr)))
#define __raw_readq(__addr)		(_raw_readq((unsigned long)(__addr)))
#define __raw_writeb(__b, __addr)	(_raw_writeb((u8)(__b), (unsigned long)(__addr)))
#define __raw_writew(__w, __addr)	(_raw_writew((u16)(__w), (unsigned long)(__addr)))
#define __raw_writel(__l, __addr)	(_raw_writel((u32)(__l), (unsigned long)(__addr)))
#define __raw_writeq(__q, __addr)	(_raw_writeq((u64)(__q), (unsigned long)(__addr)))

/* Valid I/O Space regions are anywhere, because each PCI bus supported
 * can live in an arbitrary area of the physical address range.
 */
#define IO_SPACE_LIMIT 0xffffffffffffffffUL

/* Now, SBUS variants, only difference from PCI is that we do
 * not use little-endian ASIs.
 */
static inline u8 _sbus_readb(const volatile void __iomem *addr)
{
	u8 ret;

	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");

	return ret;
}

static inline u16 _sbus_readw(const volatile void __iomem *addr)
{
	u16 ret;

	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");

	return ret;
}

static inline u32 _sbus_readl(const volatile void __iomem *addr)
{
	u32 ret;

	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");

	return ret;
}

static inline u64 _sbus_readq(const volatile void __iomem *addr)
{
	u64 ret;

	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
			     : "=r" (ret)
			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");

	return ret;
}

static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
{
	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
			     : /* no outputs */
			     : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");
}

static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
{
	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
			     : /* no outputs */
			     : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");
}

static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");
}

static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
{
	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
			     : /* no outputs */
			     : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
			     : "memory");
}

#define sbus_readb(__addr)		_sbus_readb(__addr)
#define sbus_readw(__addr)		_sbus_readw(__addr)
#define sbus_readl(__addr)		_sbus_readl(__addr)
#define sbus_readq(__addr)		_sbus_readq(__addr)
#define sbus_writeb(__b, __addr)	_sbus_writeb(__b, __addr)
#define sbus_writew(__w, __addr)	_sbus_writew(__w, __addr)
#define sbus_writel(__l, __addr)	_sbus_writel(__l, __addr)
#define sbus_writeq(__l, __addr)	_sbus_writeq(__l, __addr)

static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
	while(n--) {
		sbus_writeb(c, dst);
		dst++;
	}
}

#define sbus_memset_io(d,c,sz)	_sbus_memset_io(d,c,sz)

static inline void
_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
	volatile void __iomem *d = dst;

	while (n--) {
		writeb(c, d);
		d++;
	}
}

#define memset_io(d,c,sz)	_memset_io(d,c,sz)

static inline void
_sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
		    __kernel_size_t n)
{
	char *d = dst;

	while (n--) {
		char tmp = sbus_readb(src);
		*d++ = tmp;
		src++;
	}
}

#define sbus_memcpy_fromio(d, s, sz)	_sbus_memcpy_fromio(d, s, sz)

static inline void
_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
{
	char *d = dst;

	while (n--) {
		char tmp = readb(src);
		*d++ = tmp;
		src++;
	}
}

#define memcpy_fromio(d,s,sz)	_memcpy_fromio(d,s,sz)

static inline void
_sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
		  __kernel_size_t n)
{
	const char *s = src;
	volatile void __iomem *d = dst;

	while (n--) {
		char tmp = *s++;
		sbus_writeb(tmp, d);
		d++;
	}
}

#define sbus_memcpy_toio(d, s, sz)	_sbus_memcpy_toio(d, s, sz)

static inline void
_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
{
	const char *s = src;
	volatile void __iomem *d = dst;

	while (n--) {
		char tmp = *s++;
		writeb(tmp, d);
		d++;
	}
}

#define memcpy_toio(d,s,sz)	_memcpy_toio(d,s,sz)

#define mmiowb()

#ifdef __KERNEL__

/* On sparc64 we have the whole physical IO address space accessible
 * using physically addressed loads and stores, so this does nothing.
 */
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
	return (void __iomem *)offset;
}

#define ioremap_nocache(X,Y)		ioremap((X),(Y))
#define ioremap_wc(X,Y)			ioremap((X),(Y))

static inline void iounmap(volatile void __iomem *addr)
{
}

#define ioread8(X)			readb(X)
#define ioread16(X)			readw(X)
#define ioread16be(X)			__raw_readw(X)
#define ioread32(X)			readl(X)
#define ioread32be(X)			__raw_readl(X)
#define iowrite8(val,X)			writeb(val,X)
#define iowrite16(val,X)		writew(val,X)
#define iowrite16be(val,X)		__raw_writew(val,X)
#define iowrite32(val,X)		writel(val,X)
#define iowrite32be(val,X)		__raw_writel(val,X)

/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr);
void ioport_unmap(void __iomem *);

/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
void pci_iounmap(struct pci_dev *dev, void __iomem *);

static inline int sbus_can_dma_64bit(void)
{
	return 1;
}
static inline int sbus_can_burst64(void)
{
	return 1;
}
struct device;
void sbus_set_sbus64(struct device *, int);

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#endif

#endif /* !(__SPARC64_IO_H) */
Commit	Line	Data
f5e706ad SR	1	#ifndef __SPARC64_IO_H
	2	#define __SPARC64_IO_H
	3
	4	#include <linux/kernel.h>
	5	#include <linux/compiler.h>
	6	#include <linux/types.h>
	7
	8	#include <asm/page.h> /* IO address mapping routines need this */
f5e706ad	9	#include <asm/asi.h>
a21a2fd4	10	#include <asm-generic/pci_iomap.h>
f5e706ad SR	11
	12	/* PC crapola... */
	13	#define __SLOW_DOWN_IO do { } while (0)
	14	#define SLOW_DOWN_IO do { } while (0)
	15
	16	/* BIO layer definitions. */
	17	extern unsigned long kern_base, kern_size;
f5e706ad SR	18
	19	static inline u8 _inb(unsigned long addr)
	20	{
	21	u8 ret;
	22
	23	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
	24	: "=r" (ret)
	25	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	26	: "memory");
	27
	28	return ret;
	29	}
	30
	31	static inline u16 _inw(unsigned long addr)
	32	{
	33	u16 ret;
	34
	35	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
	36	: "=r" (ret)
	37	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	38	: "memory");
	39
	40	return ret;
	41	}
	42
	43	static inline u32 _inl(unsigned long addr)
	44	{
	45	u32 ret;
	46
	47	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
	48	: "=r" (ret)
	49	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	50	: "memory");
	51
	52	return ret;
	53	}
	54
	55	static inline void _outb(u8 b, unsigned long addr)
	56	{
	57	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
	58	: /* no outputs */
	59	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	60	: "memory");
	61	}
	62
	63	static inline void _outw(u16 w, unsigned long addr)
	64	{
	65	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
	66	: /* no outputs */
	67	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	68	: "memory");
	69	}
	70
	71	static inline void _outl(u32 l, unsigned long addr)
	72	{
	73	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
	74	: /* no outputs */
	75	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	76	: "memory");
	77	}
	78
	79	#define inb(__addr) (_inb((unsigned long)(__addr)))
	80	#define inw(__addr) (_inw((unsigned long)(__addr)))
	81	#define inl(__addr) (_inl((unsigned long)(__addr)))
82	#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
83	#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
84	#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
85
86	#define inb_p(__addr) inb(__addr)
87	#define outb_p(__b, __addr) outb(__b, __addr)
88	#define inw_p(__addr) inw(__addr)
89	#define outw_p(__w, __addr) outw(__w, __addr)
90	#define inl_p(__addr) inl(__addr)
91	#define outl_p(__l, __addr) outl(__l, __addr)
92
f05a6865 SR	93	void outsb(unsigned long, const void *, unsigned long);
	94	void outsw(unsigned long, const void *, unsigned long);
	95	void outsl(unsigned long, const void *, unsigned long);
	96	void insb(unsigned long, void *, unsigned long);
	97	void insw(unsigned long, void *, unsigned long);
	98	void insl(unsigned long, void *, unsigned long);
f5e706ad SR	99
	100	static inline void ioread8_rep(void __iomem port, void buf, unsigned long count)
	101	{
	102	insb((unsigned long __force)port, buf, count);
	103	}
	104	static inline void ioread16_rep(void __iomem port, void buf, unsigned long count)
	105	{
	106	insw((unsigned long __force)port, buf, count);
	107	}
	108
	109	static inline void ioread32_rep(void __iomem port, void buf, unsigned long count)
	110	{
	111	insl((unsigned long __force)port, buf, count);
	112	}
	113
	114	static inline void iowrite8_rep(void __iomem port, const void buf, unsigned long count)
	115	{
	116	outsb((unsigned long __force)port, buf, count);
	117	}
	118
	119	static inline void iowrite16_rep(void __iomem port, const void buf, unsigned long count)
	120	{
	121	outsw((unsigned long __force)port, buf, count);
	122	}
	123
	124	static inline void iowrite32_rep(void __iomem port, const void buf, unsigned long count)
	125	{
	126	outsl((unsigned long __force)port, buf, count);
	127	}
	128
	129	/* Memory functions, same as I/O accesses on Ultra. */
	130	static inline u8 _readb(const volatile void __iomem *addr)
	131	{ u8 ret;
	132
	133	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
	134	: "=r" (ret)
	135	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	136	: "memory");
	137	return ret;
	138	}
	139
	140	static inline u16 _readw(const volatile void __iomem *addr)
	141	{ u16 ret;
	142
	143	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
	144	: "=r" (ret)
	145	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	146	: "memory");
	147
	148	return ret;
	149	}
	150
	151	static inline u32 _readl(const volatile void __iomem *addr)
	152	{ u32 ret;
	153
	154	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
	155	: "=r" (ret)
	156	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
	157	: "memory");
	158
	159	return ret;
	160	}
	161
	162	static inline u64 _readq(const volatile void __iomem *addr)
163	{ u64 ret;
164
165	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
166	: "=r" (ret)
167	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
168	: "memory");
169
170	return ret;
171	}
172
173	static inline void _writeb(u8 b, volatile void __iomem *addr)
174	{
175	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
176	: /* no outputs */
177	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
178	: "memory");
179	}
180
181	static inline void _writew(u16 w, volatile void __iomem *addr)
182	{
183	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
184	: /* no outputs */
185	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
186	: "memory");
187	}
188
189	static inline void _writel(u32 l, volatile void __iomem *addr)
190	{
191	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
192	: /* no outputs */
193	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
194	: "memory");
195	}
196
197	static inline void _writeq(u64 q, volatile void __iomem *addr)
198	{
199	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
200	: /* no outputs */
201	: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
202	: "memory");
203	}
204
205	#define readb(__addr) _readb(__addr)
206	#define readw(__addr) _readw(__addr)
207	#define readl(__addr) _readl(__addr)
208	#define readq(__addr) _readq(__addr)
209	#define readb_relaxed(__addr) _readb(__addr)
210	#define readw_relaxed(__addr) _readw(__addr)
211	#define readl_relaxed(__addr) _readl(__addr)
212	#define readq_relaxed(__addr) _readq(__addr)
213	#define writeb(__b, __addr) _writeb(__b, __addr)
214	#define writew(__w, __addr) _writew(__w, __addr)
215	#define writel(__l, __addr) _writel(__l, __addr)
216	#define writeq(__q, __addr) _writeq(__q, __addr)
217
218	/* Now versions without byte-swapping. */
219	static inline u8 _raw_readb(unsigned long addr)
220	{
221	u8 ret;
222
223	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
224	: "=r" (ret)
225	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
226
227	return ret;
228	}
229
230	static inline u16 _raw_readw(unsigned long addr)
231	{
232	u16 ret;
233
234	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
235	: "=r" (ret)
236	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
237
238	return ret;
239	}
240
241	static inline u32 _raw_readl(unsigned long addr)
242	{
243	u32 ret;
244
245	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
246	: "=r" (ret)
247	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
248
249	return ret;
250	}
251
252	static inline u64 _raw_readq(unsigned long addr)
253	{
254	u64 ret;
255
256	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
257	: "=r" (ret)
258	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
259
260	return ret;
261	}
262
263	static inline void _raw_writeb(u8 b, unsigned long addr)
264	{
265	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
266	: /* no outputs */
267	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
268	}
269
270	static inline void _raw_writew(u16 w, unsigned long addr)
271	{
272	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
273	: /* no outputs */
274	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
275	}
276
277	static inline void _raw_writel(u32 l, unsigned long addr)
278	{
279	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
280	: /* no outputs */
281	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
282	}
283
284	static inline void _raw_writeq(u64 q, unsigned long addr)
285	{
286	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
287	: /* no outputs */
288	: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
289	}
290
291	#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
292	#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
293	#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
294	#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
295	#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
296	#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
297	#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
298	#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
299
300	/* Valid I/O Space regions are anywhere, because each PCI bus supported
301	* can live in an arbitrary area of the physical address range.
302	*/
303	#define IO_SPACE_LIMIT 0xffffffffffffffffUL
304
305	/* Now, SBUS variants, only difference from PCI is that we do
306	* not use little-endian ASIs.
307	*/
308	static inline u8 _sbus_readb(const volatile void __iomem *addr)
309	{
310	u8 ret;
311
312	__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
313	: "=r" (ret)
314	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
315	: "memory");
316
317	return ret;
318	}
319
320	static inline u16 _sbus_readw(const volatile void __iomem *addr)
321	{
322	u16 ret;
323
324	__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
325	: "=r" (ret)
326	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
327	: "memory");
328
329	return ret;
330	}
331
332	static inline u32 _sbus_readl(const volatile void __iomem *addr)
333	{
334	u32 ret;
335
336	__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
337	: "=r" (ret)
338	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
339	: "memory");
340
341	return ret;
342	}
343
344	static inline u64 _sbus_readq(const volatile void __iomem *addr)
345	{
346	u64 ret;
347
348	__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
349	: "=r" (ret)
350	: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
351	: "memory");
352
353	return ret;
354	}
355
356	static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
357	{
358	__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
359	: /* no outputs */
360	: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
361	: "memory");
362	}
363
364	static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
365	{
366	__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
367	: /* no outputs */
368	: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
369	: "memory");
370	}
371
372	static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
373	{
374	__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
375	: /* no outputs */
376	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
377	: "memory");
378	}
379
380	static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
381	{
382	__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
383	: /* no outputs */
384	: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
385	: "memory");
386	}
387
388	#define sbus_readb(__addr) _sbus_readb(__addr)
389	#define sbus_readw(__addr) _sbus_readw(__addr)
390	#define sbus_readl(__addr) _sbus_readl(__addr)
391	#define sbus_readq(__addr) _sbus_readq(__addr)
392	#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
393	#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
394	#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
395	#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
396
397	static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
398	{
399	while(n--) {
400	sbus_writeb(c, dst);
401	dst++;
402	}
403	}
404
405	#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
406
407	static inline void
408	_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
409	{
410	volatile void __iomem *d = dst;
411
412	while (n--) {
413	writeb(c, d);
414	d++;
415	}
416	}
417
418	#define memset_io(d,c,sz) _memset_io(d,c,sz)
419
f11b478d JH	420	static inline void
	421	_sbus_memcpy_fromio(void dst, const volatile void __iomem src,
	422	__kernel_size_t n)
	423	{
	424	char *d = dst;
	425
	426	while (n--) {
	427	char tmp = sbus_readb(src);
	428	*d++ = tmp;
	429	src++;
	430	}
	431	}
	432
	433	#define sbus_memcpy_fromio(d, s, sz) _sbus_memcpy_fromio(d, s, sz)
	434
f5e706ad SR	435	static inline void
	436	_memcpy_fromio(void dst, const volatile void __iomem src, __kernel_size_t n)
	437	{
	438	char *d = dst;
	439
	440	while (n--) {
	441	char tmp = readb(src);
	442	*d++ = tmp;
	443	src++;
	444	}
	445	}
	446
	447	#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
	448
f11b478d JH	449	static inline void
	450	_sbus_memcpy_toio(volatile void __iomem dst, const void src,
	451	__kernel_size_t n)
	452	{
	453	const char *s = src;
	454	volatile void __iomem *d = dst;
	455
	456	while (n--) {
	457	char tmp = *s++;
	458	sbus_writeb(tmp, d);
	459	d++;
	460	}
	461	}
	462
	463	#define sbus_memcpy_toio(d, s, sz) _sbus_memcpy_toio(d, s, sz)
	464
f5e706ad SR	465	static inline void
	466	_memcpy_toio(volatile void __iomem dst, const void src, __kernel_size_t n)
	467	{
	468	const char *s = src;
	469	volatile void __iomem *d = dst;
	470
	471	while (n--) {
	472	char tmp = *s++;
	473	writeb(tmp, d);
	474	d++;
	475	}
	476	}
	477
	478	#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
	479
	480	#define mmiowb()
	481
	482	#ifdef __KERNEL__
	483
	484	/* On sparc64 we have the whole physical IO address space accessible
	485	* using physically addressed loads and stores, so this does nothing.
	486	*/
	487	static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
	488	{
	489	return (void __iomem *)offset;
	490	}
	491
	492	#define ioremap_nocache(X,Y) ioremap((X),(Y))
428695b8	493	#define ioremap_wc(X,Y) ioremap((X),(Y))
f5e706ad SR	494
	495	static inline void iounmap(volatile void __iomem *addr)
	496	{
	497	}
	498
	499	#define ioread8(X) readb(X)
	500	#define ioread16(X) readw(X)
1bff4dbb	501	#define ioread16be(X) __raw_readw(X)
f5e706ad	502	#define ioread32(X) readl(X)
1bff4dbb	503	#define ioread32be(X) __raw_readl(X)
f5e706ad SR	504	#define iowrite8(val,X) writeb(val,X)
f5e706ad SR	505	#define iowrite16(val,X) writew(val,X)
1bff4dbb	506	#define iowrite16be(val,X) __raw_writew(val,X)
f5e706ad	507	#define iowrite32(val,X) writel(val,X)
1bff4dbb	508	#define iowrite32be(val,X) __raw_writel(val,X)
f5e706ad SR	509
f5e706ad SR	510	/* Create a virtual mapping cookie for an IO port range */
f05a6865 SR	511	void __iomem *ioport_map(unsigned long port, unsigned int nr);
f05a6865 SR	512	void ioport_unmap(void __iomem *);
f5e706ad SR	513
	514	/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
	515	struct pci_dev;
f05a6865	516	void pci_iounmap(struct pci_dev dev, void __iomem );
f5e706ad	517
63237eeb DM	518	static inline int sbus_can_dma_64bit(void)
	519	{
	520	return 1;
	521	}
	522	static inline int sbus_can_burst64(void)
	523	{
	524	return 1;
	525	}
	526	struct device;
f05a6865	527	void sbus_set_sbus64(struct device *, int);
63237eeb	528
f5e706ad SR	529	/*
	530	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	531	* access
	532	*/
	533	#define xlate_dev_mem_ptr(p) __va(p)
	534
	535	/*
	536	* Convert a virtual cached pointer to an uncached pointer
	537	*/
	538	#define xlate_dev_kmem_ptr(p) p
	539
	540	#endif
	541
	542	#endif /* !(__SPARC64_IO_H) */