sparc: drop use of extern for prototypes in arch/sparc/include/asm
[deliverable/linux.git] / arch / sparc / include / asm / page_64.h
CommitLineData
f5e706ad
SR
1#ifndef _SPARC64_PAGE_H
2#define _SPARC64_PAGE_H
3
4#include <linux/const.h>
5
f5e706ad 6#define PAGE_SHIFT 13
f5e706ad
SR
7
8#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
9#define PAGE_MASK (~(PAGE_SIZE-1))
10
11/* Flushing for D-cache alias handling is only needed if
12 * the page size is smaller than 16K.
13 */
14#if PAGE_SHIFT < 14
15#define DCACHE_ALIASING_POSSIBLE
16#endif
17
37b3a8ff
DM
18#define HPAGE_SHIFT 23
19#define REAL_HPAGE_SHIFT 22
20
21#define REAL_HPAGE_SIZE (_AC(1,UL) << REAL_HPAGE_SHIFT)
f5e706ad 22
9e695d2e 23#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
f5e706ad
SR
24#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
25#define HPAGE_MASK (~(HPAGE_SIZE - 1UL))
26#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
27#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
28#endif
29
30#ifndef __ASSEMBLY__
31
9e695d2e 32#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
0fbebed6 33struct pt_regs;
f05a6865 34void hugetlb_setup(struct pt_regs *regs);
9e695d2e
DM
35#endif
36
b0f1e796
DM
37#define WANT_PAGE_VIRTUAL
38
f05a6865 39void _clear_page(void *page);
f5e706ad
SR
40#define clear_page(X) _clear_page((void *)(X))
41struct page;
f05a6865 42void clear_user_page(void *addr, unsigned long vaddr, struct page *page);
f5e706ad 43#define copy_page(X,Y) memcpy((void *)(X), (void *)(Y), PAGE_SIZE)
f05a6865 44void copy_user_page(void *to, void *from, unsigned long vaddr, struct page *topage);
f5e706ad
SR
45
46/* Unlike sparc32, sparc64's parameter passing API is more
47 * sane in that structures which as small enough are passed
48 * in registers instead of on the stack. Thus, setting
49 * STRICT_MM_TYPECHECKS does not generate worse code so
50 * let's enable it to get the type checking.
51 */
52
53#define STRICT_MM_TYPECHECKS
54
55#ifdef STRICT_MM_TYPECHECKS
56/* These are used to make use of C type-checking.. */
57typedef struct { unsigned long pte; } pte_t;
58typedef struct { unsigned long iopte; } iopte_t;
2b77933c
DM
59typedef struct { unsigned long pmd; } pmd_t;
60typedef struct { unsigned long pgd; } pgd_t;
f5e706ad
SR
61typedef struct { unsigned long pgprot; } pgprot_t;
62
63#define pte_val(x) ((x).pte)
64#define iopte_val(x) ((x).iopte)
65#define pmd_val(x) ((x).pmd)
66#define pgd_val(x) ((x).pgd)
67#define pgprot_val(x) ((x).pgprot)
68
69#define __pte(x) ((pte_t) { (x) } )
70#define __iopte(x) ((iopte_t) { (x) } )
71#define __pmd(x) ((pmd_t) { (x) } )
72#define __pgd(x) ((pgd_t) { (x) } )
73#define __pgprot(x) ((pgprot_t) { (x) } )
74
75#else
76/* .. while these make it easier on the compiler */
77typedef unsigned long pte_t;
78typedef unsigned long iopte_t;
2b77933c
DM
79typedef unsigned long pmd_t;
80typedef unsigned long pgd_t;
f5e706ad
SR
81typedef unsigned long pgprot_t;
82
83#define pte_val(x) (x)
84#define iopte_val(x) (x)
85#define pmd_val(x) (x)
86#define pgd_val(x) (x)
87#define pgprot_val(x) (x)
88
89#define __pte(x) (x)
90#define __iopte(x) (x)
91#define __pmd(x) (x)
92#define __pgd(x) (x)
93#define __pgprot(x) (x)
94
95#endif /* (STRICT_MM_TYPECHECKS) */
96
c460bec7 97typedef pte_t *pgtable_t;
f5e706ad 98
c920745e 99/* These two values define the virtual address space range in which we
2b77933c
DM
100 * must forbid 64-bit user processes from making mappings. It used to
101 * represent precisely the virtual address space hole present in most
102 * early sparc64 chips including UltraSPARC-I. But now it also is
103 * further constrained by the limits of our page tables, which is
104 * 43-bits of virtual address.
c920745e 105 */
2b77933c
DM
106#define SPARC64_VA_HOLE_TOP _AC(0xfffffc0000000000,UL)
107#define SPARC64_VA_HOLE_BOTTOM _AC(0x0000040000000000,UL)
c920745e 108
2b77933c
DM
109/* The next two defines specify the actual exclusion region we
110 * enforce, wherein we use a 4GB red zone on each side of the VA hole.
111 */
c920745e
DM
112#define VA_EXCLUDE_START (SPARC64_VA_HOLE_BOTTOM - (1UL << 32UL))
113#define VA_EXCLUDE_END (SPARC64_VA_HOLE_TOP + (1UL << 32UL))
114
f5e706ad 115#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
c920745e
DM
116 _AC(0x0000000070000000,UL) : \
117 VA_EXCLUDE_END)
f5e706ad
SR
118
119#include <asm-generic/memory_model.h>
120
e0a45e35 121#define PAGE_OFFSET_BY_BITS(X) (-(_AC(1,UL) << (X)))
b2d43834 122extern unsigned long PAGE_OFFSET;
f5e706ad 123
b2d43834 124#endif /* !(__ASSEMBLY__) */
bb7b4353 125
b2d43834
DM
126/* The maximum number of physical memory address bits we support, this
127 * is used to size various tables used to manage kernel TLB misses and
128 * also the sparsemem code.
bb7b4353 129 */
b2d43834 130#define MAX_PHYS_ADDRESS_BITS 47
bb7b4353
DM
131
132/* These two shift counts are used when indexing sparc64_valid_addr_bitmap
133 * and kpte_linear_bitmap.
134 */
135#define ILOG2_4MB 22
136#define ILOG2_256MB 28
137
f5e706ad
SR
138#ifndef __ASSEMBLY__
139
140#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
141#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
142
143#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
144
145#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr)>>PAGE_SHIFT)
146
147#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
148
149#define virt_to_phys __pa
150#define phys_to_virt __va
151
152#endif /* !(__ASSEMBLY__) */
153
154#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
155 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
156
5b17e1cd 157#include <asm-generic/getorder.h>
f5e706ad
SR
158
159#endif /* _SPARC64_PAGE_H */
This page took 0.365237 seconds and 5 git commands to generate.