[deliverable/linux.git] / arch / sparc / include / asm / pgtable_32.h

#ifndef _SPARC_PGTABLE_H
#define _SPARC_PGTABLE_H

/*  asm/pgtable.h:  Defines and functions used to work
 *                        with Sparc page tables.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/const.h>

#ifndef __ASSEMBLY__
#include <asm-generic/4level-fixup.h>

#include <linux/spinlock.h>
#include <linux/swap.h>
#include <asm/types.h>
#include <asm/pgtsrmmu.h>
#include <asm/vaddrs.h>
#include <asm/oplib.h>
#include <asm/cpu_type.h>


struct vm_area_struct;
struct page;

extern void load_mmu(void);
extern unsigned long calc_highpages(void);

#define pte_ERROR(e)   __builtin_trap()
#define pmd_ERROR(e)   __builtin_trap()
#define pgd_ERROR(e)   __builtin_trap()

#define PMD_SHIFT		22
#define PMD_SIZE        	(1UL << PMD_SHIFT)
#define PMD_MASK        	(~(PMD_SIZE-1))
#define PMD_ALIGN(__addr) 	(((__addr) + ~PMD_MASK) & PMD_MASK)
#define PGDIR_SHIFT     	SRMMU_PGDIR_SHIFT
#define PGDIR_SIZE      	SRMMU_PGDIR_SIZE
#define PGDIR_MASK      	SRMMU_PGDIR_MASK
#define PTRS_PER_PTE    	1024
#define PTRS_PER_PMD    	SRMMU_PTRS_PER_PMD
#define PTRS_PER_PGD    	SRMMU_PTRS_PER_PGD
#define USER_PTRS_PER_PGD	PAGE_OFFSET / SRMMU_PGDIR_SIZE
#define FIRST_USER_ADDRESS	0
#define PTE_SIZE		(PTRS_PER_PTE*4)

#define PAGE_NONE	SRMMU_PAGE_NONE
#define PAGE_SHARED	SRMMU_PAGE_SHARED
#define PAGE_COPY	SRMMU_PAGE_COPY
#define PAGE_READONLY	SRMMU_PAGE_RDONLY
#define PAGE_KERNEL	SRMMU_PAGE_KERNEL

/* Top-level page directory - dummy used by init-mm.
 * srmmu.c will assign the real one (which is dynamically sized) */
#define swapper_pg_dir NULL

extern void paging_init(void);

extern unsigned long ptr_in_current_pgd;

/*         xwr */
#define __P000  PAGE_NONE
#define __P001  PAGE_READONLY
#define __P010  PAGE_COPY
#define __P011  PAGE_COPY
#define __P100  PAGE_READONLY
#define __P101  PAGE_READONLY
#define __P110  PAGE_COPY
#define __P111  PAGE_COPY

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED
#define __S100	PAGE_READONLY
#define __S101	PAGE_READONLY
#define __S110	PAGE_SHARED
#define __S111	PAGE_SHARED

/* First physical page can be anywhere, the following is needed so that
 * va-->pa and vice versa conversions work properly without performance
 * hit for all __pa()/__va() operations.
 */
extern unsigned long phys_base;
extern unsigned long pfn_base;

/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern unsigned long empty_zero_page;

#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))

/*
 * In general all page table modifications should use the V8 atomic
 * swap instruction.  This insures the mmu and the cpu are in sync
 * with respect to ref/mod bits in the page tables.
 */
static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
{
	__asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
	return value;
}

/* Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */

static inline void set_pte(pte_t *ptep, pte_t pteval)
{
	srmmu_swap((unsigned long *)ptep, pte_val(pteval));
}

#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)

static inline int srmmu_device_memory(unsigned long x)
{
	return ((x & 0xF0000000) != 0);
}

static inline struct page *pmd_page(pmd_t pmd)
{
	if (srmmu_device_memory(pmd_val(pmd)))
		BUG();
	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
}

static inline unsigned long pgd_page_vaddr(pgd_t pgd)
{
	if (srmmu_device_memory(pgd_val(pgd))) {
		return ~0;
	} else {
		unsigned long v = pgd_val(pgd) & SRMMU_PTD_PMASK;
		return (unsigned long)__nocache_va(v << 4);
	}
}

static inline int pte_present(pte_t pte)
{
	return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
}

static inline int pte_none(pte_t pte)
{
	return !pte_val(pte);
}

static inline void __pte_clear(pte_t *ptep)
{
	set_pte(ptep, __pte(0));
}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	__pte_clear(ptep);
}

static inline int pmd_bad(pmd_t pmd)
{
	return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
}

static inline int pmd_present(pmd_t pmd)
{
	return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
}

static inline int pmd_none(pmd_t pmd)
{
	return !pmd_val(pmd);
}

static inline void pmd_clear(pmd_t *pmdp)
{
	int i;
	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
		set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
}

static inline int pgd_none(pgd_t pgd)          
{
	return !(pgd_val(pgd) & 0xFFFFFFF);
}

static inline int pgd_bad(pgd_t pgd)
{
	return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
}

static inline int pgd_present(pgd_t pgd)
{
	return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
}

static inline void pgd_clear(pgd_t *pgdp)
{
	set_pte((pte_t *)pgdp, __pte(0));
}

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
static inline int pte_write(pte_t pte)
{
	return pte_val(pte) & SRMMU_WRITE;
}

static inline int pte_dirty(pte_t pte)
{
	return pte_val(pte) & SRMMU_DIRTY;
}

static inline int pte_young(pte_t pte)
{
	return pte_val(pte) & SRMMU_REF;
}

/*
 * The following only work if pte_present() is not true.
 */
static inline int pte_file(pte_t pte)
{
	return pte_val(pte) & SRMMU_FILE;
}

static inline int pte_special(pte_t pte)
{
	return 0;
}

static inline pte_t pte_wrprotect(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_WRITE);
}

static inline pte_t pte_mkclean(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_DIRTY);
}

static inline pte_t pte_mkold(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_REF);
}

static inline pte_t pte_mkwrite(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_WRITE);
}

static inline pte_t pte_mkdirty(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_DIRTY);
}

static inline pte_t pte_mkyoung(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_REF);
}

#define pte_mkspecial(pte)    (pte)

#define pfn_pte(pfn, prot)		mk_pte(pfn_to_page(pfn), prot)

static inline unsigned long pte_pfn(pte_t pte)
{
	if (srmmu_device_memory(pte_val(pte))) {
		/* Just return something that will cause
		 * pfn_valid() to return false.  This makes
		 * copy_one_pte() to just directly copy to
		 * PTE over.
		 */
		return ~0UL;
	}
	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
}

#define pte_page(pte)	pfn_to_page(pte_pfn(pte))

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
{
	return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot));
}

static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
{
	return __pte(((page) >> 4) | pgprot_val(pgprot));
}

static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
{
	return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot));
}

#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t prot)
{
	prot &= ~__pgprot(SRMMU_CACHE);
	return prot;
}

static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & SRMMU_CHG_MASK) |
		pgprot_val(newprot));
}

#define pgd_index(address) ((address) >> PGDIR_SHIFT)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* Find an entry in the second-level page table.. */
static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
{
	return (pmd_t *) pgd_page_vaddr(*dir) +
		((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
}

/* Find an entry in the third-level page table.. */
pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address);

/*
 * This shortcut works on sun4m (and sun4d) because the nocache area is static.
 */
#define pte_offset_map(d, a)		pte_offset_kernel(d,a)
#define pte_unmap(pte)		do{}while(0)

struct seq_file;
void mmu_info(struct seq_file *m);

/* Fault handler stuff... */
#define FAULT_CODE_PROT     0x1
#define FAULT_CODE_WRITE    0x2
#define FAULT_CODE_USER     0x4

#define update_mmu_cache(vma, address, ptep) do { } while (0)

void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
                      unsigned long xva, unsigned int len);
void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len);

/* Encode and de-code a swap entry */
static inline unsigned long __swp_type(swp_entry_t entry)
{
	return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
}

static inline unsigned long __swp_offset(swp_entry_t entry)
{
	return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
}

static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
{
	return (swp_entry_t) {
		(type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
		| (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
}

#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

/* file-offset-in-pte helpers */
static inline unsigned long pte_to_pgoff(pte_t pte)
{
	return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
}

static inline pte_t pgoff_to_pte(unsigned long pgoff)
{
	return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
}

/*
 * This is made a constant because mm/fremap.c required a constant.
 */
#define PTE_FILE_MAX_BITS 24

static inline unsigned long
__get_phys (unsigned long addr)
{
	switch (sparc_cpu_model){
	case sun4m:
	case sun4d:
		return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
	default:
		return 0;
	}
}

static inline int
__get_iospace (unsigned long addr)
{
	switch (sparc_cpu_model){
	case sun4m:
	case sun4d:
		return (srmmu_get_pte (addr) >> 28);
	default:
		return -1;
	}
}

extern unsigned long *sparc_valid_addr_bitmap;

/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) \
	(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))

/*
 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
 * its high 4 bits.  These macros/functions put it there or get it from there.
 */
#define MK_IOSPACE_PFN(space, pfn)	(pfn | (space << (BITS_PER_LONG - 4)))
#define GET_IOSPACE(pfn)		(pfn >> (BITS_PER_LONG - 4))
#define GET_PFN(pfn)			(pfn & 0x0fffffffUL)

extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
			   unsigned long, pgprot_t);

static inline int io_remap_pfn_range(struct vm_area_struct *vma,
				     unsigned long from, unsigned long pfn,
				     unsigned long size, pgprot_t prot)
{
	unsigned long long offset, space, phys_base;

	offset = ((unsigned long long) GET_PFN(pfn)) << PAGE_SHIFT;
	space = GET_IOSPACE(pfn);
	phys_base = offset | (space << 32ULL);

	return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
}
#define io_remap_pfn_range io_remap_pfn_range 

#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
({									  \
	int __changed = !pte_same(*(__ptep), __entry);			  \
	if (__changed) {						  \
		set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
		flush_tlb_page(__vma, __address);			  \
	}								  \
	__changed;							  \
})

#include <asm-generic/pgtable.h>

#endif /* !(__ASSEMBLY__) */

#define VMALLOC_START           _AC(0xfe600000,UL)
#define VMALLOC_END             _AC(0xffc00000,UL)

/* We provide our own get_unmapped_area to cope with VA holes for userland */
#define HAVE_ARCH_UNMAPPED_AREA

/*
 * No page table caches to initialise
 */
#define pgtable_cache_init()	do { } while (0)

#endif /* !(_SPARC_PGTABLE_H) */
Commit	Line	Data
f5e706ad SR	1	#ifndef _SPARC_PGTABLE_H
	2	#define _SPARC_PGTABLE_H
	3
a439fe51	4	/* asm/pgtable.h: Defines and functions used to work
f5e706ad SR	5	* with Sparc page tables.
	6	*
	7	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	8	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	9	*/
	10
eb485d64 SR	11	#include <linux/const.h>
eb485d64 SR	12
f5e706ad SR	13	#ifndef __ASSEMBLY__
	14	#include <asm-generic/4level-fixup.h>
	15
	16	#include <linux/spinlock.h>
	17	#include <linux/swap.h>
	18	#include <asm/types.h>
f5e706ad	19	#include <asm/pgtsrmmu.h>
9701b264	20	#include <asm/vaddrs.h>
f5e706ad	21	#include <asm/oplib.h>
d550bbd4	22	#include <asm/cpu_type.h>
f5e706ad SR	23
	24
	25	struct vm_area_struct;
	26	struct page;
	27
	28	extern void load_mmu(void);
	29	extern unsigned long calc_highpages(void);
	30
f5e706ad SR	31	#define pte_ERROR(e) __builtin_trap()
	32	#define pmd_ERROR(e) __builtin_trap()
	33	#define pgd_ERROR(e) __builtin_trap()
	34
1ee0e144	35	#define PMD_SHIFT 22
f5e706ad SR	36	#define PMD_SIZE (1UL << PMD_SHIFT)
	37	#define PMD_MASK (~(PMD_SIZE-1))
	38	#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
3d386c0e DM	39	#define PGDIR_SHIFT SRMMU_PGDIR_SHIFT
	40	#define PGDIR_SIZE SRMMU_PGDIR_SIZE
	41	#define PGDIR_MASK SRMMU_PGDIR_MASK
f5e706ad	42	#define PTRS_PER_PTE 1024
3d386c0e DM	43	#define PTRS_PER_PMD SRMMU_PTRS_PER_PMD
	44	#define PTRS_PER_PGD SRMMU_PTRS_PER_PGD
	45	#define USER_PTRS_PER_PGD PAGE_OFFSET / SRMMU_PGDIR_SIZE
f5e706ad SR	46	#define FIRST_USER_ADDRESS 0
	47	#define PTE_SIZE (PTRS_PER_PTE*4)
	48
6439d1c6 DM	49	#define PAGE_NONE SRMMU_PAGE_NONE
	50	#define PAGE_SHARED SRMMU_PAGE_SHARED
	51	#define PAGE_COPY SRMMU_PAGE_COPY
	52	#define PAGE_READONLY SRMMU_PAGE_RDONLY
	53	#define PAGE_KERNEL SRMMU_PAGE_KERNEL
f5e706ad	54
881e02d2 SR	55	/* Top-level page directory - dummy used by init-mm.
	56	* srmmu.c will assign the real one (which is dynamically sized) */
	57	#define swapper_pg_dir NULL
f5e706ad SR	58
	59	extern void paging_init(void);
	60
f5e706ad SR	61	extern unsigned long ptr_in_current_pgd;
f5e706ad SR	62
6439d1c6 DM	63	/* xwr */
	64	#define __P000 PAGE_NONE
	65	#define __P001 PAGE_READONLY
	66	#define __P010 PAGE_COPY
	67	#define __P011 PAGE_COPY
	68	#define __P100 PAGE_READONLY
	69	#define __P101 PAGE_READONLY
	70	#define __P110 PAGE_COPY
	71	#define __P111 PAGE_COPY
	72
	73	#define __S000 PAGE_NONE
	74	#define __S001 PAGE_READONLY
	75	#define __S010 PAGE_SHARED
	76	#define __S011 PAGE_SHARED
	77	#define __S100 PAGE_READONLY
	78	#define __S101 PAGE_READONLY
	79	#define __S110 PAGE_SHARED
	80	#define __S111 PAGE_SHARED
f5e706ad	81
f5e706ad SR	82	/* First physical page can be anywhere, the following is needed so that
	83	* va-->pa and vice versa conversions work properly without performance
	84	* hit for all __pa()/__va() operations.
	85	*/
	86	extern unsigned long phys_base;
	87	extern unsigned long pfn_base;
	88
	89	/*
f5e706ad SR	90	* ZERO_PAGE is a global shared page that is always zero: used
	91	* for zero-mapped memory areas etc..
	92	*/
f5e706ad SR	93	extern unsigned long empty_zero_page;
f5e706ad SR	94
f5e706ad SR	95	#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
f5e706ad SR	96
a46d6056 DM	97	/*
	98	* In general all page table modifications should use the V8 atomic
	99	* swap instruction. This insures the mmu and the cpu are in sync
	100	* with respect to ref/mod bits in the page tables.
	101	*/
	102	static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
	103	{
	104	__asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
	105	return value;
	106	}
	107
62875cff DM	108	/* Certain architectures need to do special things when pte's
	109	* within a page table are directly modified. Thus, the following
	110	* hook is made available.
	111	*/
	112
	113	static inline void set_pte(pte_t *ptep, pte_t pteval)
a46d6056 DM	114	{
	115	srmmu_swap((unsigned long *)ptep, pte_val(pteval));
	116	}
	117
62875cff DM	118	#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
62875cff DM	119
3d827367 DM	120	static inline int srmmu_device_memory(unsigned long x)
	121	{
	122	return ((x & 0xF0000000) != 0);
	123	}
	124
	125	static inline struct page *pmd_page(pmd_t pmd)
	126	{
	127	if (srmmu_device_memory(pmd_val(pmd)))
	128	BUG();
	129	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
	130	}
	131
9701b264 SR	132	static inline unsigned long pgd_page_vaddr(pgd_t pgd)
	133	{
	134	if (srmmu_device_memory(pgd_val(pgd))) {
	135	return ~0;
	136	} else {
	137	unsigned long v = pgd_val(pgd) & SRMMU_PTD_PMASK;
	138	return (unsigned long)__nocache_va(v << 4);
	139	}
	140	}
f5e706ad	141
62875cff DM	142	static inline int pte_present(pte_t pte)
	143	{
	144	return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
	145	}
f5e706ad SR	146
	147	static inline int pte_none(pte_t pte)
	148	{
c87fe1c0	149	return !pte_val(pte);
f5e706ad SR	150	}
f5e706ad SR	151
a46d6056 DM	152	static inline void __pte_clear(pte_t *ptep)
a46d6056 DM	153	{
62875cff	154	set_pte(ptep, __pte(0));
a46d6056 DM	155	}
	156
	157	static inline void pte_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	158	{
	159	__pte_clear(ptep);
	160	}
f5e706ad	161
f167edae DM	162	static inline int pmd_bad(pmd_t pmd)
	163	{
	164	return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
	165	}
	166
	167	static inline int pmd_present(pmd_t pmd)
	168	{
	169	return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
	170	}
f5e706ad SR	171
	172	static inline int pmd_none(pmd_t pmd)
	173	{
c87fe1c0	174	return !pmd_val(pmd);
f5e706ad SR	175	}
f5e706ad SR	176
a46d6056 DM	177	static inline void pmd_clear(pmd_t *pmdp)
	178	{
	179	int i;
	180	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
62875cff	181	set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
a46d6056	182	}
f5e706ad	183
7d9fa4aa DM	184	static inline int pgd_none(pgd_t pgd)
	185	{
	186	return !(pgd_val(pgd) & 0xFFFFFFF);
	187	}
f5e706ad	188
7d9fa4aa DM	189	static inline int pgd_bad(pgd_t pgd)
	190	{
	191	return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
	192	}
	193
	194	static inline int pgd_present(pgd_t pgd)
	195	{
	196	return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
	197	}
a46d6056 DM	198
	199	static inline void pgd_clear(pgd_t *pgdp)
	200	{
62875cff	201	set_pte((pte_t *)pgdp, __pte(0));
a46d6056	202	}
f5e706ad SR	203
	204	/*
	205	* The following only work if pte_present() is true.
	206	* Undefined behaviour if not..
	207	*/
f5e706ad SR	208	static inline int pte_write(pte_t pte)
f5e706ad SR	209	{
f755f77a	210	return pte_val(pte) & SRMMU_WRITE;
f5e706ad SR	211	}
f5e706ad SR	212
f5e706ad SR	213	static inline int pte_dirty(pte_t pte)
f5e706ad SR	214	{
f755f77a	215	return pte_val(pte) & SRMMU_DIRTY;
f5e706ad SR	216	}
f5e706ad SR	217
f5e706ad SR	218	static inline int pte_young(pte_t pte)
f5e706ad SR	219	{
f755f77a	220	return pte_val(pte) & SRMMU_REF;
f5e706ad SR	221	}
	222
	223	/*
	224	* The following only work if pte_present() is not true.
	225	*/
f5e706ad SR	226	static inline int pte_file(pte_t pte)
f5e706ad SR	227	{
301d5bbb	228	return pte_val(pte) & SRMMU_FILE;
f5e706ad SR	229	}
	230
	231	static inline int pte_special(pte_t pte)
	232	{
	233	return 0;
	234	}
	235
f5e706ad SR	236	static inline pte_t pte_wrprotect(pte_t pte)
f5e706ad SR	237	{
301d5bbb	238	return __pte(pte_val(pte) & ~SRMMU_WRITE);
f5e706ad SR	239	}
f5e706ad SR	240
f5e706ad SR	241	static inline pte_t pte_mkclean(pte_t pte)
f5e706ad SR	242	{
301d5bbb	243	return __pte(pte_val(pte) & ~SRMMU_DIRTY);
f5e706ad SR	244	}
f5e706ad SR	245
f5e706ad SR	246	static inline pte_t pte_mkold(pte_t pte)
f5e706ad SR	247	{
301d5bbb	248	return __pte(pte_val(pte) & ~SRMMU_REF);
f5e706ad SR	249	}
f5e706ad SR	250
301d5bbb DM	251	static inline pte_t pte_mkwrite(pte_t pte)
	252	{
	253	return __pte(pte_val(pte) \| SRMMU_WRITE);
	254	}
f5e706ad	255
301d5bbb DM	256	static inline pte_t pte_mkdirty(pte_t pte)
	257	{
	258	return __pte(pte_val(pte) \| SRMMU_DIRTY);
	259	}
	260
	261	static inline pte_t pte_mkyoung(pte_t pte)
	262	{
	263	return __pte(pte_val(pte) \| SRMMU_REF);
	264	}
f5e706ad SR	265
	266	#define pte_mkspecial(pte) (pte)
	267
	268	#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
	269
3d827367 DM	270	static inline unsigned long pte_pfn(pte_t pte)
	271	{
	272	if (srmmu_device_memory(pte_val(pte))) {
	273	/* Just return something that will cause
	274	* pfn_valid() to return false. This makes
	275	* copy_one_pte() to just directly copy to
	276	* PTE over.
	277	*/
	278	return ~0UL;
	279	}
	280	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
	281	}
	282
f5e706ad SR	283	#define pte_page(pte) pfn_to_page(pte_pfn(pte))
	284
	285	/*
	286	* Conversion functions: convert a page and protection to a page entry,
	287	* and a page entry and page directory to the page they refer to.
	288	*/
62875cff DM	289	static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
	290	{
	291	return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) \| pgprot_val(pgprot));
	292	}
f5e706ad	293
62875cff DM	294	static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
	295	{
	296	return __pte(((page) >> 4) \| pgprot_val(pgprot));
	297	}
f5e706ad	298
62875cff DM	299	static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
	300	{
	301	return __pte(((page) >> 4) \| (space << 28) \| pgprot_val(pgprot));
	302	}
f5e706ad	303
afaedde7 SR	304	#define pgprot_noncached pgprot_noncached
	305	static inline pgprot_t pgprot_noncached(pgprot_t prot)
	306	{
	307	prot &= ~__pgprot(SRMMU_CACHE);
	308	return prot;
	309	}
f5e706ad	310
f5e706ad SR	311	static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
	312	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
	313	{
9701b264	314	return __pte((pte_val(pte) & SRMMU_CHG_MASK) \|
f5e706ad SR	315	pgprot_val(newprot));
	316	}
	317
	318	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	319
	320	/* to find an entry in a page-table-directory */
	321	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	322
	323	/* to find an entry in a kernel page-table-directory */
	324	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	325
	326	/* Find an entry in the second-level page table.. */
9701b264 SR	327	static inline pmd_t pmd_offset(pgd_t dir, unsigned long address)
	328	{
	329	return (pmd_t ) pgd_page_vaddr(dir) +
	330	((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
	331	}
f5e706ad SR	332
f5e706ad SR	333	/* Find an entry in the third-level page table.. */
9701b264	334	pte_t pte_offset_kernel(pmd_t dir, unsigned long address);
f5e706ad SR	335
f5e706ad SR	336	/*
ee906c9e	337	* This shortcut works on sun4m (and sun4d) because the nocache area is static.
f5e706ad SR	338	*/
f5e706ad SR	339	#define pte_offset_map(d, a) pte_offset_kernel(d,a)
f5e706ad	340	#define pte_unmap(pte) do{}while(0)
f5e706ad	341
f5e706ad	342	struct seq_file;
9701b264	343	void mmu_info(struct seq_file *m);
f5e706ad SR	344
	345	/* Fault handler stuff... */
	346	#define FAULT_CODE_PROT 0x1
	347	#define FAULT_CODE_WRITE 0x2
	348	#define FAULT_CODE_USER 0x4
	349
f613914e	350	#define update_mmu_cache(vma, address, ptep) do { } while (0)
f5e706ad	351
9701b264 SR	352	void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
	353	unsigned long xva, unsigned int len);
	354	void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len);
f5e706ad	355
f5e706ad	356	/* Encode and de-code a swap entry */
9701b264 SR	357	static inline unsigned long __swp_type(swp_entry_t entry)
	358	{
	359	return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
	360	}
f5e706ad	361
9701b264 SR	362	static inline unsigned long __swp_offset(swp_entry_t entry)
	363	{
	364	return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
	365	}
	366
	367	static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
	368	{
	369	return (swp_entry_t) {
	370	(type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
	371	\| (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
	372	}
f5e706ad SR	373
	374	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	375	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	376
	377	/* file-offset-in-pte helpers */
afaedde7 SR	378	static inline unsigned long pte_to_pgoff(pte_t pte)
	379	{
	380	return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
	381	}
f5e706ad	382
afaedde7 SR	383	static inline pte_t pgoff_to_pte(unsigned long pgoff)
	384	{
	385	return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) \| SRMMU_FILE);
	386	}
f5e706ad SR	387
	388	/*
	389	* This is made a constant because mm/fremap.c required a constant.
f5e706ad SR	390	*/
	391	#define PTE_FILE_MAX_BITS 24
	392
f5e706ad SR	393	static inline unsigned long
	394	__get_phys (unsigned long addr)
	395	{
	396	switch (sparc_cpu_model){
f5e706ad SR	397	case sun4m:
	398	case sun4d:
	399	return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
	400	default:
	401	return 0;
	402	}
	403	}
	404
	405	static inline int
	406	__get_iospace (unsigned long addr)
	407	{
	408	switch (sparc_cpu_model){
f5e706ad SR	409	case sun4m:
	410	case sun4d:
	411	return (srmmu_get_pte (addr) >> 28);
	412	default:
	413	return -1;
	414	}
	415	}
	416
	417	extern unsigned long *sparc_valid_addr_bitmap;
	418
	419	/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
	420	#define kern_addr_valid(addr) \
	421	(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
	422
f5e706ad SR	423	/*
	424	* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
	425	* its high 4 bits. These macros/functions put it there or get it from there.
	426	*/
	427	#define MK_IOSPACE_PFN(space, pfn) (pfn \| (space << (BITS_PER_LONG - 4)))
	428	#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
	429	#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
	430
3e37fd31 DM	431	extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
	432	unsigned long, pgprot_t);
	433
	434	static inline int io_remap_pfn_range(struct vm_area_struct *vma,
	435	unsigned long from, unsigned long pfn,
	436	unsigned long size, pgprot_t prot)
	437	{
	438	unsigned long long offset, space, phys_base;
	439
	440	offset = ((unsigned long long) GET_PFN(pfn)) << PAGE_SHIFT;
	441	space = GET_IOSPACE(pfn);
	442	phys_base = offset \| (space << 32ULL);
	443
	444	return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
	445	}
40d158e6	446	#define io_remap_pfn_range io_remap_pfn_range
3e37fd31	447
f5e706ad SR	448	#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
	449	#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
	450	({ \
	451	int __changed = !pte_same(*(__ptep), __entry); \
	452	if (__changed) { \
	453	set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
	454	flush_tlb_page(__vma, __address); \
	455	} \
1ee0e144	456	__changed; \
f5e706ad SR	457	})
	458
	459	#include <asm-generic/pgtable.h>
	460
	461	#endif /* !(__ASSEMBLY__) */
	462
eb485d64	463	#define VMALLOC_START _AC(0xfe600000,UL)
eb485d64	464	#define VMALLOC_END _AC(0xffc00000,UL)
f5e706ad	465
f5e706ad SR	466	/* We provide our own get_unmapped_area to cope with VA holes for userland */
	467	#define HAVE_ARCH_UNMAPPED_AREA
	468
	469	/*
	470	* No page table caches to initialise
	471	*/
	472	#define pgtable_cache_init() do { } while (0)
	473
	474	#endif /* !(_SPARC_PGTABLE_H) */