[deliverable/linux.git] / arch / sparc / include / asm / pgtable_32.h

#ifndef _SPARC_PGTABLE_H
#define _SPARC_PGTABLE_H

/*  asm/pgtable.h:  Defines and functions used to work
 *                        with Sparc page tables.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/const.h>

#ifndef __ASSEMBLY__
#include <asm-generic/4level-fixup.h>

#include <linux/spinlock.h>
#include <linux/swap.h>
#include <asm/types.h>
#include <asm/pgtsrmmu.h>
#include <asm/oplib.h>
#include <asm/btfixup.h>
#include <asm/cpu_type.h>


struct vm_area_struct;
struct page;

extern void load_mmu(void);
extern unsigned long calc_highpages(void);

#define pte_ERROR(e)   __builtin_trap()
#define pmd_ERROR(e)   __builtin_trap()
#define pgd_ERROR(e)   __builtin_trap()

#define PMD_SHIFT		22
#define PMD_SIZE        	(1UL << PMD_SHIFT)
#define PMD_MASK        	(~(PMD_SIZE-1))
#define PMD_ALIGN(__addr) 	(((__addr) + ~PMD_MASK) & PMD_MASK)
#define PGDIR_SHIFT     	SRMMU_PGDIR_SHIFT
#define PGDIR_SIZE      	SRMMU_PGDIR_SIZE
#define PGDIR_MASK      	SRMMU_PGDIR_MASK
#define PTRS_PER_PTE    	1024
#define PTRS_PER_PMD    	SRMMU_PTRS_PER_PMD
#define PTRS_PER_PGD    	SRMMU_PTRS_PER_PGD
#define USER_PTRS_PER_PGD	PAGE_OFFSET / SRMMU_PGDIR_SIZE
#define FIRST_USER_ADDRESS	0
#define PTE_SIZE		(PTRS_PER_PTE*4)

#define PAGE_NONE	SRMMU_PAGE_NONE
#define PAGE_SHARED	SRMMU_PAGE_SHARED
#define PAGE_COPY	SRMMU_PAGE_COPY
#define PAGE_READONLY	SRMMU_PAGE_RDONLY
#define PAGE_KERNEL	SRMMU_PAGE_KERNEL

/* Top-level page directory */
extern pgd_t swapper_pg_dir[1024];

extern void paging_init(void);

extern unsigned long ptr_in_current_pgd;

/*         xwr */
#define __P000  PAGE_NONE
#define __P001  PAGE_READONLY
#define __P010  PAGE_COPY
#define __P011  PAGE_COPY
#define __P100  PAGE_READONLY
#define __P101  PAGE_READONLY
#define __P110  PAGE_COPY
#define __P111  PAGE_COPY

#define __S000	PAGE_NONE
#define __S001	PAGE_READONLY
#define __S010	PAGE_SHARED
#define __S011	PAGE_SHARED
#define __S100	PAGE_READONLY
#define __S101	PAGE_READONLY
#define __S110	PAGE_SHARED
#define __S111	PAGE_SHARED

extern int num_contexts;

/* First physical page can be anywhere, the following is needed so that
 * va-->pa and vice versa conversions work properly without performance
 * hit for all __pa()/__va() operations.
 */
extern unsigned long phys_base;
extern unsigned long pfn_base;

/*
 * BAD_PAGETABLE is used when we need a bogus page-table, while
 * BAD_PAGE is used for a bogus page.
 *
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern pte_t * __bad_pagetable(void);
extern pte_t __bad_page(void);
extern unsigned long empty_zero_page;

#define BAD_PAGETABLE __bad_pagetable()
#define BAD_PAGE __bad_page()
#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))

/*
 * In general all page table modifications should use the V8 atomic
 * swap instruction.  This insures the mmu and the cpu are in sync
 * with respect to ref/mod bits in the page tables.
 */
static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
{
	__asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
	return value;
}

/* Certain architectures need to do special things when pte's
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */

static inline void set_pte(pte_t *ptep, pte_t pteval)
{
	srmmu_swap((unsigned long *)ptep, pte_val(pteval));
}

#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)

static inline int srmmu_device_memory(unsigned long x)
{
	return ((x & 0xF0000000) != 0);
}

static inline struct page *pmd_page(pmd_t pmd)
{
	if (srmmu_device_memory(pmd_val(pmd)))
		BUG();
	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
}

BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)

#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)

static inline int pte_present(pte_t pte)
{
	return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
}

static inline int pte_none(pte_t pte)
{
	return !pte_val(pte);
}

static inline void __pte_clear(pte_t *ptep)
{
	set_pte(ptep, __pte(0));
}

static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	__pte_clear(ptep);
}

static inline int pmd_bad(pmd_t pmd)
{
	return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
}

static inline int pmd_present(pmd_t pmd)
{
	return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
}

static inline int pmd_none(pmd_t pmd)
{
	return !pmd_val(pmd);
}

static inline void pmd_clear(pmd_t *pmdp)
{
	int i;
	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
		set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
}

static inline int pgd_none(pgd_t pgd)          
{
	return !(pgd_val(pgd) & 0xFFFFFFF);
}

static inline int pgd_bad(pgd_t pgd)
{
	return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
}

static inline int pgd_present(pgd_t pgd)
{
	return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
}

static inline void pgd_clear(pgd_t *pgdp)
{
	set_pte((pte_t *)pgdp, __pte(0));
}

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
static inline int pte_write(pte_t pte)
{
	return pte_val(pte) & SRMMU_WRITE;
}

static inline int pte_dirty(pte_t pte)
{
	return pte_val(pte) & SRMMU_DIRTY;
}

static inline int pte_young(pte_t pte)
{
	return pte_val(pte) & SRMMU_REF;
}

/*
 * The following only work if pte_present() is not true.
 */
static inline int pte_file(pte_t pte)
{
	return pte_val(pte) & SRMMU_FILE;
}

static inline int pte_special(pte_t pte)
{
	return 0;
}

static inline pte_t pte_wrprotect(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_WRITE);
}

static inline pte_t pte_mkclean(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_DIRTY);
}

static inline pte_t pte_mkold(pte_t pte)
{
	return __pte(pte_val(pte) & ~SRMMU_REF);
}

static inline pte_t pte_mkwrite(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_WRITE);
}

static inline pte_t pte_mkdirty(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_DIRTY);
}

static inline pte_t pte_mkyoung(pte_t pte)
{
	return __pte(pte_val(pte) | SRMMU_REF);
}

#define pte_mkspecial(pte)    (pte)

#define pfn_pte(pfn, prot)		mk_pte(pfn_to_page(pfn), prot)

static inline unsigned long pte_pfn(pte_t pte)
{
	if (srmmu_device_memory(pte_val(pte))) {
		/* Just return something that will cause
		 * pfn_valid() to return false.  This makes
		 * copy_one_pte() to just directly copy to
		 * PTE over.
		 */
		return ~0UL;
	}
	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
}

#define pte_page(pte)	pfn_to_page(pte_pfn(pte))

/*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
{
	return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot));
}

static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
{
	return __pte(((page) >> 4) | pgprot_val(pgprot));
}

static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
{
	return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot));
}

#define pgprot_noncached pgprot_noncached
static inline pgprot_t pgprot_noncached(pgprot_t prot)
{
	prot &= ~__pgprot(SRMMU_CACHE);
	return prot;
}

BTFIXUPDEF_INT(pte_modify_mask)

static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
		pgprot_val(newprot));
}

#define pgd_index(address) ((address) >> PGDIR_SHIFT)

/* to find an entry in a page-table-directory */
#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* Find an entry in the second-level page table.. */
BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)

/* Find an entry in the third-level page table.. */
BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)

/*
 * This shortcut works on sun4m (and sun4d) because the nocache area is static.
 */
#define pte_offset_map(d, a)		pte_offset_kernel(d,a)
#define pte_unmap(pte)		do{}while(0)

struct seq_file;
BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)

#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)

/* Fault handler stuff... */
#define FAULT_CODE_PROT     0x1
#define FAULT_CODE_WRITE    0x2
#define FAULT_CODE_USER     0x4

BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t *)

#define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep)

BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
    unsigned long, unsigned int)
BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)

extern int invalid_segment;

/* Encode and de-code a swap entry */
BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)

#define __swp_type(__x)			BTFIXUP_CALL(__swp_type)(__x)
#define __swp_offset(__x)		BTFIXUP_CALL(__swp_offset)(__x)
#define __swp_entry(__type,__off)	BTFIXUP_CALL(__swp_entry)(__type,__off)

#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val })

/* file-offset-in-pte helpers */
static inline unsigned long pte_to_pgoff(pte_t pte)
{
	return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
}

static inline pte_t pgoff_to_pte(unsigned long pgoff)
{
	return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
}

/*
 * This is made a constant because mm/fremap.c required a constant.
 */
#define PTE_FILE_MAX_BITS 24

/*
 */
struct ctx_list {
	struct ctx_list *next;
	struct ctx_list *prev;
	unsigned int ctx_number;
	struct mm_struct *ctx_mm;
};

extern struct ctx_list *ctx_list_pool;  /* Dynamically allocated */
extern struct ctx_list ctx_free;        /* Head of free list */
extern struct ctx_list ctx_used;        /* Head of used contexts list */

#define NO_CONTEXT     -1

static inline void remove_from_ctx_list(struct ctx_list *entry)
{
	entry->next->prev = entry->prev;
	entry->prev->next = entry->next;
}

static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
{
	entry->next = head;
	(entry->prev = head->prev)->next = entry;
	head->prev = entry;
}
#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)

static inline unsigned long
__get_phys (unsigned long addr)
{
	switch (sparc_cpu_model){
	case sun4m:
	case sun4d:
		return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
	default:
		return 0;
	}
}

static inline int
__get_iospace (unsigned long addr)
{
	switch (sparc_cpu_model){
	case sun4m:
	case sun4d:
		return (srmmu_get_pte (addr) >> 28);
	default:
		return -1;
	}
}

extern unsigned long *sparc_valid_addr_bitmap;

/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define kern_addr_valid(addr) \
	(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))

/*
 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
 * its high 4 bits.  These macros/functions put it there or get it from there.
 */
#define MK_IOSPACE_PFN(space, pfn)	(pfn | (space << (BITS_PER_LONG - 4)))
#define GET_IOSPACE(pfn)		(pfn >> (BITS_PER_LONG - 4))
#define GET_PFN(pfn)			(pfn & 0x0fffffffUL)

extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
			   unsigned long, pgprot_t);

static inline int io_remap_pfn_range(struct vm_area_struct *vma,
				     unsigned long from, unsigned long pfn,
				     unsigned long size, pgprot_t prot)
{
	unsigned long long offset, space, phys_base;

	offset = ((unsigned long long) GET_PFN(pfn)) << PAGE_SHIFT;
	space = GET_IOSPACE(pfn);
	phys_base = offset | (space << 32ULL);

	return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
}

#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
({									  \
	int __changed = !pte_same(*(__ptep), __entry);			  \
	if (__changed) {						  \
		set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
		flush_tlb_page(__vma, __address);			  \
	}								  \
	__changed;							  \
})

#include <asm-generic/pgtable.h>

#endif /* !(__ASSEMBLY__) */

#define VMALLOC_START           _AC(0xfe600000,UL)
#define VMALLOC_END             _AC(0xffc00000,UL)

/* We provide our own get_unmapped_area to cope with VA holes for userland */
#define HAVE_ARCH_UNMAPPED_AREA

/*
 * No page table caches to initialise
 */
#define pgtable_cache_init()	do { } while (0)

#endif /* !(_SPARC_PGTABLE_H) */
Commit	Line	Data
f5e706ad SR	1	#ifndef _SPARC_PGTABLE_H
	2	#define _SPARC_PGTABLE_H
	3
a439fe51	4	/* asm/pgtable.h: Defines and functions used to work
f5e706ad SR	5	* with Sparc page tables.
	6	*
	7	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	8	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	9	*/
	10
eb485d64 SR	11	#include <linux/const.h>
eb485d64 SR	12
f5e706ad SR	13	#ifndef __ASSEMBLY__
	14	#include <asm-generic/4level-fixup.h>
	15
	16	#include <linux/spinlock.h>
	17	#include <linux/swap.h>
	18	#include <asm/types.h>
f5e706ad	19	#include <asm/pgtsrmmu.h>
f5e706ad SR	20	#include <asm/oplib.h>
f5e706ad SR	21	#include <asm/btfixup.h>
d550bbd4	22	#include <asm/cpu_type.h>
f5e706ad SR	23
	24
	25	struct vm_area_struct;
	26	struct page;
	27
	28	extern void load_mmu(void);
	29	extern unsigned long calc_highpages(void);
	30
f5e706ad SR	31	#define pte_ERROR(e) __builtin_trap()
	32	#define pmd_ERROR(e) __builtin_trap()
	33	#define pgd_ERROR(e) __builtin_trap()
	34
1ee0e144	35	#define PMD_SHIFT 22
f5e706ad SR	36	#define PMD_SIZE (1UL << PMD_SHIFT)
	37	#define PMD_MASK (~(PMD_SIZE-1))
	38	#define PMD_ALIGN(__addr) (((__addr) + ~PMD_MASK) & PMD_MASK)
3d386c0e DM	39	#define PGDIR_SHIFT SRMMU_PGDIR_SHIFT
	40	#define PGDIR_SIZE SRMMU_PGDIR_SIZE
	41	#define PGDIR_MASK SRMMU_PGDIR_MASK
f5e706ad	42	#define PTRS_PER_PTE 1024
3d386c0e DM	43	#define PTRS_PER_PMD SRMMU_PTRS_PER_PMD
	44	#define PTRS_PER_PGD SRMMU_PTRS_PER_PGD
	45	#define USER_PTRS_PER_PGD PAGE_OFFSET / SRMMU_PGDIR_SIZE
f5e706ad SR	46	#define FIRST_USER_ADDRESS 0
	47	#define PTE_SIZE (PTRS_PER_PTE*4)
	48
6439d1c6 DM	49	#define PAGE_NONE SRMMU_PAGE_NONE
	50	#define PAGE_SHARED SRMMU_PAGE_SHARED
	51	#define PAGE_COPY SRMMU_PAGE_COPY
	52	#define PAGE_READONLY SRMMU_PAGE_RDONLY
	53	#define PAGE_KERNEL SRMMU_PAGE_KERNEL
f5e706ad SR	54
	55	/* Top-level page directory */
	56	extern pgd_t swapper_pg_dir[1024];
	57
	58	extern void paging_init(void);
	59
f5e706ad SR	60	extern unsigned long ptr_in_current_pgd;
f5e706ad SR	61
6439d1c6 DM	62	/* xwr */
	63	#define __P000 PAGE_NONE
	64	#define __P001 PAGE_READONLY
	65	#define __P010 PAGE_COPY
	66	#define __P011 PAGE_COPY
	67	#define __P100 PAGE_READONLY
	68	#define __P101 PAGE_READONLY
	69	#define __P110 PAGE_COPY
	70	#define __P111 PAGE_COPY
	71
	72	#define __S000 PAGE_NONE
	73	#define __S001 PAGE_READONLY
	74	#define __S010 PAGE_SHARED
	75	#define __S011 PAGE_SHARED
	76	#define __S100 PAGE_READONLY
	77	#define __S101 PAGE_READONLY
	78	#define __S110 PAGE_SHARED
	79	#define __S111 PAGE_SHARED
f5e706ad SR	80
	81	extern int num_contexts;
	82
	83	/* First physical page can be anywhere, the following is needed so that
	84	* va-->pa and vice versa conversions work properly without performance
	85	* hit for all __pa()/__va() operations.
	86	*/
	87	extern unsigned long phys_base;
	88	extern unsigned long pfn_base;
	89
	90	/*
	91	* BAD_PAGETABLE is used when we need a bogus page-table, while
	92	* BAD_PAGE is used for a bogus page.
	93	*
	94	* ZERO_PAGE is a global shared page that is always zero: used
	95	* for zero-mapped memory areas etc..
	96	*/
	97	extern pte_t * __bad_pagetable(void);
	98	extern pte_t __bad_page(void);
	99	extern unsigned long empty_zero_page;
	100
	101	#define BAD_PAGETABLE __bad_pagetable()
	102	#define BAD_PAGE __bad_page()
	103	#define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
	104
a46d6056 DM	105	/*
	106	* In general all page table modifications should use the V8 atomic
	107	* swap instruction. This insures the mmu and the cpu are in sync
	108	* with respect to ref/mod bits in the page tables.
	109	*/
	110	static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
	111	{
	112	__asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
	113	return value;
	114	}
	115
62875cff DM	116	/* Certain architectures need to do special things when pte's
	117	* within a page table are directly modified. Thus, the following
	118	* hook is made available.
	119	*/
	120
	121	static inline void set_pte(pte_t *ptep, pte_t pteval)
a46d6056 DM	122	{
	123	srmmu_swap((unsigned long *)ptep, pte_val(pteval));
	124	}
	125
62875cff DM	126	#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
62875cff DM	127
3d827367 DM	128	static inline int srmmu_device_memory(unsigned long x)
	129	{
	130	return ((x & 0xF0000000) != 0);
	131	}
	132
	133	static inline struct page *pmd_page(pmd_t pmd)
	134	{
	135	if (srmmu_device_memory(pmd_val(pmd)))
	136	BUG();
	137	return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
	138	}
	139
f5e706ad SR	140	BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
f5e706ad SR	141
f5e706ad SR	142	#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
f5e706ad SR	143
62875cff DM	144	static inline int pte_present(pte_t pte)
	145	{
	146	return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
	147	}
f5e706ad SR	148
	149	static inline int pte_none(pte_t pte)
	150	{
c87fe1c0	151	return !pte_val(pte);
f5e706ad SR	152	}
f5e706ad SR	153
a46d6056 DM	154	static inline void __pte_clear(pte_t *ptep)
a46d6056 DM	155	{
62875cff	156	set_pte(ptep, __pte(0));
a46d6056 DM	157	}
	158
	159	static inline void pte_clear(struct mm_struct mm, unsigned long addr, pte_t ptep)
	160	{
	161	__pte_clear(ptep);
	162	}
f5e706ad	163
f167edae DM	164	static inline int pmd_bad(pmd_t pmd)
	165	{
	166	return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
	167	}
	168
	169	static inline int pmd_present(pmd_t pmd)
	170	{
	171	return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
	172	}
f5e706ad SR	173
	174	static inline int pmd_none(pmd_t pmd)
	175	{
c87fe1c0	176	return !pmd_val(pmd);
f5e706ad SR	177	}
f5e706ad SR	178
a46d6056 DM	179	static inline void pmd_clear(pmd_t *pmdp)
	180	{
	181	int i;
	182	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
62875cff	183	set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
a46d6056	184	}
f5e706ad	185
7d9fa4aa DM	186	static inline int pgd_none(pgd_t pgd)
	187	{
	188	return !(pgd_val(pgd) & 0xFFFFFFF);
	189	}
f5e706ad	190
7d9fa4aa DM	191	static inline int pgd_bad(pgd_t pgd)
	192	{
	193	return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
	194	}
	195
	196	static inline int pgd_present(pgd_t pgd)
	197	{
	198	return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
	199	}
a46d6056 DM	200
	201	static inline void pgd_clear(pgd_t *pgdp)
	202	{
62875cff	203	set_pte((pte_t *)pgdp, __pte(0));
a46d6056	204	}
f5e706ad SR	205
	206	/*
	207	* The following only work if pte_present() is true.
	208	* Undefined behaviour if not..
	209	*/
f5e706ad SR	210	static inline int pte_write(pte_t pte)
f5e706ad SR	211	{
f755f77a	212	return pte_val(pte) & SRMMU_WRITE;
f5e706ad SR	213	}
f5e706ad SR	214
f5e706ad SR	215	static inline int pte_dirty(pte_t pte)
f5e706ad SR	216	{
f755f77a	217	return pte_val(pte) & SRMMU_DIRTY;
f5e706ad SR	218	}
f5e706ad SR	219
f5e706ad SR	220	static inline int pte_young(pte_t pte)
f5e706ad SR	221	{
f755f77a	222	return pte_val(pte) & SRMMU_REF;
f5e706ad SR	223	}
	224
	225	/*
	226	* The following only work if pte_present() is not true.
	227	*/
f5e706ad SR	228	static inline int pte_file(pte_t pte)
f5e706ad SR	229	{
301d5bbb	230	return pte_val(pte) & SRMMU_FILE;
f5e706ad SR	231	}
	232
	233	static inline int pte_special(pte_t pte)
	234	{
	235	return 0;
	236	}
	237
f5e706ad SR	238	static inline pte_t pte_wrprotect(pte_t pte)
f5e706ad SR	239	{
301d5bbb	240	return __pte(pte_val(pte) & ~SRMMU_WRITE);
f5e706ad SR	241	}
f5e706ad SR	242
f5e706ad SR	243	static inline pte_t pte_mkclean(pte_t pte)
f5e706ad SR	244	{
301d5bbb	245	return __pte(pte_val(pte) & ~SRMMU_DIRTY);
f5e706ad SR	246	}
f5e706ad SR	247
f5e706ad SR	248	static inline pte_t pte_mkold(pte_t pte)
f5e706ad SR	249	{
301d5bbb	250	return __pte(pte_val(pte) & ~SRMMU_REF);
f5e706ad SR	251	}
f5e706ad SR	252
301d5bbb DM	253	static inline pte_t pte_mkwrite(pte_t pte)
	254	{
	255	return __pte(pte_val(pte) \| SRMMU_WRITE);
	256	}
f5e706ad	257
301d5bbb DM	258	static inline pte_t pte_mkdirty(pte_t pte)
	259	{
	260	return __pte(pte_val(pte) \| SRMMU_DIRTY);
	261	}
	262
	263	static inline pte_t pte_mkyoung(pte_t pte)
	264	{
	265	return __pte(pte_val(pte) \| SRMMU_REF);
	266	}
f5e706ad SR	267
	268	#define pte_mkspecial(pte) (pte)
	269
	270	#define pfn_pte(pfn, prot) mk_pte(pfn_to_page(pfn), prot)
	271
3d827367 DM	272	static inline unsigned long pte_pfn(pte_t pte)
	273	{
	274	if (srmmu_device_memory(pte_val(pte))) {
	275	/* Just return something that will cause
	276	* pfn_valid() to return false. This makes
	277	* copy_one_pte() to just directly copy to
	278	* PTE over.
	279	*/
	280	return ~0UL;
	281	}
	282	return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
	283	}
	284
f5e706ad SR	285	#define pte_page(pte) pfn_to_page(pte_pfn(pte))
	286
	287	/*
	288	* Conversion functions: convert a page and protection to a page entry,
	289	* and a page entry and page directory to the page they refer to.
	290	*/
62875cff DM	291	static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
	292	{
	293	return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) \| pgprot_val(pgprot));
	294	}
f5e706ad	295
62875cff DM	296	static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
	297	{
	298	return __pte(((page) >> 4) \| pgprot_val(pgprot));
	299	}
f5e706ad	300
62875cff DM	301	static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
	302	{
	303	return __pte(((page) >> 4) \| (space << 28) \| pgprot_val(pgprot));
	304	}
f5e706ad	305
afaedde7 SR	306	#define pgprot_noncached pgprot_noncached
	307	static inline pgprot_t pgprot_noncached(pgprot_t prot)
	308	{
	309	prot &= ~__pgprot(SRMMU_CACHE);
	310	return prot;
	311	}
f5e706ad SR	312
	313	BTFIXUPDEF_INT(pte_modify_mask)
	314
	315	static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
	316	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
	317	{
	318	return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) \|
	319	pgprot_val(newprot));
	320	}
	321
	322	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	323
	324	/* to find an entry in a page-table-directory */
	325	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	326
	327	/* to find an entry in a kernel page-table-directory */
	328	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	329
	330	/* Find an entry in the second-level page table.. */
	331	BTFIXUPDEF_CALL(pmd_t , pmd_offset, pgd_t , unsigned long)
	332	#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
	333
	334	/* Find an entry in the third-level page table.. */
	335	BTFIXUPDEF_CALL(pte_t , pte_offset_kernel, pmd_t , unsigned long)
	336	#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
	337
	338	/*
ee906c9e	339	* This shortcut works on sun4m (and sun4d) because the nocache area is static.
f5e706ad SR	340	*/
f5e706ad SR	341	#define pte_offset_map(d, a) pte_offset_kernel(d,a)
f5e706ad	342	#define pte_unmap(pte) do{}while(0)
f5e706ad	343
f5e706ad SR	344	struct seq_file;
	345	BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
	346
	347	#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
	348
	349	/* Fault handler stuff... */
	350	#define FAULT_CODE_PROT 0x1
	351	#define FAULT_CODE_WRITE 0x2
	352	#define FAULT_CODE_USER 0x4
	353
4b3073e1	354	BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct , unsigned long, pte_t )
f5e706ad	355
4b3073e1	356	#define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep)
f5e706ad SR	357
	358	BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
	359	unsigned long, unsigned int)
	360	BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
	361	#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
	362	#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
	363
	364	extern int invalid_segment;
	365
	366	/* Encode and de-code a swap entry */
	367	BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
	368	BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
	369	BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
	370
	371	#define __swp_type(__x) BTFIXUP_CALL(__swp_type)(__x)
	372	#define __swp_offset(__x) BTFIXUP_CALL(__swp_offset)(__x)
	373	#define __swp_entry(__type,__off) BTFIXUP_CALL(__swp_entry)(__type,__off)
	374
	375	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	376	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	377
	378	/* file-offset-in-pte helpers */
afaedde7 SR	379	static inline unsigned long pte_to_pgoff(pte_t pte)
	380	{
	381	return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
	382	}
f5e706ad	383
afaedde7 SR	384	static inline pte_t pgoff_to_pte(unsigned long pgoff)
	385	{
	386	return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) \| SRMMU_FILE);
	387	}
f5e706ad SR	388
	389	/*
	390	* This is made a constant because mm/fremap.c required a constant.
f5e706ad SR	391	*/
	392	#define PTE_FILE_MAX_BITS 24
	393
	394	/*
	395	*/
	396	struct ctx_list {
	397	struct ctx_list *next;
	398	struct ctx_list *prev;
	399	unsigned int ctx_number;
	400	struct mm_struct *ctx_mm;
	401	};
	402
	403	extern struct ctx_list ctx_list_pool; / Dynamically allocated */
	404	extern struct ctx_list ctx_free; /* Head of free list */
	405	extern struct ctx_list ctx_used; /* Head of used contexts list */
	406
	407	#define NO_CONTEXT -1
	408
	409	static inline void remove_from_ctx_list(struct ctx_list *entry)
	410	{
	411	entry->next->prev = entry->prev;
	412	entry->prev->next = entry->next;
	413	}
	414
	415	static inline void add_to_ctx_list(struct ctx_list head, struct ctx_list entry)
	416	{
	417	entry->next = head;
	418	(entry->prev = head->prev)->next = entry;
	419	head->prev = entry;
	420	}
	421	#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
	422	#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
	423
	424	static inline unsigned long
	425	__get_phys (unsigned long addr)
	426	{
	427	switch (sparc_cpu_model){
f5e706ad SR	428	case sun4m:
	429	case sun4d:
	430	return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
	431	default:
	432	return 0;
	433	}
	434	}
	435
	436	static inline int
	437	__get_iospace (unsigned long addr)
	438	{
	439	switch (sparc_cpu_model){
f5e706ad SR	440	case sun4m:
	441	case sun4d:
	442	return (srmmu_get_pte (addr) >> 28);
	443	default:
	444	return -1;
	445	}
	446	}
	447
	448	extern unsigned long *sparc_valid_addr_bitmap;
	449
	450	/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
	451	#define kern_addr_valid(addr) \
	452	(test_bit(__pa((unsigned long)(addr))>>20, sparc_valid_addr_bitmap))
	453
f5e706ad SR	454	/*
	455	* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
	456	* its high 4 bits. These macros/functions put it there or get it from there.
	457	*/
	458	#define MK_IOSPACE_PFN(space, pfn) (pfn \| (space << (BITS_PER_LONG - 4)))
	459	#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
	460	#define GET_PFN(pfn) (pfn & 0x0fffffffUL)
	461
3e37fd31 DM	462	extern int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long,
	463	unsigned long, pgprot_t);
	464
	465	static inline int io_remap_pfn_range(struct vm_area_struct *vma,
	466	unsigned long from, unsigned long pfn,
	467	unsigned long size, pgprot_t prot)
	468	{
	469	unsigned long long offset, space, phys_base;
	470
	471	offset = ((unsigned long long) GET_PFN(pfn)) << PAGE_SHIFT;
	472	space = GET_IOSPACE(pfn);
	473	phys_base = offset \| (space << 32ULL);
	474
	475	return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
	476	}
	477
f5e706ad SR	478	#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
	479	#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
	480	({ \
	481	int __changed = !pte_same(*(__ptep), __entry); \
	482	if (__changed) { \
	483	set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
	484	flush_tlb_page(__vma, __address); \
	485	} \
1ee0e144	486	__changed; \
f5e706ad SR	487	})
	488
	489	#include <asm-generic/pgtable.h>
	490
	491	#endif /* !(__ASSEMBLY__) */
	492
eb485d64	493	#define VMALLOC_START _AC(0xfe600000,UL)
eb485d64	494	#define VMALLOC_END _AC(0xffc00000,UL)
f5e706ad	495
f5e706ad SR	496	/* We provide our own get_unmapped_area to cope with VA holes for userland */
	497	#define HAVE_ARCH_UNMAPPED_AREA
	498
	499	/*
	500	* No page table caches to initialise
	501	*/
	502	#define pgtable_cache_init() do { } while (0)
	503
	504	#endif /* !(_SPARC_PGTABLE_H) */