Commit | Line | Data |
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f5e706ad SR |
1 | #ifndef _SPARC64_TLBFLUSH_H |
2 | #define _SPARC64_TLBFLUSH_H | |
3 | ||
f5e706ad SR |
4 | #include <asm/mmu_context.h> |
5 | ||
6 | /* TSB flush operations. */ | |
90f08e39 PZ |
7 | |
8 | #define TLB_BATCH_NR 192 | |
9 | ||
10 | struct tlb_batch { | |
11 | struct mm_struct *mm; | |
12 | unsigned long tlb_nr; | |
f36391d2 | 13 | unsigned long active; |
90f08e39 PZ |
14 | unsigned long vaddrs[TLB_BATCH_NR]; |
15 | }; | |
16 | ||
f05a6865 SR |
17 | void flush_tsb_kernel_range(unsigned long start, unsigned long end); |
18 | void flush_tsb_user(struct tlb_batch *tb); | |
19 | void flush_tsb_user_page(struct mm_struct *mm, unsigned long vaddr); | |
f5e706ad SR |
20 | |
21 | /* TLB flush operations. */ | |
22 | ||
f36391d2 DM |
23 | static inline void flush_tlb_mm(struct mm_struct *mm) |
24 | { | |
25 | } | |
26 | ||
27 | static inline void flush_tlb_page(struct vm_area_struct *vma, | |
28 | unsigned long vmaddr) | |
29 | { | |
30 | } | |
31 | ||
32 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
33 | unsigned long start, unsigned long end) | |
34 | { | |
35 | } | |
36 | ||
37 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
f5e706ad | 38 | |
f05a6865 SR |
39 | void flush_tlb_pending(void); |
40 | void arch_enter_lazy_mmu_mode(void); | |
41 | void arch_leave_lazy_mmu_mode(void); | |
f36391d2 | 42 | #define arch_flush_lazy_mmu_mode() do {} while (0) |
f5e706ad SR |
43 | |
44 | /* Local cpu only. */ | |
f05a6865 SR |
45 | void __flush_tlb_all(void); |
46 | void __flush_tlb_page(unsigned long context, unsigned long vaddr); | |
47 | void __flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
f5e706ad SR |
48 | |
49 | #ifndef CONFIG_SMP | |
50 | ||
51 | #define flush_tlb_kernel_range(start,end) \ | |
52 | do { flush_tsb_kernel_range(start,end); \ | |
53 | __flush_tlb_kernel_range(start,end); \ | |
54 | } while (0) | |
55 | ||
f36391d2 DM |
56 | static inline void global_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr) |
57 | { | |
58 | __flush_tlb_page(CTX_HWBITS(mm->context), vaddr); | |
59 | } | |
60 | ||
f5e706ad SR |
61 | #else /* CONFIG_SMP */ |
62 | ||
f05a6865 SR |
63 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end); |
64 | void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr); | |
f5e706ad SR |
65 | |
66 | #define flush_tlb_kernel_range(start, end) \ | |
67 | do { flush_tsb_kernel_range(start,end); \ | |
68 | smp_flush_tlb_kernel_range(start, end); \ | |
69 | } while (0) | |
70 | ||
f36391d2 DM |
71 | #define global_flush_tlb_page(mm, vaddr) \ |
72 | smp_flush_tlb_page(mm, vaddr) | |
73 | ||
f5e706ad SR |
74 | #endif /* ! CONFIG_SMP */ |
75 | ||
76 | #endif /* _SPARC64_TLBFLUSH_H */ |