projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | #ifndef _SPARC_VAC_OPS_H |
| 2 | #define _SPARC_VAC_OPS_H | |
| 3 | ||
| 4 | /* vac-ops.h: Inline assembly routines to do operations on the Sparc | |
| 5 | * VAC (virtual address cache) for the sun4c. | |
| 6 | * | |
| 7 | * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu) | |
| 8 | */ | |
| 9 | ||
| 1da177e4 LT |
10 | #include <asm/sysen.h> |
| 11 | #include <asm/contregs.h> | |
| 12 | #include <asm/asi.h> | |
| 13 | ||
| 14 | /* The SUN4C models have a virtually addressed write-through | |
| 15 | * cache. | |
| 16 | * | |
| 17 | * The cache tags are directly accessible through an ASI and | |
| 18 | * each have the form: | |
| 19 | * | |
| 20 | * ------------------------------------------------------------ | |
| 21 | * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ | | |
| 22 | * ------------------------------------------------------------ | |
| 23 | * 31 25 24 22 21 20 19 18 16 15 2 1 0 | |
| 24 | * | |
| 25 | * MBZ: These bits are either unused and/or reserved and should | |
| 26 | * be written as zeroes. | |
| 27 | * | |
| 28 | * CONTEXT: Records the context to which this cache line belongs. | |
| 29 | * | |
| 30 | * WRITE: A copy of the writable bit from the mmu pte access bits. | |
| 31 | * | |
| 32 | * PRIV: A copy of the privileged bit from the pte access bits. | |
| 33 | * | |
| 34 | * VALID: If set, this line is valid, else invalid. | |
| 35 | * | |
| 36 | * TagID: Fourteen bits of tag ID. | |
| 37 | * | |
| 38 | * Every virtual address is seen by the cache like this: | |
| 39 | * | |
| 40 | * ---------------------------------------- | |
| 41 | * | RESV | TagID | LINE | BYTE-in-LINE | | |
| 42 | * ---------------------------------------- | |
| 43 | * 31 30 29 16 15 4 3 0 | |
| 44 | * | |
| 45 | * RESV: Unused/reserved. | |
| 46 | * | |
| 47 | * TagID: Used to match the Tag-ID in that vac tags. | |
| 48 | * | |
| 49 | * LINE: Which line within the cache | |
| 50 | * | |
| 51 | * BYTE-in-LINE: Which byte within the cache line. | |
| 52 | */ | |
| 53 | ||
| 54 | /* Sun4c VAC Tags */ | |
| 55 | #define S4CVACTAG_CID 0x01c00000 | |
| 56 | #define S4CVACTAG_W 0x00200000 | |
| 57 | #define S4CVACTAG_P 0x00100000 | |
| 58 | #define S4CVACTAG_V 0x00080000 | |
| 59 | #define S4CVACTAG_TID 0x0000fffc | |
| 60 | ||
| 61 | /* Sun4c VAC Virtual Address */ | |
| 62 | /* These aren't used, why bother? (Anton) */ | |
| 63 | #if 0 | |
| 64 | #define S4CVACVA_TID 0x3fff0000 | |
| 65 | #define S4CVACVA_LINE 0x0000fff0 | |
| 66 | #define S4CVACVA_BIL 0x0000000f | |
| 67 | #endif | |
| 68 | ||
| 69 | /* The indexing of cache lines creates a problem. Because the line | |
| 70 | * field of a virtual address extends past the page offset within | |
| 71 | * the virtual address it is possible to have what are called | |
| 72 | * 'bad aliases' which will create inconsistencies. So we must make | |
| 73 | * sure that within a context that if a physical page is mapped | |
| 74 | * more than once, that 'extra' line bits are the same. If this is | |
| 75 | * not the case, and thus is a 'bad alias' we must turn off the | |
| 76 | * cacheable bit in the pte's of all such pages. | |
| 77 | */ | |
| 78 | ||
| 1da177e4 | 79 | #define S4CVAC_BADBITS 0x0000f000 |
| 1da177e4 LT |
80 | |
| 81 | /* The following is true if vaddr1 and vaddr2 would cause | |
| 82 | * a 'bad alias'. | |
| 83 | */ | |
| 84 | #define S4CVAC_BADALIAS(vaddr1, vaddr2) \ | |
| 85 | ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \ | |
| 86 | (S4CVAC_BADBITS)) | |
| 87 | ||
| 88 | /* The following structure describes the characteristics of a sun4c | |
| 89 | * VAC as probed from the prom during boot time. | |
| 90 | */ | |
| 91 | struct sun4c_vac_props { | |
| 92 | unsigned int num_bytes; /* Size of the cache */ | |
| 1da177e4 | 93 | unsigned int do_hwflushes; /* Hardware flushing available? */ |
| 1da177e4 LT |
94 | unsigned int linesize; /* Size of each line in bytes */ |
| 95 | unsigned int log2lsize; /* log2(linesize) */ | |
| 96 | unsigned int on; /* VAC is enabled */ | |
| 97 | }; | |
| 98 | ||
| 99 | extern struct sun4c_vac_props sun4c_vacinfo; | |
| 100 | ||
| 101 | /* sun4c_enable_vac() enables the sun4c virtual address cache. */ | |
| 102 | static inline void sun4c_enable_vac(void) | |
| 103 | { | |
| 104 | __asm__ __volatile__("lduba [%0] %1, %%g1\n\t" | |
| 105 | "or %%g1, %2, %%g1\n\t" | |
| 106 | "stba %%g1, [%0] %1\n\t" | |
| 107 | : /* no outputs */ | |
| 108 | : "r" ((unsigned int) AC_SENABLE), | |
| 109 | "i" (ASI_CONTROL), "i" (SENABLE_CACHE) | |
| 110 | : "g1", "memory"); | |
| 111 | sun4c_vacinfo.on = 1; | |
| 112 | } | |
| 113 | ||
| 114 | /* sun4c_disable_vac() disables the virtual address cache. */ | |
| 115 | static inline void sun4c_disable_vac(void) | |
| 116 | { | |
| 117 | __asm__ __volatile__("lduba [%0] %1, %%g1\n\t" | |
| 118 | "andn %%g1, %2, %%g1\n\t" | |
| 119 | "stba %%g1, [%0] %1\n\t" | |
| 120 | : /* no outputs */ | |
| 121 | : "r" ((unsigned int) AC_SENABLE), | |
| 122 | "i" (ASI_CONTROL), "i" (SENABLE_CACHE) | |
| 123 | : "g1", "memory"); | |
| 124 | sun4c_vacinfo.on = 0; | |
| 125 | } | |
| 126 | ||
| 127 | #endif /* !(_SPARC_VAC_OPS_H) */ |