Commit | Line | Data |
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6eda3a75 DM |
1 | /* These get patched into the trap table at boot time |
2 | * once we know we have a cheetah processor. | |
3 | */ | |
4 | .globl cheetah_fecc_trap_vector | |
5 | .type cheetah_fecc_trap_vector,#function | |
6 | cheetah_fecc_trap_vector: | |
7 | membar #Sync | |
8 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
9 | andn %g1, DCU_DC | DCU_IC, %g1 | |
10 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
11 | membar #Sync | |
12 | sethi %hi(cheetah_fast_ecc), %g2 | |
13 | jmpl %g2 + %lo(cheetah_fast_ecc), %g0 | |
14 | mov 0, %g1 | |
15 | .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector | |
16 | ||
17 | .globl cheetah_fecc_trap_vector_tl1 | |
18 | .type cheetah_fecc_trap_vector_tl1,#function | |
19 | cheetah_fecc_trap_vector_tl1: | |
20 | membar #Sync | |
21 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
22 | andn %g1, DCU_DC | DCU_IC, %g1 | |
23 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
24 | membar #Sync | |
25 | sethi %hi(cheetah_fast_ecc), %g2 | |
26 | jmpl %g2 + %lo(cheetah_fast_ecc), %g0 | |
27 | mov 1, %g1 | |
28 | .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1 | |
29 | ||
30 | .globl cheetah_cee_trap_vector | |
31 | .type cheetah_cee_trap_vector,#function | |
32 | cheetah_cee_trap_vector: | |
33 | membar #Sync | |
34 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
35 | andn %g1, DCU_IC, %g1 | |
36 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
37 | membar #Sync | |
38 | sethi %hi(cheetah_cee), %g2 | |
39 | jmpl %g2 + %lo(cheetah_cee), %g0 | |
40 | mov 0, %g1 | |
41 | .size cheetah_cee_trap_vector,.-cheetah_cee_trap_vector | |
42 | ||
43 | .globl cheetah_cee_trap_vector_tl1 | |
44 | .type cheetah_cee_trap_vector_tl1,#function | |
45 | cheetah_cee_trap_vector_tl1: | |
46 | membar #Sync | |
47 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
48 | andn %g1, DCU_IC, %g1 | |
49 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
50 | membar #Sync | |
51 | sethi %hi(cheetah_cee), %g2 | |
52 | jmpl %g2 + %lo(cheetah_cee), %g0 | |
53 | mov 1, %g1 | |
54 | .size cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1 | |
55 | ||
56 | .globl cheetah_deferred_trap_vector | |
57 | .type cheetah_deferred_trap_vector,#function | |
58 | cheetah_deferred_trap_vector: | |
59 | membar #Sync | |
60 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; | |
61 | andn %g1, DCU_DC | DCU_IC, %g1; | |
62 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG; | |
63 | membar #Sync; | |
64 | sethi %hi(cheetah_deferred_trap), %g2 | |
65 | jmpl %g2 + %lo(cheetah_deferred_trap), %g0 | |
66 | mov 0, %g1 | |
67 | .size cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector | |
68 | ||
69 | .globl cheetah_deferred_trap_vector_tl1 | |
70 | .type cheetah_deferred_trap_vector_tl1,#function | |
71 | cheetah_deferred_trap_vector_tl1: | |
72 | membar #Sync; | |
73 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; | |
74 | andn %g1, DCU_DC | DCU_IC, %g1; | |
75 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG; | |
76 | membar #Sync; | |
77 | sethi %hi(cheetah_deferred_trap), %g2 | |
78 | jmpl %g2 + %lo(cheetah_deferred_trap), %g0 | |
79 | mov 1, %g1 | |
80 | .size cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1 | |
81 | ||
82 | /* Cheetah+ specific traps. These are for the new I/D cache parity | |
83 | * error traps. The first argument to cheetah_plus_parity_handler | |
84 | * is encoded as follows: | |
85 | * | |
86 | * Bit0: 0=dcache,1=icache | |
87 | * Bit1: 0=recoverable,1=unrecoverable | |
88 | */ | |
89 | .globl cheetah_plus_dcpe_trap_vector | |
90 | .type cheetah_plus_dcpe_trap_vector,#function | |
91 | cheetah_plus_dcpe_trap_vector: | |
92 | membar #Sync | |
93 | sethi %hi(do_cheetah_plus_data_parity), %g7 | |
94 | jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0 | |
95 | nop | |
96 | nop | |
97 | nop | |
98 | nop | |
99 | nop | |
100 | .size cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector | |
101 | ||
102 | .type do_cheetah_plus_data_parity,#function | |
103 | do_cheetah_plus_data_parity: | |
104 | rdpr %pil, %g2 | |
b4f4372f | 105 | wrpr %g0, PIL_NORMAL_MAX, %pil |
6eda3a75 DM |
106 | ba,pt %xcc, etrap_irq |
107 | rd %pc, %g7 | |
108 | #ifdef CONFIG_TRACE_IRQFLAGS | |
109 | call trace_hardirqs_off | |
110 | nop | |
111 | #endif | |
112 | mov 0x0, %o0 | |
113 | call cheetah_plus_parity_error | |
114 | add %sp, PTREGS_OFF, %o1 | |
115 | ba,a,pt %xcc, rtrap_irq | |
116 | .size do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity | |
117 | ||
118 | .globl cheetah_plus_dcpe_trap_vector_tl1 | |
119 | .type cheetah_plus_dcpe_trap_vector_tl1,#function | |
120 | cheetah_plus_dcpe_trap_vector_tl1: | |
121 | membar #Sync | |
122 | wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate | |
123 | sethi %hi(do_dcpe_tl1), %g3 | |
124 | jmpl %g3 + %lo(do_dcpe_tl1), %g0 | |
125 | nop | |
126 | nop | |
127 | nop | |
128 | nop | |
129 | .size cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1 | |
130 | ||
131 | .globl cheetah_plus_icpe_trap_vector | |
132 | .type cheetah_plus_icpe_trap_vector,#function | |
133 | cheetah_plus_icpe_trap_vector: | |
134 | membar #Sync | |
135 | sethi %hi(do_cheetah_plus_insn_parity), %g7 | |
136 | jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0 | |
137 | nop | |
138 | nop | |
139 | nop | |
140 | nop | |
141 | nop | |
142 | .size cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector | |
143 | ||
144 | .type do_cheetah_plus_insn_parity,#function | |
145 | do_cheetah_plus_insn_parity: | |
146 | rdpr %pil, %g2 | |
b4f4372f | 147 | wrpr %g0, PIL_NORMAL_MAX, %pil |
6eda3a75 DM |
148 | ba,pt %xcc, etrap_irq |
149 | rd %pc, %g7 | |
150 | #ifdef CONFIG_TRACE_IRQFLAGS | |
151 | call trace_hardirqs_off | |
152 | nop | |
153 | #endif | |
154 | mov 0x1, %o0 | |
155 | call cheetah_plus_parity_error | |
156 | add %sp, PTREGS_OFF, %o1 | |
157 | ba,a,pt %xcc, rtrap_irq | |
158 | .size do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity | |
159 | ||
160 | .globl cheetah_plus_icpe_trap_vector_tl1 | |
161 | .type cheetah_plus_icpe_trap_vector_tl1,#function | |
162 | cheetah_plus_icpe_trap_vector_tl1: | |
163 | membar #Sync | |
164 | wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate | |
165 | sethi %hi(do_icpe_tl1), %g3 | |
166 | jmpl %g3 + %lo(do_icpe_tl1), %g0 | |
167 | nop | |
168 | nop | |
169 | nop | |
170 | nop | |
171 | .size cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1 | |
172 | ||
173 | /* If we take one of these traps when tl >= 1, then we | |
174 | * jump to interrupt globals. If some trap level above us | |
175 | * was also using interrupt globals, we cannot recover. | |
176 | * We may use all interrupt global registers except %g6. | |
177 | */ | |
178 | .globl do_dcpe_tl1 | |
179 | .type do_dcpe_tl1,#function | |
180 | do_dcpe_tl1: | |
181 | rdpr %tl, %g1 ! Save original trap level | |
182 | mov 1, %g2 ! Setup TSTATE checking loop | |
183 | sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit | |
184 | 1: wrpr %g2, %tl ! Set trap level to check | |
185 | rdpr %tstate, %g4 ! Read TSTATE for this level | |
186 | andcc %g4, %g3, %g0 ! Interrupt globals in use? | |
187 | bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable | |
188 | wrpr %g1, %tl ! Restore original trap level | |
189 | add %g2, 1, %g2 ! Next trap level | |
190 | cmp %g2, %g1 ! Hit them all yet? | |
191 | ble,pt %icc, 1b ! Not yet | |
192 | nop | |
193 | wrpr %g1, %tl ! Restore original trap level | |
194 | do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ | |
195 | sethi %hi(dcache_parity_tl1_occurred), %g2 | |
196 | lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1 | |
197 | add %g1, 1, %g1 | |
198 | stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)] | |
199 | /* Reset D-cache parity */ | |
200 | sethi %hi(1 << 16), %g1 ! D-cache size | |
201 | mov (1 << 5), %g2 ! D-cache line size | |
202 | sub %g1, %g2, %g1 ! Move down 1 cacheline | |
203 | 1: srl %g1, 14, %g3 ! Compute UTAG | |
204 | membar #Sync | |
205 | stxa %g3, [%g1] ASI_DCACHE_UTAG | |
206 | membar #Sync | |
207 | sub %g2, 8, %g3 ! 64-bit data word within line | |
208 | 2: membar #Sync | |
209 | stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA | |
210 | membar #Sync | |
211 | subcc %g3, 8, %g3 ! Next 64-bit data word | |
212 | bge,pt %icc, 2b | |
213 | nop | |
214 | subcc %g1, %g2, %g1 ! Next cacheline | |
215 | bge,pt %icc, 1b | |
216 | nop | |
217 | ba,pt %xcc, dcpe_icpe_tl1_common | |
218 | nop | |
219 | ||
220 | do_dcpe_tl1_fatal: | |
221 | sethi %hi(1f), %g7 | |
222 | ba,pt %xcc, etraptl1 | |
223 | 1: or %g7, %lo(1b), %g7 | |
224 | mov 0x2, %o0 | |
225 | call cheetah_plus_parity_error | |
226 | add %sp, PTREGS_OFF, %o1 | |
227 | ba,pt %xcc, rtrap | |
228 | nop | |
229 | .size do_dcpe_tl1,.-do_dcpe_tl1 | |
230 | ||
231 | .globl do_icpe_tl1 | |
232 | .type do_icpe_tl1,#function | |
233 | do_icpe_tl1: | |
234 | rdpr %tl, %g1 ! Save original trap level | |
235 | mov 1, %g2 ! Setup TSTATE checking loop | |
236 | sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit | |
237 | 1: wrpr %g2, %tl ! Set trap level to check | |
238 | rdpr %tstate, %g4 ! Read TSTATE for this level | |
239 | andcc %g4, %g3, %g0 ! Interrupt globals in use? | |
240 | bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable | |
241 | wrpr %g1, %tl ! Restore original trap level | |
242 | add %g2, 1, %g2 ! Next trap level | |
243 | cmp %g2, %g1 ! Hit them all yet? | |
244 | ble,pt %icc, 1b ! Not yet | |
245 | nop | |
246 | wrpr %g1, %tl ! Restore original trap level | |
247 | do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ | |
248 | sethi %hi(icache_parity_tl1_occurred), %g2 | |
249 | lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1 | |
250 | add %g1, 1, %g1 | |
251 | stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)] | |
252 | /* Flush I-cache */ | |
253 | sethi %hi(1 << 15), %g1 ! I-cache size | |
254 | mov (1 << 5), %g2 ! I-cache line size | |
255 | sub %g1, %g2, %g1 | |
256 | 1: or %g1, (2 << 3), %g3 | |
257 | stxa %g0, [%g3] ASI_IC_TAG | |
258 | membar #Sync | |
259 | subcc %g1, %g2, %g1 | |
260 | bge,pt %icc, 1b | |
261 | nop | |
262 | ba,pt %xcc, dcpe_icpe_tl1_common | |
263 | nop | |
264 | ||
265 | do_icpe_tl1_fatal: | |
266 | sethi %hi(1f), %g7 | |
267 | ba,pt %xcc, etraptl1 | |
268 | 1: or %g7, %lo(1b), %g7 | |
269 | mov 0x3, %o0 | |
270 | call cheetah_plus_parity_error | |
271 | add %sp, PTREGS_OFF, %o1 | |
272 | ba,pt %xcc, rtrap | |
273 | nop | |
274 | .size do_icpe_tl1,.-do_icpe_tl1 | |
275 | ||
276 | .type dcpe_icpe_tl1_common,#function | |
277 | dcpe_icpe_tl1_common: | |
278 | /* Flush D-cache, re-enable D/I caches in DCU and finally | |
279 | * retry the trapping instruction. | |
280 | */ | |
281 | sethi %hi(1 << 16), %g1 ! D-cache size | |
282 | mov (1 << 5), %g2 ! D-cache line size | |
283 | sub %g1, %g2, %g1 | |
284 | 1: stxa %g0, [%g1] ASI_DCACHE_TAG | |
285 | membar #Sync | |
286 | subcc %g1, %g2, %g1 | |
287 | bge,pt %icc, 1b | |
288 | nop | |
289 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
290 | or %g1, (DCU_DC | DCU_IC), %g1 | |
291 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
292 | membar #Sync | |
293 | retry | |
294 | .size dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common | |
295 | ||
296 | /* Capture I/D/E-cache state into per-cpu error scoreboard. | |
297 | * | |
298 | * %g1: (TL>=0) ? 1 : 0 | |
299 | * %g2: scratch | |
300 | * %g3: scratch | |
301 | * %g4: AFSR | |
302 | * %g5: AFAR | |
303 | * %g6: unused, will have current thread ptr after etrap | |
304 | * %g7: scratch | |
305 | */ | |
306 | .type __cheetah_log_error,#function | |
307 | __cheetah_log_error: | |
308 | /* Put "TL1" software bit into AFSR. */ | |
309 | and %g1, 0x1, %g1 | |
310 | sllx %g1, 63, %g2 | |
311 | or %g4, %g2, %g4 | |
312 | ||
313 | /* Get log entry pointer for this cpu at this trap level. */ | |
314 | BRANCH_IF_JALAPENO(g2,g3,50f) | |
315 | ldxa [%g0] ASI_SAFARI_CONFIG, %g2 | |
316 | srlx %g2, 17, %g2 | |
317 | ba,pt %xcc, 60f | |
318 | and %g2, 0x3ff, %g2 | |
319 | ||
320 | 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2 | |
321 | srlx %g2, 17, %g2 | |
322 | and %g2, 0x1f, %g2 | |
323 | ||
324 | 60: sllx %g2, 9, %g2 | |
325 | sethi %hi(cheetah_error_log), %g3 | |
326 | ldx [%g3 + %lo(cheetah_error_log)], %g3 | |
327 | brz,pn %g3, 80f | |
328 | nop | |
329 | ||
330 | add %g3, %g2, %g3 | |
331 | sllx %g1, 8, %g1 | |
332 | add %g3, %g1, %g1 | |
333 | ||
334 | /* %g1 holds pointer to the top of the logging scoreboard */ | |
335 | ldx [%g1 + 0x0], %g7 | |
336 | cmp %g7, -1 | |
337 | bne,pn %xcc, 80f | |
338 | nop | |
339 | ||
340 | stx %g4, [%g1 + 0x0] | |
341 | stx %g5, [%g1 + 0x8] | |
342 | add %g1, 0x10, %g1 | |
343 | ||
344 | /* %g1 now points to D-cache logging area */ | |
345 | set 0x3ff8, %g2 /* DC_addr mask */ | |
346 | and %g5, %g2, %g2 /* DC_addr bits of AFAR */ | |
347 | srlx %g5, 12, %g3 | |
348 | or %g3, 1, %g3 /* PHYS tag + valid */ | |
349 | ||
350 | 10: ldxa [%g2] ASI_DCACHE_TAG, %g7 | |
351 | cmp %g3, %g7 /* TAG match? */ | |
352 | bne,pt %xcc, 13f | |
353 | nop | |
354 | ||
355 | /* Yep, what we want, capture state. */ | |
356 | stx %g2, [%g1 + 0x20] | |
357 | stx %g7, [%g1 + 0x28] | |
358 | ||
359 | /* A membar Sync is required before and after utag access. */ | |
360 | membar #Sync | |
361 | ldxa [%g2] ASI_DCACHE_UTAG, %g7 | |
362 | membar #Sync | |
363 | stx %g7, [%g1 + 0x30] | |
364 | ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7 | |
365 | stx %g7, [%g1 + 0x38] | |
366 | clr %g3 | |
367 | ||
368 | 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7 | |
369 | stx %g7, [%g1] | |
370 | add %g3, (1 << 5), %g3 | |
371 | cmp %g3, (4 << 5) | |
372 | bl,pt %xcc, 12b | |
373 | add %g1, 0x8, %g1 | |
374 | ||
375 | ba,pt %xcc, 20f | |
376 | add %g1, 0x20, %g1 | |
377 | ||
378 | 13: sethi %hi(1 << 14), %g7 | |
379 | add %g2, %g7, %g2 | |
380 | srlx %g2, 14, %g7 | |
381 | cmp %g7, 4 | |
382 | bl,pt %xcc, 10b | |
383 | nop | |
384 | ||
385 | add %g1, 0x40, %g1 | |
386 | ||
387 | /* %g1 now points to I-cache logging area */ | |
388 | 20: set 0x1fe0, %g2 /* IC_addr mask */ | |
389 | and %g5, %g2, %g2 /* IC_addr bits of AFAR */ | |
390 | sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */ | |
391 | srlx %g5, (13 - 8), %g3 /* Make PTAG */ | |
392 | andn %g3, 0xff, %g3 /* Mask off undefined bits */ | |
393 | ||
394 | 21: ldxa [%g2] ASI_IC_TAG, %g7 | |
395 | andn %g7, 0xff, %g7 | |
396 | cmp %g3, %g7 | |
397 | bne,pt %xcc, 23f | |
398 | nop | |
399 | ||
400 | /* Yep, what we want, capture state. */ | |
401 | stx %g2, [%g1 + 0x40] | |
402 | stx %g7, [%g1 + 0x48] | |
403 | add %g2, (1 << 3), %g2 | |
404 | ldxa [%g2] ASI_IC_TAG, %g7 | |
405 | add %g2, (1 << 3), %g2 | |
406 | stx %g7, [%g1 + 0x50] | |
407 | ldxa [%g2] ASI_IC_TAG, %g7 | |
408 | add %g2, (1 << 3), %g2 | |
409 | stx %g7, [%g1 + 0x60] | |
410 | ldxa [%g2] ASI_IC_TAG, %g7 | |
411 | stx %g7, [%g1 + 0x68] | |
412 | sub %g2, (3 << 3), %g2 | |
413 | ldxa [%g2] ASI_IC_STAG, %g7 | |
414 | stx %g7, [%g1 + 0x58] | |
415 | clr %g3 | |
416 | srlx %g2, 2, %g2 | |
417 | ||
418 | 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7 | |
419 | stx %g7, [%g1] | |
420 | add %g3, (1 << 3), %g3 | |
421 | cmp %g3, (8 << 3) | |
422 | bl,pt %xcc, 22b | |
423 | add %g1, 0x8, %g1 | |
424 | ||
425 | ba,pt %xcc, 30f | |
426 | add %g1, 0x30, %g1 | |
427 | ||
428 | 23: sethi %hi(1 << 14), %g7 | |
429 | add %g2, %g7, %g2 | |
430 | srlx %g2, 14, %g7 | |
431 | cmp %g7, 4 | |
432 | bl,pt %xcc, 21b | |
433 | nop | |
434 | ||
435 | add %g1, 0x70, %g1 | |
436 | ||
437 | /* %g1 now points to E-cache logging area */ | |
438 | 30: andn %g5, (32 - 1), %g2 | |
439 | stx %g2, [%g1 + 0x20] | |
440 | ldxa [%g2] ASI_EC_TAG_DATA, %g7 | |
441 | stx %g7, [%g1 + 0x28] | |
442 | ldxa [%g2] ASI_EC_R, %g0 | |
443 | clr %g3 | |
444 | ||
445 | 31: ldxa [%g3] ASI_EC_DATA, %g7 | |
446 | stx %g7, [%g1 + %g3] | |
447 | add %g3, 0x8, %g3 | |
448 | cmp %g3, 0x20 | |
449 | ||
450 | bl,pt %xcc, 31b | |
451 | nop | |
452 | 80: | |
453 | rdpr %tt, %g2 | |
454 | cmp %g2, 0x70 | |
455 | be c_fast_ecc | |
456 | cmp %g2, 0x63 | |
457 | be c_cee | |
458 | nop | |
459 | ba,pt %xcc, c_deferred | |
460 | .size __cheetah_log_error,.-__cheetah_log_error | |
461 | ||
462 | /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc | |
463 | * in the trap table. That code has done a memory barrier | |
464 | * and has disabled both the I-cache and D-cache in the DCU | |
465 | * control register. The I-cache is disabled so that we may | |
466 | * capture the corrupted cache line, and the D-cache is disabled | |
467 | * because corrupt data may have been placed there and we don't | |
468 | * want to reference it. | |
469 | * | |
470 | * %g1 is one if this trap occurred at %tl >= 1. | |
471 | * | |
472 | * Next, we turn off error reporting so that we don't recurse. | |
473 | */ | |
474 | .globl cheetah_fast_ecc | |
475 | .type cheetah_fast_ecc,#function | |
476 | cheetah_fast_ecc: | |
477 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 | |
478 | andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 | |
479 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN | |
480 | membar #Sync | |
481 | ||
482 | /* Fetch and clear AFSR/AFAR */ | |
483 | ldxa [%g0] ASI_AFSR, %g4 | |
484 | ldxa [%g0] ASI_AFAR, %g5 | |
485 | stxa %g4, [%g0] ASI_AFSR | |
486 | membar #Sync | |
487 | ||
488 | ba,pt %xcc, __cheetah_log_error | |
489 | nop | |
490 | .size cheetah_fast_ecc,.-cheetah_fast_ecc | |
491 | ||
492 | .type c_fast_ecc,#function | |
493 | c_fast_ecc: | |
494 | rdpr %pil, %g2 | |
b4f4372f | 495 | wrpr %g0, PIL_NORMAL_MAX, %pil |
6eda3a75 DM |
496 | ba,pt %xcc, etrap_irq |
497 | rd %pc, %g7 | |
498 | #ifdef CONFIG_TRACE_IRQFLAGS | |
499 | call trace_hardirqs_off | |
500 | nop | |
501 | #endif | |
502 | mov %l4, %o1 | |
503 | mov %l5, %o2 | |
504 | call cheetah_fecc_handler | |
505 | add %sp, PTREGS_OFF, %o0 | |
506 | ba,a,pt %xcc, rtrap_irq | |
507 | .size c_fast_ecc,.-c_fast_ecc | |
508 | ||
509 | /* Our caller has disabled I-cache and performed membar Sync. */ | |
510 | .globl cheetah_cee | |
511 | .type cheetah_cee,#function | |
512 | cheetah_cee: | |
513 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 | |
514 | andn %g2, ESTATE_ERROR_CEEN, %g2 | |
515 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN | |
516 | membar #Sync | |
517 | ||
518 | /* Fetch and clear AFSR/AFAR */ | |
519 | ldxa [%g0] ASI_AFSR, %g4 | |
520 | ldxa [%g0] ASI_AFAR, %g5 | |
521 | stxa %g4, [%g0] ASI_AFSR | |
522 | membar #Sync | |
523 | ||
524 | ba,pt %xcc, __cheetah_log_error | |
525 | nop | |
526 | .size cheetah_cee,.-cheetah_cee | |
527 | ||
528 | .type c_cee,#function | |
529 | c_cee: | |
530 | rdpr %pil, %g2 | |
b4f4372f | 531 | wrpr %g0, PIL_NORMAL_MAX, %pil |
6eda3a75 DM |
532 | ba,pt %xcc, etrap_irq |
533 | rd %pc, %g7 | |
534 | #ifdef CONFIG_TRACE_IRQFLAGS | |
535 | call trace_hardirqs_off | |
536 | nop | |
537 | #endif | |
538 | mov %l4, %o1 | |
539 | mov %l5, %o2 | |
540 | call cheetah_cee_handler | |
541 | add %sp, PTREGS_OFF, %o0 | |
542 | ba,a,pt %xcc, rtrap_irq | |
543 | .size c_cee,.-c_cee | |
544 | ||
545 | /* Our caller has disabled I-cache+D-cache and performed membar Sync. */ | |
546 | .globl cheetah_deferred_trap | |
547 | .type cheetah_deferred_trap,#function | |
548 | cheetah_deferred_trap: | |
549 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 | |
550 | andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 | |
551 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN | |
552 | membar #Sync | |
553 | ||
554 | /* Fetch and clear AFSR/AFAR */ | |
555 | ldxa [%g0] ASI_AFSR, %g4 | |
556 | ldxa [%g0] ASI_AFAR, %g5 | |
557 | stxa %g4, [%g0] ASI_AFSR | |
558 | membar #Sync | |
559 | ||
560 | ba,pt %xcc, __cheetah_log_error | |
561 | nop | |
562 | .size cheetah_deferred_trap,.-cheetah_deferred_trap | |
563 | ||
564 | .type c_deferred,#function | |
565 | c_deferred: | |
566 | rdpr %pil, %g2 | |
b4f4372f | 567 | wrpr %g0, PIL_NORMAL_MAX, %pil |
6eda3a75 DM |
568 | ba,pt %xcc, etrap_irq |
569 | rd %pc, %g7 | |
570 | #ifdef CONFIG_TRACE_IRQFLAGS | |
571 | call trace_hardirqs_off | |
572 | nop | |
573 | #endif | |
574 | mov %l4, %o1 | |
575 | mov %l5, %o2 | |
576 | call cheetah_deferred_handler | |
577 | add %sp, PTREGS_OFF, %o0 | |
578 | ba,a,pt %xcc, rtrap_irq | |
579 | .size c_deferred,.-c_deferred |