Commit | Line | Data |
---|---|---|
88278ca2 | 1 | /* |
1da177e4 LT |
2 | * head.S: The initial boot code for the Sparc port of Linux. |
3 | * | |
4 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com) | |
6 | * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
7 | * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
8 | * Copyright (C) 1997 Michael A. Griffith (grif@acm.org) | |
9 | * | |
10 | * CompactPCI platform by Eric Brower, 1999. | |
11 | */ | |
12 | ||
13 | #include <linux/version.h> | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | ||
16 | #include <asm/head.h> | |
17 | #include <asm/asi.h> | |
18 | #include <asm/contregs.h> | |
19 | #include <asm/ptrace.h> | |
20 | #include <asm/psr.h> | |
21 | #include <asm/page.h> | |
19fce2b9 | 22 | #include <asm/kdebug.h> |
1da177e4 LT |
23 | #include <asm/winmacro.h> |
24 | #include <asm/thread_info.h> /* TI_UWINMASK */ | |
25 | #include <asm/errno.h> | |
26 | #include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */ | |
27 | ||
28 | .data | |
eb06f476 SR |
29 | /* The following are used with the prom_vector node-ops to figure out |
30 | * the cpu-type | |
1da177e4 | 31 | */ |
1da177e4 | 32 | .align 4 |
1da177e4 LT |
33 | cputyp: |
34 | .word 1 | |
35 | ||
36 | .align 4 | |
37 | .globl cputypval | |
38 | cputypval: | |
eb06f476 | 39 | .asciz "sun4m" |
1da177e4 LT |
40 | .ascii " " |
41 | ||
eb06f476 | 42 | /* Tested on SS-5, SS-10 */ |
1da177e4 | 43 | .align 4 |
1da177e4 | 44 | cputypvar: |
1da177e4 LT |
45 | .asciz "compatible" |
46 | ||
47 | .align 4 | |
48 | ||
ec24158e SR |
49 | notsup: |
50 | .asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n" | |
1da177e4 | 51 | .align 4 |
1da177e4 LT |
52 | |
53 | sun4e_notsup: | |
54 | .asciz "Sparc-Linux sun4e support does not exist\n\n" | |
55 | .align 4 | |
56 | ||
c64d7524 SR |
57 | /* The trap-table - located in the __HEAD section */ |
58 | #include "ttable_32.S" | |
2c1cfb2d | 59 | |
1da177e4 LT |
60 | .align PAGE_SIZE |
61 | ||
62 | /* This was the only reasonable way I could think of to properly align | |
63 | * these page-table data structures. | |
64 | */ | |
1da177e4 LT |
65 | .globl swapper_pg_dir |
66 | swapper_pg_dir: .skip PAGE_SIZE | |
1b4cb70e | 67 | .globl empty_zero_page |
1da177e4 LT |
68 | empty_zero_page: .skip PAGE_SIZE |
69 | ||
70 | .global root_flags | |
71 | .global ram_flags | |
72 | .global root_dev | |
73 | .global sparc_ramdisk_image | |
74 | .global sparc_ramdisk_size | |
75 | ||
76 | /* This stuff has to be in sync with SILO and other potential boot loaders | |
77 | * Fields should be kept upward compatible and whenever any change is made, | |
78 | * HdrS version should be incremented. | |
79 | */ | |
80 | .ascii "HdrS" | |
81 | .word LINUX_VERSION_CODE | |
82 | .half 0x0203 /* HdrS version */ | |
83 | root_flags: | |
84 | .half 1 | |
85 | root_dev: | |
86 | .half 0 | |
87 | ram_flags: | |
88 | .half 0 | |
89 | sparc_ramdisk_image: | |
90 | .word 0 | |
91 | sparc_ramdisk_size: | |
92 | .word 0 | |
93 | .word reboot_command | |
94 | .word 0, 0, 0 | |
95 | .word _end | |
96 | ||
97 | /* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in | |
98 | * %g7 and at prom_vector_p. And also quickly check whether we are on | |
99 | * a v0, v2, or v3 prom. | |
100 | */ | |
101 | gokernel: | |
102 | /* Ok, it's nice to know, as early as possible, if we | |
103 | * are already mapped where we expect to be in virtual | |
104 | * memory. The Solaris /boot elf format bootloader | |
105 | * will peek into our elf header and load us where | |
106 | * we want to be, otherwise we have to re-map. | |
107 | * | |
108 | * Some boot loaders don't place the jmp'rs address | |
109 | * in %o7, so we do a pc-relative call to a local | |
110 | * label, then see what %o7 has. | |
111 | */ | |
112 | ||
113 | mov %o7, %g4 ! Save %o7 | |
114 | ||
115 | /* Jump to it, and pray... */ | |
116 | current_pc: | |
117 | call 1f | |
118 | nop | |
119 | ||
120 | 1: | |
121 | mov %o7, %g3 | |
122 | ||
123 | tst %o0 | |
124 | be no_sun4u_here | |
125 | mov %g4, %o7 /* Previous %o7. */ | |
ec24158e | 126 | |
1da177e4 LT |
127 | mov %o0, %l0 ! stash away romvec |
128 | mov %o0, %g7 ! put it here too | |
129 | mov %o1, %l1 ! stash away debug_vec too | |
130 | ||
131 | /* Ok, let's check out our run time program counter. */ | |
132 | set current_pc, %g5 | |
133 | cmp %g3, %g5 | |
134 | be already_mapped | |
ec24158e | 135 | nop |
1da177e4 LT |
136 | |
137 | /* %l6 will hold the offset we have to subtract | |
138 | * from absolute symbols in order to access areas | |
139 | * in our own image. If already mapped this is | |
140 | * just plain zero, else it is KERNBASE. | |
141 | */ | |
142 | set KERNBASE, %l6 | |
143 | b copy_prom_lvl14 | |
144 | nop | |
145 | ||
146 | already_mapped: | |
147 | mov 0, %l6 | |
148 | ||
149 | /* Copy over the Prom's level 14 clock handler. */ | |
150 | copy_prom_lvl14: | |
151 | #if 1 | |
152 | /* DJHR | |
153 | * preserve our linked/calculated instructions | |
154 | */ | |
155 | set lvl14_save, %g1 | |
156 | set t_irq14, %g3 | |
157 | sub %g1, %l6, %g1 ! translate to physical | |
158 | sub %g3, %l6, %g3 ! translate to physical | |
159 | ldd [%g3], %g4 | |
160 | std %g4, [%g1] | |
161 | ldd [%g3+8], %g4 | |
162 | std %g4, [%g1+8] | |
163 | #endif | |
164 | rd %tbr, %g1 | |
165 | andn %g1, 0xfff, %g1 ! proms trap table base | |
166 | or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr | |
167 | or %g1, %g2, %g2 | |
168 | set t_irq14, %g3 | |
169 | sub %g3, %l6, %g3 | |
170 | ldd [%g2], %g4 | |
171 | std %g4, [%g3] | |
172 | ldd [%g2 + 0x8], %g4 | |
173 | std %g4, [%g3 + 0x8] ! Copy proms handler | |
174 | ||
323206a1 SR |
175 | /* DON'T TOUCH %l0 thru %l5 in these remapping routines, |
176 | * we need their values afterwards! | |
1da177e4 | 177 | */ |
323206a1 | 178 | |
1da177e4 LT |
179 | /* Now check whether we are already mapped, if we |
180 | * are we can skip all this garbage coming up. | |
181 | */ | |
182 | copy_prom_done: | |
183 | cmp %l6, 0 | |
184 | be go_to_highmem ! this will be a nop then | |
185 | nop | |
186 | ||
9b4c514a DM |
187 | /* Validate that we are in fact running on an |
188 | * SRMMU based cpu. | |
189 | */ | |
190 | set 0x4000, %g6 | |
191 | cmp %g7, %g6 | |
192 | bne not_a_sun4 | |
193 | nop | |
194 | ||
7b372d65 | 195 | halt_notsup: |
9b4c514a | 196 | ld [%g7 + 0x68], %o1 |
ec24158e | 197 | set notsup, %o0 |
9b4c514a DM |
198 | sub %o0, %l6, %o0 |
199 | call %o1 | |
200 | nop | |
201 | ba halt_me | |
202 | nop | |
203 | ||
204 | not_a_sun4: | |
7b372d65 SR |
205 | /* It looks like this is a machine we support. |
206 | * Now find out what MMU we are dealing with | |
207 | * LEON - identified by the psr.impl field | |
208 | * Viking - identified by the psr.impl field | |
209 | * In all other cases a sun4m srmmu. | |
210 | * We check that the MMU is enabled in all cases. | |
211 | */ | |
212 | ||
213 | /* Check if this is a LEON CPU */ | |
214 | rd %psr, %g3 | |
215 | srl %g3, PSR_IMPL_SHIFT, %g3 | |
216 | and %g3, PSR_IMPL_SHIFTED_MASK, %g3 | |
217 | cmp %g3, PSR_IMPL_LEON | |
218 | be leon_remap /* It is a LEON - jump */ | |
219 | nop | |
220 | ||
221 | /* Sanity-check, is MMU enabled */ | |
9b4c514a DM |
222 | lda [%g0] ASI_M_MMUREGS, %g1 |
223 | andcc %g1, 1, %g0 | |
7b372d65 | 224 | be halt_notsup |
9b4c514a DM |
225 | nop |
226 | ||
7b372d65 SR |
227 | /* Check for a viking (TI) module. */ |
228 | cmp %g3, PSR_IMPL_TI | |
229 | bne srmmu_not_viking | |
1da177e4 LT |
230 | nop |
231 | ||
232 | /* Figure out what kind of viking we are on. | |
233 | * We need to know if we have to play with the | |
234 | * AC bit and disable traps or not. | |
235 | */ | |
236 | ||
237 | /* I've only seen MicroSparc's on SparcClassics with this | |
238 | * bit set. | |
239 | */ | |
240 | set 0x800, %g2 | |
241 | lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg | |
242 | and %g2, %g3, %g3 | |
243 | subcc %g3, 0x0, %g0 | |
7b372d65 | 244 | bnz srmmu_not_viking ! is in mbus mode |
1da177e4 | 245 | nop |
ec24158e | 246 | |
1da177e4 LT |
247 | rd %psr, %g3 ! DO NOT TOUCH %g3 |
248 | andn %g3, PSR_ET, %g2 | |
249 | wr %g2, 0x0, %psr | |
250 | WRITE_PAUSE | |
ec24158e | 251 | |
1da177e4 LT |
252 | /* Get context table pointer, then convert to |
253 | * a physical address, which is 36 bits. | |
254 | */ | |
255 | set AC_M_CTPR, %g4 | |
256 | lda [%g4] ASI_M_MMUREGS, %g4 | |
257 | sll %g4, 0x4, %g4 ! We use this below | |
258 | ! DO NOT TOUCH %g4 | |
259 | ||
260 | /* Set the AC bit in the Viking's MMU control reg. */ | |
261 | lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5 | |
262 | set 0x8000, %g6 ! AC bit mask | |
263 | or %g5, %g6, %g6 ! Or it in... | |
264 | sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes... | |
265 | ||
266 | /* Grrr, why does it seem like every other load/store | |
267 | * on the sun4m is in some ASI space... | |
268 | * Fine with me, let's get the pointer to the level 1 | |
269 | * page table directory and fetch its entry. | |
270 | */ | |
271 | lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr | |
272 | srl %o1, 0x4, %o1 ! Clear low 4 bits | |
273 | sll %o1, 0x8, %o1 ! Make physical | |
ec24158e | 274 | |
1da177e4 LT |
275 | /* Ok, pull in the PTD. */ |
276 | lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd | |
277 | ||
278 | /* Calculate to KERNBASE entry. */ | |
ec24158e | 279 | add %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3 |
1da177e4 LT |
280 | |
281 | /* Poke the entry into the calculated address. */ | |
282 | sta %o2, [%o3] ASI_M_BYPASS | |
283 | ||
284 | /* I don't get it Sun, if you engineered all these | |
285 | * boot loaders and the PROM (thank you for the debugging | |
286 | * features btw) why did you not have them load kernel | |
287 | * images up in high address space, since this is necessary | |
288 | * for ABI compliance anyways? Does this low-mapping provide | |
289 | * enhanced interoperability? | |
290 | * | |
291 | * "The PROM is the computer." | |
292 | */ | |
293 | ||
294 | /* Ok, restore the MMU control register we saved in %g5 */ | |
295 | sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch | |
296 | ||
297 | /* Turn traps back on. We saved it in %g3 earlier. */ | |
298 | wr %g3, 0x0, %psr ! tick tock, tick tock | |
299 | ||
300 | /* Now we burn precious CPU cycles due to bad engineering. */ | |
301 | WRITE_PAUSE | |
302 | ||
303 | /* Wow, all that just to move a 32-bit value from one | |
304 | * place to another... Jump to high memory. | |
305 | */ | |
306 | b go_to_highmem | |
307 | nop | |
308 | ||
7b372d65 | 309 | srmmu_not_viking: |
1da177e4 LT |
310 | /* This works on viking's in Mbus mode and all |
311 | * other MBUS modules. It is virtually the same as | |
312 | * the above madness sans turning traps off and flipping | |
313 | * the AC bit. | |
314 | */ | |
1da177e4 LT |
315 | set AC_M_CTPR, %g1 |
316 | lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr | |
317 | sll %g1, 0x4, %g1 ! make physical addr | |
318 | lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table | |
319 | srl %g1, 0x4, %g1 | |
320 | sll %g1, 0x8, %g1 ! make phys addr for l1 tbl | |
321 | ||
322 | lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 | |
323 | add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 | |
324 | sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry | |
325 | b go_to_highmem | |
326 | nop ! wheee.... | |
327 | ||
1da177e4 | 328 | |
7b372d65 SR |
329 | leon_remap: |
330 | /* Sanity-check, is MMU enabled */ | |
331 | lda [%g0] ASI_LEON_MMUREGS, %g1 | |
332 | andcc %g1, 1, %g0 | |
333 | be halt_notsup | |
334 | nop | |
335 | ||
336 | /* Same code as in the srmmu_not_viking case, | |
337 | * with the LEON ASI for mmuregs | |
338 | */ | |
339 | set AC_M_CTPR, %g1 | |
340 | lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr | |
341 | sll %g1, 0x4, %g1 ! make physical addr | |
342 | lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table | |
343 | srl %g1, 0x4, %g1 | |
344 | sll %g1, 0x8, %g1 ! make phys addr for l1 tbl | |
345 | ||
346 | lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 | |
347 | add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 | |
348 | sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry | |
349 | b go_to_highmem | |
350 | nop ! wheee.... | |
351 | ||
1da177e4 LT |
352 | /* Now do a non-relative jump so that PC is in high-memory */ |
353 | go_to_highmem: | |
354 | set execute_in_high_mem, %g1 | |
355 | jmpl %g1, %g0 | |
356 | nop | |
357 | ||
358 | /* The code above should be at beginning and we have to take care about | |
a0871e8c | 359 | * short jumps, as branching to .init.text section from .text is usually |
1da177e4 LT |
360 | * impossible */ |
361 | __INIT | |
362 | /* Acquire boot time privileged register values, this will help debugging. | |
363 | * I figure out and store nwindows and nwindowsm1 later on. | |
364 | */ | |
365 | execute_in_high_mem: | |
366 | mov %l0, %o0 ! put back romvec | |
367 | mov %l1, %o1 ! and debug_vec | |
368 | ||
369 | sethi %hi(prom_vector_p), %g1 | |
370 | st %o0, [%g1 + %lo(prom_vector_p)] | |
371 | ||
372 | sethi %hi(linux_dbvec), %g1 | |
373 | st %o1, [%g1 + %lo(linux_dbvec)] | |
374 | ||
30005efc SR |
375 | /* Check if this is a LEON CPU. |
376 | * Skip getprops call if it is | |
377 | */ | |
378 | srl %g3, PSR_IMPL_SHIFT, %g3 | |
379 | and %g3, PSR_IMPL_SHIFTED_MASK, %g3 | |
380 | cmp %g3, PSR_IMPL_LEON | |
381 | bne get_cputype | |
1da177e4 | 382 | |
8401707f | 383 | |
30005efc | 384 | /* LEON CPU - set boot_cpu_id */ |
01dae0f0 | 385 | sethi %hi(boot_cpu_id), %g2 ! boot-cpu index |
8401707f | 386 | |
01dae0f0 DH |
387 | #ifdef CONFIG_SMP |
388 | ldub [%g2 + %lo(boot_cpu_id)], %g1 | |
389 | cmp %g1, 0xff ! unset means first CPU | |
30005efc SR |
390 | #ifdef CONFIG_SPARC_LEON |
391 | /* XXX Hack to allow build - remove ifdef later */ | |
01dae0f0 DH |
392 | bne leon_smp_cpu_startup ! continue only with master |
393 | nop | |
30005efc | 394 | #endif |
01dae0f0 DH |
395 | #endif |
396 | /* Get CPU-ID from most significant 4-bit of ASR17 */ | |
397 | rd %asr17, %g1 | |
398 | srl %g1, 28, %g1 | |
8401707f | 399 | |
01dae0f0 DH |
400 | /* Update boot_cpu_id only on boot cpu */ |
401 | stub %g1, [%g2 + %lo(boot_cpu_id)] | |
8401707f | 402 | |
323206a1 | 403 | ba continue_boot |
0fd7ef1f | 404 | nop |
30005efc SR |
405 | |
406 | /* Get the machine type via the mysterious romvec node operations. */ | |
407 | get_cputype: | |
408 | add %g7, 0x1c, %l1 | |
409 | ld [%l1], %l0 | |
410 | ld [%l0], %l0 | |
411 | call %l0 | |
412 | or %g0, %g0, %o0 ! next_node(0) = first_node | |
413 | or %o0, %g0, %g6 | |
414 | ||
415 | sethi %hi(cputypvar), %o1 ! First node has cpu-arch | |
416 | or %o1, %lo(cputypvar), %o1 | |
417 | sethi %hi(cputypval), %o2 ! information, the string | |
418 | or %o2, %lo(cputypval), %o2 | |
419 | ld [%l1], %l0 ! 'compatible' tells | |
420 | ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where | |
421 | call %l0 ! x is one of 'm', 'd' or 'e'. | |
422 | nop ! %o2 holds pointer | |
423 | ! to a buf where above string | |
424 | ! will get stored by the prom. | |
d6ea5573 SR |
425 | |
426 | /* Check to cputype. We may be booted on a sun4u (64 bit box), | |
427 | * and sun4d needs special treatment. | |
428 | */ | |
1da177e4 LT |
429 | set cputypval, %o2 |
430 | ldub [%o2 + 0x4], %l1 | |
431 | ||
d6ea5573 SR |
432 | cmp %l1, 'm' |
433 | be sun4m_init | |
1da177e4 | 434 | cmp %l1, 's' |
d6ea5573 | 435 | be sun4m_init |
1da177e4 | 436 | cmp %l1, 'd' |
d6ea5573 | 437 | be sun4d_init |
1da177e4 LT |
438 | cmp %l1, 'e' |
439 | be no_sun4e_here ! Could be a sun4e. | |
440 | nop | |
441 | b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :)) | |
442 | nop | |
443 | ||
1da177e4 LT |
444 | /* CPUID in bootbus can be found at PA 0xff0140000 */ |
445 | #define SUN4D_BOOTBUS_CPUID 0xf0140000 | |
446 | ||
447 | sun4d_init: | |
448 | /* Need to patch call to handler_irq */ | |
449 | set patch_handler_irq, %g4 | |
450 | set sun4d_handler_irq, %g5 | |
451 | sethi %hi(0x40000000), %g3 ! call | |
452 | sub %g5, %g4, %g5 | |
453 | srl %g5, 2, %g5 | |
454 | or %g5, %g3, %g5 | |
455 | st %g5, [%g4] | |
456 | ||
457 | #ifdef CONFIG_SMP | |
458 | /* Get our CPU id out of bootbus */ | |
459 | set SUN4D_BOOTBUS_CPUID, %g3 | |
460 | lduba [%g3] ASI_M_CTL, %g3 | |
461 | and %g3, 0xf8, %g3 | |
462 | srl %g3, 3, %g4 | |
463 | sta %g4, [%g0] ASI_M_VIKING_TMP1 | |
464 | sethi %hi(boot_cpu_id), %g5 | |
465 | stb %g4, [%g5 + %lo(boot_cpu_id)] | |
1da177e4 LT |
466 | #endif |
467 | ||
468 | /* Fall through to sun4m_init */ | |
469 | ||
470 | sun4m_init: | |
1da177e4 LT |
471 | /* Ok, the PROM could have done funny things and apple cider could still |
472 | * be sitting in the fault status/address registers. Read them all to | |
473 | * clear them so we don't get magic faults later on. | |
474 | */ | |
475 | /* This sucks, apparently this makes Vikings call prom panic, will fix later */ | |
476 | 2: | |
477 | rd %psr, %o1 | |
30005efc | 478 | srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU |
1da177e4 | 479 | |
30005efc | 480 | subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC |
323206a1 | 481 | be continue_boot |
1da177e4 LT |
482 | nop |
483 | ||
484 | set AC_M_SFSR, %o0 | |
485 | lda [%o0] ASI_M_MMUREGS, %g0 | |
486 | set AC_M_SFAR, %o0 | |
487 | lda [%o0] ASI_M_MMUREGS, %g0 | |
488 | ||
489 | /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */ | |
490 | subcc %o1, 0, %g0 | |
323206a1 | 491 | be continue_boot |
1da177e4 LT |
492 | nop |
493 | ||
494 | set AC_M_AFSR, %o0 | |
495 | lda [%o0] ASI_M_MMUREGS, %g0 | |
496 | set AC_M_AFAR, %o0 | |
497 | lda [%o0] ASI_M_MMUREGS, %g0 | |
498 | nop | |
499 | ||
500 | ||
323206a1 | 501 | continue_boot: |
1da177e4 LT |
502 | |
503 | /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's | |
504 | * show-time! | |
505 | */ | |
506 | ||
507 | sethi %hi(cputyp), %o0 | |
508 | st %g4, [%o0 + %lo(cputyp)] | |
509 | ||
510 | /* Turn on Supervisor, EnableFloating, and all the PIL bits. | |
511 | * Also puts us in register window zero with traps off. | |
512 | */ | |
513 | set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2 | |
514 | wr %g2, 0x0, %psr | |
515 | WRITE_PAUSE | |
516 | ||
517 | /* I want a kernel stack NOW! */ | |
518 | set init_thread_union, %g1 | |
519 | set (THREAD_SIZE - STACKFRAME_SZ), %g2 | |
520 | add %g1, %g2, %sp | |
521 | mov 0, %fp /* And for good luck */ | |
522 | ||
523 | /* Zero out our BSS section. */ | |
524 | set __bss_start , %o0 ! First address of BSS | |
86ed40bd | 525 | set _end , %o1 ! Last address of BSS |
1da177e4 | 526 | add %o0, 0x1, %o0 |
ec24158e | 527 | 1: |
1da177e4 LT |
528 | stb %g0, [%o0] |
529 | subcc %o0, %o1, %g0 | |
530 | bl 1b | |
531 | add %o0, 0x1, %o0 | |
532 | ||
5fcafb7a DH |
533 | /* If boot_cpu_id has not been setup by machine specific |
534 | * init-code above we default it to zero. | |
535 | */ | |
536 | sethi %hi(boot_cpu_id), %g2 | |
537 | ldub [%g2 + %lo(boot_cpu_id)], %g3 | |
538 | cmp %g3, 0xff | |
539 | bne 1f | |
540 | nop | |
541 | mov %g0, %g3 | |
542 | stub %g3, [%g2 + %lo(boot_cpu_id)] | |
543 | ||
837ebf0e | 544 | 1: sll %g3, 2, %g3 |
5fcafb7a | 545 | |
1da177e4 LT |
546 | /* Initialize the uwinmask value for init task just in case. |
547 | * But first make current_set[boot_cpu_id] point to something useful. | |
548 | */ | |
549 | set init_thread_union, %g6 | |
550 | set current_set, %g2 | |
551 | #ifdef CONFIG_SMP | |
1da177e4 LT |
552 | st %g6, [%g2] |
553 | add %g2, %g3, %g2 | |
554 | #endif | |
555 | st %g6, [%g2] | |
556 | ||
557 | st %g0, [%g6 + TI_UWINMASK] | |
558 | ||
559 | /* Compute NWINDOWS and stash it away. Now uses %wim trick explained | |
560 | * in the V8 manual. Ok, this method seems to work, Sparc is cool... | |
561 | * No, it doesn't work, have to play the save/readCWP/restore trick. | |
562 | */ | |
563 | ||
564 | wr %g0, 0x0, %wim ! so we do not get a trap | |
565 | WRITE_PAUSE | |
566 | ||
567 | save | |
568 | ||
569 | rd %psr, %g3 | |
570 | ||
571 | restore | |
572 | ||
573 | and %g3, 0x1f, %g3 | |
574 | add %g3, 0x1, %g3 | |
575 | ||
576 | mov 2, %g1 | |
577 | wr %g1, 0x0, %wim ! make window 1 invalid | |
578 | WRITE_PAUSE | |
579 | ||
580 | cmp %g3, 0x7 | |
581 | bne 2f | |
582 | nop | |
583 | ||
584 | /* Adjust our window handling routines to | |
585 | * do things correctly on 7 window Sparcs. | |
586 | */ | |
587 | ||
588 | #define PATCH_INSN(src, dest) \ | |
589 | set src, %g5; \ | |
590 | set dest, %g2; \ | |
591 | ld [%g5], %g4; \ | |
592 | st %g4, [%g2]; | |
ec24158e | 593 | |
1da177e4 LT |
594 | /* Patch for window spills... */ |
595 | PATCH_INSN(spnwin_patch1_7win, spnwin_patch1) | |
596 | PATCH_INSN(spnwin_patch2_7win, spnwin_patch2) | |
597 | PATCH_INSN(spnwin_patch3_7win, spnwin_patch3) | |
598 | ||
599 | /* Patch for window fills... */ | |
600 | PATCH_INSN(fnwin_patch1_7win, fnwin_patch1) | |
601 | PATCH_INSN(fnwin_patch2_7win, fnwin_patch2) | |
602 | ||
603 | /* Patch for trap entry setup... */ | |
604 | PATCH_INSN(tsetup_7win_patch1, tsetup_patch1) | |
605 | PATCH_INSN(tsetup_7win_patch2, tsetup_patch2) | |
606 | PATCH_INSN(tsetup_7win_patch3, tsetup_patch3) | |
607 | PATCH_INSN(tsetup_7win_patch4, tsetup_patch4) | |
608 | PATCH_INSN(tsetup_7win_patch5, tsetup_patch5) | |
609 | PATCH_INSN(tsetup_7win_patch6, tsetup_patch6) | |
610 | ||
611 | /* Patch for returning from traps... */ | |
612 | PATCH_INSN(rtrap_7win_patch1, rtrap_patch1) | |
613 | PATCH_INSN(rtrap_7win_patch2, rtrap_patch2) | |
614 | PATCH_INSN(rtrap_7win_patch3, rtrap_patch3) | |
615 | PATCH_INSN(rtrap_7win_patch4, rtrap_patch4) | |
616 | PATCH_INSN(rtrap_7win_patch5, rtrap_patch5) | |
617 | ||
618 | /* Patch for killing user windows from the register file. */ | |
619 | PATCH_INSN(kuw_patch1_7win, kuw_patch1) | |
620 | ||
621 | /* Now patch the kernel window flush sequences. | |
622 | * This saves 2 traps on every switch and fork. | |
623 | */ | |
624 | set 0x01000000, %g4 | |
625 | set flush_patch_one, %g5 | |
626 | st %g4, [%g5 + 0x18] | |
627 | st %g4, [%g5 + 0x1c] | |
628 | set flush_patch_two, %g5 | |
629 | st %g4, [%g5 + 0x18] | |
630 | st %g4, [%g5 + 0x1c] | |
631 | set flush_patch_three, %g5 | |
632 | st %g4, [%g5 + 0x18] | |
633 | st %g4, [%g5 + 0x1c] | |
634 | set flush_patch_four, %g5 | |
635 | st %g4, [%g5 + 0x18] | |
636 | st %g4, [%g5 + 0x1c] | |
637 | set flush_patch_exception, %g5 | |
638 | st %g4, [%g5 + 0x18] | |
639 | st %g4, [%g5 + 0x1c] | |
640 | set flush_patch_switch, %g5 | |
641 | st %g4, [%g5 + 0x18] | |
642 | st %g4, [%g5 + 0x1c] | |
643 | ||
ec24158e | 644 | 2: |
1da177e4 LT |
645 | sethi %hi(nwindows), %g4 |
646 | st %g3, [%g4 + %lo(nwindows)] ! store final value | |
647 | sub %g3, 0x1, %g3 | |
648 | sethi %hi(nwindowsm1), %g4 | |
649 | st %g3, [%g4 + %lo(nwindowsm1)] | |
650 | ||
651 | /* Here we go, start using Linux's trap table... */ | |
652 | set trapbase, %g3 | |
653 | wr %g3, 0x0, %tbr | |
654 | WRITE_PAUSE | |
655 | ||
656 | /* Finally, turn on traps so that we can call c-code. */ | |
657 | rd %psr, %g3 | |
658 | wr %g3, 0x0, %psr | |
659 | WRITE_PAUSE | |
660 | ||
661 | wr %g3, PSR_ET, %psr | |
662 | WRITE_PAUSE | |
663 | ||
664 | /* First we call prom_init() to set up PROMLIB, then | |
665 | * off to start_kernel(). | |
666 | */ | |
667 | ||
668 | sethi %hi(prom_vector_p), %g5 | |
669 | ld [%g5 + %lo(prom_vector_p)], %o0 | |
670 | call prom_init | |
671 | nop | |
672 | ||
ec24158e | 673 | call start_kernel |
1da177e4 | 674 | nop |
ec24158e | 675 | |
1da177e4 LT |
676 | /* We should not get here. */ |
677 | call halt_me | |
678 | nop | |
5110bd21 | 679 | |
1da177e4 LT |
680 | no_sun4e_here: |
681 | ld [%g7 + 0x68], %o1 | |
682 | set sun4e_notsup, %o0 | |
683 | call %o1 | |
684 | nop | |
685 | b halt_me | |
686 | nop | |
687 | ||
688 | __INITDATA | |
689 | ||
690 | sun4u_1: | |
691 | .asciz "finddevice" | |
692 | .align 4 | |
693 | sun4u_2: | |
694 | .asciz "/chosen" | |
695 | .align 4 | |
696 | sun4u_3: | |
697 | .asciz "getprop" | |
698 | .align 4 | |
699 | sun4u_4: | |
700 | .asciz "stdout" | |
701 | .align 4 | |
702 | sun4u_5: | |
703 | .asciz "write" | |
704 | .align 4 | |
705 | sun4u_6: | |
ec24158e | 706 | .asciz "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r" |
1da177e4 LT |
707 | sun4u_6e: |
708 | .align 4 | |
709 | sun4u_7: | |
710 | .asciz "exit" | |
711 | .align 8 | |
712 | sun4u_a1: | |
713 | .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0 | |
714 | sun4u_r1: | |
715 | .word 0 | |
716 | sun4u_a2: | |
717 | .word 0, sun4u_3, 0, 4, 0, 1, 0 | |
718 | sun4u_i2: | |
719 | .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0 | |
720 | sun4u_r2: | |
721 | .word 0 | |
722 | sun4u_a3: | |
723 | .word 0, sun4u_5, 0, 3, 0, 1, 0 | |
724 | sun4u_i3: | |
725 | .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0 | |
726 | sun4u_r3: | |
727 | .word 0 | |
728 | sun4u_a4: | |
729 | .word 0, sun4u_7, 0, 0, 0, 0 | |
730 | sun4u_r4: | |
731 | ||
732 | __INIT | |
733 | no_sun4u_here: | |
734 | set sun4u_a1, %o0 | |
735 | set current_pc, %l2 | |
736 | cmp %l2, %g3 | |
737 | be 1f | |
738 | mov %o4, %l0 | |
739 | sub %g3, %l2, %l6 | |
740 | add %o0, %l6, %o0 | |
741 | mov %o0, %l4 | |
742 | mov sun4u_r4 - sun4u_a1, %l3 | |
743 | ld [%l4], %l5 | |
744 | 2: | |
745 | add %l4, 4, %l4 | |
746 | cmp %l5, %l2 | |
747 | add %l5, %l6, %l5 | |
748 | bgeu,a 3f | |
749 | st %l5, [%l4 - 4] | |
750 | 3: | |
751 | subcc %l3, 4, %l3 | |
752 | bne 2b | |
753 | ld [%l4], %l5 | |
754 | 1: | |
755 | call %l0 | |
756 | mov %o0, %l1 | |
757 | ||
758 | ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1 | |
759 | add %l1, (sun4u_a2 - sun4u_a1), %o0 | |
760 | call %l0 | |
761 | st %o1, [%o0 + (sun4u_i2 - sun4u_a2)] | |
762 | ||
763 | ld [%l1 + (sun4u_1 - sun4u_a1)], %o1 | |
764 | add %l1, (sun4u_a3 - sun4u_a1), %o0 | |
765 | call %l0 | |
766 | st %o1, [%o0 + (sun4u_i3 - sun4u_a3)] | |
767 | ||
768 | call %l0 | |
769 | add %l1, (sun4u_a4 - sun4u_a1), %o0 | |
770 | ||
771 | /* Not reached */ | |
772 | halt_me: | |
773 | ld [%g7 + 0x74], %o0 | |
774 | call %o0 ! Get us out of here... | |
775 | nop ! Apparently Solaris is better. | |
776 | ||
777 | /* Ok, now we continue in the .data/.text sections */ | |
778 | ||
779 | .data | |
780 | .align 4 | |
781 | ||
782 | /* | |
783 | * Fill up the prom vector, note in particular the kind first element, | |
784 | * no joke. I don't need all of them in here as the entire prom vector | |
785 | * gets initialized in c-code so all routines can use it. | |
786 | */ | |
787 | ||
1da177e4 LT |
788 | prom_vector_p: |
789 | .word 0 | |
790 | ||
791 | /* We calculate the following at boot time, window fills/spills and trap entry | |
792 | * code uses these to keep track of the register windows. | |
793 | */ | |
794 | ||
795 | .align 4 | |
796 | .globl nwindows | |
797 | .globl nwindowsm1 | |
798 | nwindows: | |
799 | .word 8 | |
800 | nwindowsm1: | |
801 | .word 7 | |
802 | ||
803 | /* Boot time debugger vector value. We need this later on. */ | |
804 | ||
805 | .align 4 | |
806 | .globl linux_dbvec | |
807 | linux_dbvec: | |
808 | .word 0 | |
809 | .word 0 | |
810 | ||
811 | .align 8 | |
812 | ||
813 | .globl lvl14_save | |
814 | lvl14_save: | |
815 | .word 0 | |
816 | .word 0 | |
817 | .word 0 | |
818 | .word 0 | |
819 | .word t_irq14 | |
820 | ||
821 | .section ".fixup",#alloc,#execinstr | |
822 | .globl __ret_efault | |
823 | __ret_efault: | |
824 | ret | |
825 | restore %g0, -EFAULT, %o0 |