Commit | Line | Data |
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1d05995b SR |
1 | #include <linux/platform_device.h> |
2 | ||
d550bbd4 | 3 | #include <asm/cpu_type.h> |
32231a66 | 4 | |
6baa9b20 SR |
5 | struct irq_bucket { |
6 | struct irq_bucket *next; | |
7 | unsigned int real_irq; | |
8 | unsigned int irq; | |
9 | unsigned int pil; | |
10 | }; | |
11 | ||
4ba22b16 SR |
12 | #define SUN4M_HARD_INT(x) (0x000000001 << (x)) |
13 | #define SUN4M_SOFT_INT(x) (0x000010000 << (x)) | |
14 | ||
6baa9b20 SR |
15 | #define SUN4D_MAX_BOARD 10 |
16 | #define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5) | |
17 | ||
18 | /* Map between the irq identifier used in hw to the | |
19 | * irq_bucket. The map is sufficient large to hold | |
20 | * the sun4d hw identifiers. | |
21 | */ | |
22 | extern struct irq_bucket *irq_map[SUN4D_MAX_IRQ]; | |
23 | ||
24 | ||
0399bb5b SR |
25 | /* sun4m specific type definitions */ |
26 | ||
27 | /* This maps direct to CPU specific interrupt registers */ | |
28 | struct sun4m_irq_percpu { | |
29 | u32 pending; | |
30 | u32 clear; | |
31 | u32 set; | |
32 | }; | |
33 | ||
34 | /* This maps direct to global interrupt registers */ | |
35 | struct sun4m_irq_global { | |
36 | u32 pending; | |
37 | u32 mask; | |
38 | u32 mask_clear; | |
39 | u32 mask_set; | |
40 | u32 interrupt_target; | |
41 | }; | |
42 | ||
43 | extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; | |
44 | extern struct sun4m_irq_global __iomem *sun4m_irq_global; | |
45 | ||
62f08283 TK |
46 | /* The following definitions describe the individual platform features: */ |
47 | #define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */ | |
48 | #define FEAT_L10_CLOCKEVENT (1 << 1) /* L10 timer is used as a clockevent */ | |
49 | #define FEAT_L14_ONESHOT (1 << 2) /* L14 timer clockevent can oneshot */ | |
50 | ||
bbdc2661 | 51 | /* |
472bc4f2 | 52 | * Platform specific configuration |
bbdc2661 SR |
53 | * The individual platforms assign their platform |
54 | * specifics in their init functions. | |
55 | */ | |
472bc4f2 | 56 | struct sparc_config { |
62f08283 | 57 | void (*init_timers)(void); |
1d05995b SR |
58 | unsigned int (*build_device_irq)(struct platform_device *op, |
59 | unsigned int real_irq); | |
62f08283 TK |
60 | |
61 | /* generic clockevent features - see FEAT_* above */ | |
62 | int features; | |
63 | ||
64 | /* clock rate used for clock event timer */ | |
65 | int clock_rate; | |
66 | ||
67 | /* one period for clock source timer */ | |
68 | unsigned int cs_period; | |
69 | ||
70 | /* function to obtain offsett for cs period */ | |
71 | unsigned int (*get_cycles_offset)(void); | |
08c9388f SR |
72 | |
73 | void (*clear_clock_irq)(void); | |
74 | void (*load_profile_irq)(int cpu, unsigned int limit); | |
bbdc2661 | 75 | }; |
472bc4f2 | 76 | extern struct sparc_config sparc_config; |
bbdc2661 | 77 | |
6baa9b20 SR |
78 | unsigned int irq_alloc(unsigned int real_irq, unsigned int pil); |
79 | void irq_link(unsigned int irq); | |
80 | void irq_unlink(unsigned int irq); | |
81 | void handler_irq(unsigned int pil, struct pt_regs *regs); | |
bbdc2661 | 82 | |
4ba22b16 | 83 | unsigned long leon_get_irqmask(unsigned int irq); |
32231a66 | 84 | |
fbb86383 SR |
85 | /* irq_32.c */ |
86 | void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs); | |
87 | ||
2b399177 SR |
88 | /* sun4m_irq.c */ |
89 | void sun4m_nmi(struct pt_regs *regs); | |
90 | ||
5ac75688 SR |
91 | /* sun4d_irq.c */ |
92 | void sun4d_handler_irq(unsigned int pil, struct pt_regs *regs); | |
93 | ||
4ba22b16 | 94 | #ifdef CONFIG_SMP |
55dd23ec DH |
95 | |
96 | /* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */ | |
38f7f8f0 | 97 | #define SUN4D_IPI_IRQ 13 |
55dd23ec | 98 | |
2e74a74f | 99 | void sun4d_ipi_interrupt(void); |
55dd23ec | 100 | |
32231a66 | 101 | #endif |