Commit | Line | Data |
---|---|---|
88278ca2 | 1 | /* |
fd49bf48 SR |
2 | * Interrupt request handling routines. On the |
3 | * Sparc the IRQs are basically 'cast in stone' | |
4 | * and you are supposed to probe the prom's device | |
5 | * node trees to find out who's got which IRQ. | |
1da177e4 LT |
6 | * |
7 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
8 | * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
9 | * Copyright (C) 1995,2002 Pete A. Zaitcev (zaitcev@yahoo.com) | |
10 | * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) | |
11 | * Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org) | |
12 | */ | |
13 | ||
1da177e4 | 14 | #include <linux/kernel_stat.h> |
1da177e4 | 15 | #include <linux/seq_file.h> |
7b64db60 | 16 | #include <linux/export.h> |
1da177e4 | 17 | |
a2a211cb | 18 | #include <asm/cacheflush.h> |
6baa9b20 | 19 | #include <asm/cpudata.h> |
fbb86383 | 20 | #include <asm/setup.h> |
1da177e4 | 21 | #include <asm/pcic.h> |
0fd7ef1f | 22 | #include <asm/leon.h> |
1da177e4 | 23 | |
81265fd9 | 24 | #include "kernel.h" |
32231a66 AV |
25 | #include "irq.h" |
26 | ||
bbdc2661 | 27 | /* platform specific irq setup */ |
472bc4f2 | 28 | struct sparc_config sparc_config; |
bbdc2661 | 29 | |
df9ee292 | 30 | unsigned long arch_local_irq_save(void) |
1da177e4 LT |
31 | { |
32 | unsigned long retval; | |
33 | unsigned long tmp; | |
34 | ||
35 | __asm__ __volatile__( | |
36 | "rd %%psr, %0\n\t" | |
1da177e4 LT |
37 | "or %0, %2, %1\n\t" |
38 | "wr %1, 0, %%psr\n\t" | |
39 | "nop; nop; nop\n" | |
40 | : "=&r" (retval), "=r" (tmp) | |
41 | : "i" (PSR_PIL) | |
42 | : "memory"); | |
43 | ||
44 | return retval; | |
45 | } | |
df9ee292 | 46 | EXPORT_SYMBOL(arch_local_irq_save); |
1da177e4 | 47 | |
df9ee292 | 48 | void arch_local_irq_enable(void) |
1da177e4 LT |
49 | { |
50 | unsigned long tmp; | |
51 | ||
52 | __asm__ __volatile__( | |
53 | "rd %%psr, %0\n\t" | |
1da177e4 LT |
54 | "andn %0, %1, %0\n\t" |
55 | "wr %0, 0, %%psr\n\t" | |
56 | "nop; nop; nop\n" | |
57 | : "=&r" (tmp) | |
58 | : "i" (PSR_PIL) | |
59 | : "memory"); | |
60 | } | |
df9ee292 | 61 | EXPORT_SYMBOL(arch_local_irq_enable); |
1da177e4 | 62 | |
df9ee292 | 63 | void arch_local_irq_restore(unsigned long old_psr) |
1da177e4 LT |
64 | { |
65 | unsigned long tmp; | |
66 | ||
67 | __asm__ __volatile__( | |
68 | "rd %%psr, %0\n\t" | |
69 | "and %2, %1, %2\n\t" | |
1da177e4 LT |
70 | "andn %0, %1, %0\n\t" |
71 | "wr %0, %2, %%psr\n\t" | |
72 | "nop; nop; nop\n" | |
73 | : "=&r" (tmp) | |
74 | : "i" (PSR_PIL), "r" (old_psr) | |
75 | : "memory"); | |
76 | } | |
df9ee292 | 77 | EXPORT_SYMBOL(arch_local_irq_restore); |
1da177e4 LT |
78 | |
79 | /* | |
80 | * Dave Redman (djhr@tadpole.co.uk) | |
81 | * | |
82 | * IRQ numbers.. These are no longer restricted to 15.. | |
83 | * | |
84 | * this is done to enable SBUS cards and onboard IO to be masked | |
85 | * correctly. using the interrupt level isn't good enough. | |
86 | * | |
87 | * For example: | |
88 | * A device interrupting at sbus level6 and the Floppy both come in | |
89 | * at IRQ11, but enabling and disabling them requires writing to | |
90 | * different bits in the SLAVIO/SEC. | |
91 | * | |
92 | * As a result of these changes sun4m machines could now support | |
93 | * directed CPU interrupts using the existing enable/disable irq code | |
94 | * with tweaks. | |
95 | * | |
6baa9b20 SR |
96 | * Sun4d complicates things even further. IRQ numbers are arbitrary |
97 | * 32-bit values in that case. Since this is similar to sparc64, | |
98 | * we adopt a virtual IRQ numbering scheme as is done there. | |
99 | * Virutal interrupt numbers are allocated by build_irq(). So NR_IRQS | |
100 | * just becomes a limit of how many interrupt sources we can handle in | |
101 | * a single system. Even fully loaded SS2000 machines top off at | |
102 | * about 32 interrupt sources or so, therefore a NR_IRQS value of 64 | |
103 | * is more than enough. | |
104 | * | |
105 | * We keep a map of per-PIL enable interrupts. These get wired | |
106 | * up via the irq_chip->startup() method which gets invoked by | |
107 | * the generic IRQ layer during request_irq(). | |
1da177e4 LT |
108 | */ |
109 | ||
1da177e4 | 110 | |
6baa9b20 SR |
111 | /* Table of allocated irqs. Unused entries has irq == 0 */ |
112 | static struct irq_bucket irq_table[NR_IRQS]; | |
113 | /* Protect access to irq_table */ | |
114 | static DEFINE_SPINLOCK(irq_table_lock); | |
1da177e4 | 115 | |
6baa9b20 SR |
116 | /* Map between the irq identifier used in hw to the irq_bucket. */ |
117 | struct irq_bucket *irq_map[SUN4D_MAX_IRQ]; | |
118 | /* Protect access to irq_map */ | |
119 | static DEFINE_SPINLOCK(irq_map_lock); | |
1da177e4 | 120 | |
6baa9b20 SR |
121 | /* Allocate a new irq from the irq_table */ |
122 | unsigned int irq_alloc(unsigned int real_irq, unsigned int pil) | |
1da177e4 | 123 | { |
1da177e4 | 124 | unsigned long flags; |
6baa9b20 SR |
125 | unsigned int i; |
126 | ||
127 | spin_lock_irqsave(&irq_table_lock, flags); | |
128 | for (i = 1; i < NR_IRQS; i++) { | |
129 | if (irq_table[i].real_irq == real_irq && irq_table[i].pil == pil) | |
130 | goto found; | |
131 | } | |
1da177e4 | 132 | |
6baa9b20 SR |
133 | for (i = 1; i < NR_IRQS; i++) { |
134 | if (!irq_table[i].irq) | |
135 | break; | |
136 | } | |
fd49bf48 | 137 | |
1da177e4 | 138 | if (i < NR_IRQS) { |
6baa9b20 SR |
139 | irq_table[i].real_irq = real_irq; |
140 | irq_table[i].irq = i; | |
141 | irq_table[i].pil = pil; | |
142 | } else { | |
143 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
144 | i = 0; | |
1da177e4 | 145 | } |
6baa9b20 SR |
146 | found: |
147 | spin_unlock_irqrestore(&irq_table_lock, flags); | |
148 | ||
149 | return i; | |
1da177e4 LT |
150 | } |
151 | ||
6baa9b20 SR |
152 | /* Based on a single pil handler_irq may need to call several |
153 | * interrupt handlers. Use irq_map as entry to irq_table, | |
154 | * and let each entry in irq_table point to the next entry. | |
155 | */ | |
156 | void irq_link(unsigned int irq) | |
1da177e4 | 157 | { |
6baa9b20 | 158 | struct irq_bucket *p; |
fd49bf48 | 159 | unsigned long flags; |
6baa9b20 | 160 | unsigned int pil; |
fd49bf48 | 161 | |
6baa9b20 | 162 | BUG_ON(irq >= NR_IRQS); |
1da177e4 | 163 | |
6baa9b20 | 164 | spin_lock_irqsave(&irq_map_lock, flags); |
1da177e4 | 165 | |
6baa9b20 SR |
166 | p = &irq_table[irq]; |
167 | pil = p->pil; | |
168 | BUG_ON(pil > SUN4D_MAX_IRQ); | |
169 | p->next = irq_map[pil]; | |
170 | irq_map[pil] = p; | |
1da177e4 | 171 | |
6baa9b20 SR |
172 | spin_unlock_irqrestore(&irq_map_lock, flags); |
173 | } | |
1da177e4 | 174 | |
6baa9b20 SR |
175 | void irq_unlink(unsigned int irq) |
176 | { | |
177 | struct irq_bucket *p, **pnext; | |
178 | unsigned long flags; | |
1da177e4 | 179 | |
6baa9b20 | 180 | BUG_ON(irq >= NR_IRQS); |
1da177e4 | 181 | |
6baa9b20 | 182 | spin_lock_irqsave(&irq_map_lock, flags); |
1da177e4 | 183 | |
6baa9b20 SR |
184 | p = &irq_table[irq]; |
185 | BUG_ON(p->pil > SUN4D_MAX_IRQ); | |
186 | pnext = &irq_map[p->pil]; | |
187 | while (*pnext != p) | |
188 | pnext = &(*pnext)->next; | |
189 | *pnext = p->next; | |
1da177e4 | 190 | |
6baa9b20 | 191 | spin_unlock_irqrestore(&irq_map_lock, flags); |
1da177e4 | 192 | } |
1da177e4 | 193 | |
a54123e2 | 194 | |
6baa9b20 SR |
195 | /* /proc/interrupts printing */ |
196 | int arch_show_interrupts(struct seq_file *p, int prec) | |
1da177e4 | 197 | { |
6baa9b20 | 198 | int j; |
fd49bf48 | 199 | |
d6d04819 DH |
200 | #ifdef CONFIG_SMP |
201 | seq_printf(p, "RES: "); | |
202 | for_each_online_cpu(j) | |
203 | seq_printf(p, "%10u ", cpu_data(j).irq_resched_count); | |
204 | seq_printf(p, " IPI rescheduling interrupts\n"); | |
205 | seq_printf(p, "CAL: "); | |
206 | for_each_online_cpu(j) | |
207 | seq_printf(p, "%10u ", cpu_data(j).irq_call_count); | |
208 | seq_printf(p, " IPI function call interrupts\n"); | |
209 | #endif | |
6baa9b20 SR |
210 | seq_printf(p, "NMI: "); |
211 | for_each_online_cpu(j) | |
212 | seq_printf(p, "%10u ", cpu_data(j).counter); | |
213 | seq_printf(p, " Non-maskable interrupts\n"); | |
214 | return 0; | |
1da177e4 LT |
215 | } |
216 | ||
6baa9b20 | 217 | void handler_irq(unsigned int pil, struct pt_regs *regs) |
1da177e4 | 218 | { |
0d84438d | 219 | struct pt_regs *old_regs; |
6baa9b20 | 220 | struct irq_bucket *p; |
1da177e4 | 221 | |
6baa9b20 | 222 | BUG_ON(pil > 15); |
0d84438d | 223 | old_regs = set_irq_regs(regs); |
1da177e4 | 224 | irq_enter(); |
6baa9b20 SR |
225 | |
226 | p = irq_map[pil]; | |
227 | while (p) { | |
228 | struct irq_bucket *next = p->next; | |
229 | ||
230 | generic_handle_irq(p->irq); | |
231 | p = next; | |
232 | } | |
1da177e4 | 233 | irq_exit(); |
0d84438d | 234 | set_irq_regs(old_regs); |
1da177e4 LT |
235 | } |
236 | ||
0a808a31 | 237 | #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE) |
6baa9b20 | 238 | static unsigned int floppy_irq; |
1da177e4 | 239 | |
6baa9b20 | 240 | int sparc_floppy_request_irq(unsigned int irq, irq_handler_t irq_handler) |
1da177e4 | 241 | { |
1da177e4 | 242 | unsigned int cpu_irq; |
6baa9b20 SR |
243 | int err; |
244 | ||
1da177e4 | 245 | |
6baa9b20 SR |
246 | err = request_irq(irq, irq_handler, 0, "floppy", NULL); |
247 | if (err) | |
248 | return -1; | |
1da177e4 | 249 | |
6baa9b20 SR |
250 | /* Save for later use in floppy interrupt handler */ |
251 | floppy_irq = irq; | |
1da177e4 | 252 | |
6baa9b20 | 253 | cpu_irq = (irq & (NR_IRQS - 1)); |
1da177e4 LT |
254 | |
255 | /* Dork with trap table if we get this far. */ | |
256 | #define INSTANTIATE(table) \ | |
257 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \ | |
258 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \ | |
6baa9b20 | 259 | SPARC_BRANCH((unsigned long) floppy_hardint, \ |
1da177e4 LT |
260 | (unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\ |
261 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \ | |
262 | table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP; | |
263 | ||
264 | INSTANTIATE(sparc_ttable) | |
b08b5c9c SR |
265 | |
266 | #if defined CONFIG_SMP | |
267 | if (sparc_cpu_model != sparc_leon) { | |
268 | struct tt_entry *trap_table; | |
269 | ||
270 | trap_table = &trapbase_cpu1; | |
271 | INSTANTIATE(trap_table) | |
272 | trap_table = &trapbase_cpu2; | |
273 | INSTANTIATE(trap_table) | |
274 | trap_table = &trapbase_cpu3; | |
275 | INSTANTIATE(trap_table) | |
276 | } | |
1da177e4 LT |
277 | #endif |
278 | #undef INSTANTIATE | |
279 | /* | |
280 | * XXX Correct thing whould be to flush only I- and D-cache lines | |
281 | * which contain the handler in question. But as of time of the | |
282 | * writing we have no CPU-neutral interface to fine-grained flushes. | |
283 | */ | |
284 | flush_cache_all(); | |
6baa9b20 | 285 | return 0; |
1da177e4 | 286 | } |
6baa9b20 | 287 | EXPORT_SYMBOL(sparc_floppy_request_irq); |
1da177e4 | 288 | |
fd49bf48 SR |
289 | /* |
290 | * These variables are used to access state from the assembler | |
0a808a31 DM |
291 | * interrupt handler, floppy_hardint, so we cannot put these in |
292 | * the floppy driver image because that would not work in the | |
293 | * modular case. | |
294 | */ | |
295 | volatile unsigned char *fdc_status; | |
296 | EXPORT_SYMBOL(fdc_status); | |
297 | ||
298 | char *pdma_vaddr; | |
299 | EXPORT_SYMBOL(pdma_vaddr); | |
300 | ||
301 | unsigned long pdma_size; | |
302 | EXPORT_SYMBOL(pdma_size); | |
303 | ||
304 | volatile int doing_pdma; | |
305 | EXPORT_SYMBOL(doing_pdma); | |
306 | ||
307 | char *pdma_base; | |
308 | EXPORT_SYMBOL(pdma_base); | |
309 | ||
310 | unsigned long pdma_areasize; | |
311 | EXPORT_SYMBOL(pdma_areasize); | |
312 | ||
6baa9b20 SR |
313 | /* Use the generic irq support to call floppy_interrupt |
314 | * which was setup using request_irq() in sparc_floppy_request_irq(). | |
315 | * We only have one floppy interrupt so we do not need to check | |
316 | * for additional handlers being wired up by irq_link() | |
317 | */ | |
0a808a31 DM |
318 | void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs) |
319 | { | |
320 | struct pt_regs *old_regs; | |
0a808a31 DM |
321 | |
322 | old_regs = set_irq_regs(regs); | |
0a808a31 | 323 | irq_enter(); |
6baa9b20 | 324 | generic_handle_irq(floppy_irq); |
0a808a31 | 325 | irq_exit(); |
0a808a31 | 326 | set_irq_regs(old_regs); |
0a808a31 | 327 | } |
0a808a31 DM |
328 | #endif |
329 | ||
1da177e4 LT |
330 | /* djhr |
331 | * This could probably be made indirect too and assigned in the CPU | |
332 | * bits of the code. That would be much nicer I think and would also | |
333 | * fit in with the idea of being able to tune your kernel for your machine | |
334 | * by removing unrequired machine and device support. | |
335 | * | |
336 | */ | |
337 | ||
338 | void __init init_IRQ(void) | |
339 | { | |
fd49bf48 | 340 | switch (sparc_cpu_model) { |
1da177e4 | 341 | case sun4m: |
1da177e4 | 342 | pcic_probe(); |
06010fb5 | 343 | if (pcic_present()) |
1da177e4 | 344 | sun4m_pci_init_IRQ(); |
06010fb5 SR |
345 | else |
346 | sun4m_init_IRQ(); | |
1da177e4 | 347 | break; |
fd49bf48 | 348 | |
1da177e4 LT |
349 | case sun4d: |
350 | sun4d_init_IRQ(); | |
351 | break; | |
352 | ||
0fd7ef1f KE |
353 | case sparc_leon: |
354 | leon_init_IRQ(); | |
355 | break; | |
356 | ||
1da177e4 | 357 | default: |
d1a78c32 | 358 | prom_printf("Cannot initialize IRQs on this Sun machine..."); |
1da177e4 LT |
359 | break; |
360 | } | |
1da177e4 LT |
361 | } |
362 |