Commit | Line | Data |
---|---|---|
4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
227c3311 | 3 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
9843099f | 10 | #include <linux/linkage.h> |
1da177e4 LT |
11 | #include <linux/ptrace.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/seq_file.h> | |
b5a37e96 | 23 | #include <linux/bootmem.h> |
e18e2a00 | 24 | #include <linux/irq.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/irq.h> | |
2e457ef6 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/iommu.h> |
33 | #include <asm/upa.h> | |
34 | #include <asm/oplib.h> | |
25c7581b | 35 | #include <asm/prom.h> |
1da177e4 LT |
36 | #include <asm/timer.h> |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
4a907dec | 44 | #include <asm/hypervisor.h> |
42d5f99b | 45 | #include <asm/cacheflush.h> |
1da177e4 | 46 | |
d91aa123 | 47 | #include "entry.h" |
e18e2a00 DM |
48 | |
49 | #define NUM_IVECS (IMAP_INR + 1) | |
d91aa123 | 50 | |
10397e40 | 51 | struct ino_bucket *ivector_table; |
eb2d8d60 | 52 | unsigned long ivector_table_pa; |
1da177e4 | 53 | |
42d5f99b DM |
54 | /* On several sun4u processors, it is illegal to mix bypass and |
55 | * non-bypass accesses. Therefore we access all INO buckets | |
56 | * using bypass accesses only. | |
57 | */ | |
58 | static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) | |
59 | { | |
60 | unsigned long ret; | |
61 | ||
62 | __asm__ __volatile__("ldxa [%1] %2, %0" | |
63 | : "=&r" (ret) | |
64 | : "r" (bucket_pa + | |
65 | offsetof(struct ino_bucket, | |
66 | __irq_chain_pa)), | |
67 | "i" (ASI_PHYS_USE_EC)); | |
68 | ||
69 | return ret; | |
70 | } | |
71 | ||
72 | static void bucket_clear_chain_pa(unsigned long bucket_pa) | |
73 | { | |
74 | __asm__ __volatile__("stxa %%g0, [%0] %1" | |
75 | : /* no outputs */ | |
76 | : "r" (bucket_pa + | |
77 | offsetof(struct ino_bucket, | |
78 | __irq_chain_pa)), | |
79 | "i" (ASI_PHYS_USE_EC)); | |
80 | } | |
81 | ||
82 | static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) | |
83 | { | |
84 | unsigned int ret; | |
85 | ||
86 | __asm__ __volatile__("lduwa [%1] %2, %0" | |
87 | : "=&r" (ret) | |
88 | : "r" (bucket_pa + | |
89 | offsetof(struct ino_bucket, | |
90 | __virt_irq)), | |
91 | "i" (ASI_PHYS_USE_EC)); | |
92 | ||
93 | return ret; | |
94 | } | |
95 | ||
96 | static void bucket_set_virt_irq(unsigned long bucket_pa, | |
97 | unsigned int virt_irq) | |
98 | { | |
99 | __asm__ __volatile__("stwa %0, [%1] %2" | |
100 | : /* no outputs */ | |
101 | : "r" (virt_irq), | |
102 | "r" (bucket_pa + | |
103 | offsetof(struct ino_bucket, | |
104 | __virt_irq)), | |
105 | "i" (ASI_PHYS_USE_EC)); | |
106 | } | |
107 | ||
eb2d8d60 | 108 | #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) |
1da177e4 | 109 | |
93b3238e | 110 | static struct { |
93b3238e DM |
111 | unsigned int dev_handle; |
112 | unsigned int dev_ino; | |
256c1df3 | 113 | unsigned int in_use; |
45b3f4cc | 114 | } virt_irq_table[NR_IRQS]; |
759f89e0 | 115 | static DEFINE_SPINLOCK(virt_irq_alloc_lock); |
8047e247 | 116 | |
256c1df3 | 117 | unsigned char virt_irq_alloc(unsigned int dev_handle, |
bb74b734 | 118 | unsigned int dev_ino) |
8047e247 | 119 | { |
759f89e0 | 120 | unsigned long flags; |
8047e247 DM |
121 | unsigned char ent; |
122 | ||
123 | BUILD_BUG_ON(NR_IRQS >= 256); | |
124 | ||
759f89e0 DM |
125 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
126 | ||
35a17eb6 | 127 | for (ent = 1; ent < NR_IRQS; ent++) { |
45b3f4cc | 128 | if (!virt_irq_table[ent].in_use) |
35a17eb6 DM |
129 | break; |
130 | } | |
8047e247 DM |
131 | if (ent >= NR_IRQS) { |
132 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
759f89e0 DM |
133 | ent = 0; |
134 | } else { | |
45b3f4cc DM |
135 | virt_irq_table[ent].dev_handle = dev_handle; |
136 | virt_irq_table[ent].dev_ino = dev_ino; | |
137 | virt_irq_table[ent].in_use = 1; | |
8047e247 DM |
138 | } |
139 | ||
759f89e0 | 140 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 DM |
141 | |
142 | return ent; | |
143 | } | |
144 | ||
5746c99d | 145 | #ifdef CONFIG_PCI_MSI |
759f89e0 | 146 | void virt_irq_free(unsigned int virt_irq) |
8047e247 | 147 | { |
759f89e0 | 148 | unsigned long flags; |
8047e247 | 149 | |
35a17eb6 DM |
150 | if (virt_irq >= NR_IRQS) |
151 | return; | |
152 | ||
759f89e0 DM |
153 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
154 | ||
45b3f4cc | 155 | virt_irq_table[virt_irq].in_use = 0; |
35a17eb6 | 156 | |
759f89e0 | 157 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 | 158 | } |
5746c99d | 159 | #endif |
8047e247 | 160 | |
1da177e4 | 161 | /* |
e18e2a00 | 162 | * /proc/interrupts printing: |
1da177e4 | 163 | */ |
1da177e4 LT |
164 | |
165 | int show_interrupts(struct seq_file *p, void *v) | |
166 | { | |
e18e2a00 DM |
167 | int i = *(loff_t *) v, j; |
168 | struct irqaction * action; | |
1da177e4 | 169 | unsigned long flags; |
1da177e4 | 170 | |
e18e2a00 DM |
171 | if (i == 0) { |
172 | seq_printf(p, " "); | |
173 | for_each_online_cpu(j) | |
174 | seq_printf(p, "CPU%d ",j); | |
175 | seq_putc(p, '\n'); | |
176 | } | |
177 | ||
178 | if (i < NR_IRQS) { | |
179 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
180 | action = irq_desc[i].action; | |
181 | if (!action) | |
182 | goto skip; | |
183 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
184 | #ifndef CONFIG_SMP |
185 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
186 | #else | |
e18e2a00 | 187 | for_each_online_cpu(j) |
e81838d2 | 188 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); |
1da177e4 | 189 | #endif |
d1bef4ed | 190 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
191 | seq_printf(p, " %s", action->name); |
192 | ||
193 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 194 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 195 | |
1da177e4 | 196 | seq_putc(p, '\n'); |
e18e2a00 DM |
197 | skip: |
198 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
e5553a6d DM |
199 | } else if (i == NR_IRQS) { |
200 | seq_printf(p, "NMI: "); | |
201 | for_each_online_cpu(j) | |
202 | seq_printf(p, "%10u ", cpu_data(j).__nmi_count); | |
203 | seq_printf(p, " Non-maskable interrupts\n"); | |
1da177e4 | 204 | } |
1da177e4 LT |
205 | return 0; |
206 | } | |
207 | ||
ebd8c56c DM |
208 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
209 | { | |
210 | unsigned int tid; | |
211 | ||
212 | if (this_is_starfire) { | |
213 | tid = starfire_translate(imap, cpuid); | |
214 | tid <<= IMAP_TID_SHIFT; | |
215 | tid &= IMAP_TID_UPA; | |
216 | } else { | |
217 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
218 | unsigned long ver; | |
219 | ||
220 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
221 | if ((ver >> 32UL) == __JALAPENO_ID || | |
222 | (ver >> 32UL) == __SERRANO_ID) { | |
223 | tid = cpuid << IMAP_TID_SHIFT; | |
224 | tid &= IMAP_TID_JBUS; | |
225 | } else { | |
226 | unsigned int a = cpuid & 0x1f; | |
227 | unsigned int n = (cpuid >> 5) & 0x1f; | |
228 | ||
229 | tid = ((a << IMAP_AID_SHIFT) | | |
230 | (n << IMAP_NID_SHIFT)); | |
231 | tid &= (IMAP_AID_SAFARI | | |
232 | IMAP_NID_SAFARI);; | |
233 | } | |
234 | } else { | |
235 | tid = cpuid << IMAP_TID_SHIFT; | |
236 | tid &= IMAP_TID_UPA; | |
237 | } | |
238 | } | |
239 | ||
240 | return tid; | |
241 | } | |
242 | ||
e18e2a00 DM |
243 | struct irq_handler_data { |
244 | unsigned long iclr; | |
245 | unsigned long imap; | |
8047e247 | 246 | |
e18e2a00 | 247 | void (*pre_handler)(unsigned int, void *, void *); |
8d57d3ad DM |
248 | void *arg1; |
249 | void *arg2; | |
e18e2a00 | 250 | }; |
1da177e4 | 251 | |
e18e2a00 DM |
252 | #ifdef CONFIG_SMP |
253 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 254 | { |
e65e49d0 | 255 | cpumask_t mask; |
e18e2a00 | 256 | int cpuid; |
088dd1f8 | 257 | |
e65e49d0 | 258 | cpumask_copy(&mask, irq_desc[virt_irq].affinity); |
e18e2a00 DM |
259 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
260 | static int irq_rover; | |
261 | static DEFINE_SPINLOCK(irq_rover_lock); | |
262 | unsigned long flags; | |
1da177e4 | 263 | |
e18e2a00 DM |
264 | /* Round-robin distribution... */ |
265 | do_round_robin: | |
266 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 267 | |
e18e2a00 | 268 | while (!cpu_online(irq_rover)) { |
e305cb8f | 269 | if (++irq_rover >= nr_cpu_ids) |
e18e2a00 DM |
270 | irq_rover = 0; |
271 | } | |
272 | cpuid = irq_rover; | |
273 | do { | |
e305cb8f | 274 | if (++irq_rover >= nr_cpu_ids) |
e18e2a00 DM |
275 | irq_rover = 0; |
276 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 277 | |
e18e2a00 DM |
278 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
279 | } else { | |
280 | cpumask_t tmp; | |
088dd1f8 | 281 | |
e18e2a00 | 282 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 283 | |
e18e2a00 DM |
284 | if (cpus_empty(tmp)) |
285 | goto do_round_robin; | |
088dd1f8 | 286 | |
e18e2a00 | 287 | cpuid = first_cpu(tmp); |
1da177e4 | 288 | } |
088dd1f8 | 289 | |
e18e2a00 DM |
290 | return cpuid; |
291 | } | |
292 | #else | |
293 | static int irq_choose_cpu(unsigned int virt_irq) | |
294 | { | |
295 | return real_hard_smp_processor_id(); | |
1da177e4 | 296 | } |
e18e2a00 | 297 | #endif |
1da177e4 | 298 | |
e18e2a00 | 299 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 300 | { |
68c92186 | 301 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 302 | |
e18e2a00 | 303 | if (likely(data)) { |
861fe906 | 304 | unsigned long cpuid, imap, val; |
e18e2a00 | 305 | unsigned int tid; |
e3999574 | 306 | |
e18e2a00 DM |
307 | cpuid = irq_choose_cpu(virt_irq); |
308 | imap = data->imap; | |
e3999574 | 309 | |
e18e2a00 | 310 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 311 | |
861fe906 DM |
312 | val = upa_readq(imap); |
313 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
314 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
315 | val |= tid | IMAP_VALID; | |
316 | upa_writeq(val, imap); | |
227c3311 | 317 | upa_writeq(ICLR_IDLE, data->iclr); |
e3999574 | 318 | } |
e3999574 DM |
319 | } |
320 | ||
d5dedd45 | 321 | static int sun4u_set_affinity(unsigned int virt_irq, |
0de26520 | 322 | const struct cpumask *mask) |
b53bcb67 DM |
323 | { |
324 | sun4u_irq_enable(virt_irq); | |
d5dedd45 YL |
325 | |
326 | return 0; | |
b53bcb67 DM |
327 | } |
328 | ||
d0cac39e DM |
329 | /* Don't do anything. The desc->status check for IRQ_DISABLED in |
330 | * handler_irq() will skip the handler call and that will leave the | |
331 | * interrupt in the sent state. The next ->enable() call will hit the | |
332 | * ICLR register to reset the state machine. | |
333 | * | |
334 | * This scheme is necessary, instead of clearing the Valid bit in the | |
335 | * IMAP register, to handle the case of IMAP registers being shared by | |
336 | * multiple INOs (and thus ICLR registers). Since we use a different | |
337 | * virtual IRQ for each shared IMAP instance, the generic code thinks | |
338 | * there is only one user so it prematurely calls ->disable() on | |
339 | * free_irq(). | |
340 | * | |
341 | * We have to provide an explicit ->disable() method instead of using | |
342 | * NULL to get the default. The reason is that if the generic code | |
343 | * sees that, it also hooks up a default ->shutdown method which | |
344 | * invokes ->mask() which we do not want. See irq_chip_set_defaults(). | |
345 | */ | |
e18e2a00 | 346 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 347 | { |
088dd1f8 DM |
348 | } |
349 | ||
8d57d3ad | 350 | static void sun4u_irq_eoi(unsigned int virt_irq) |
088dd1f8 | 351 | { |
68c92186 | 352 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
5a606b72 DM |
353 | struct irq_desc *desc = irq_desc + virt_irq; |
354 | ||
355 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
356 | return; | |
088dd1f8 | 357 | |
e18e2a00 | 358 | if (likely(data)) |
861fe906 | 359 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
360 | } |
361 | ||
e18e2a00 | 362 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 363 | { |
45b3f4cc | 364 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 DM |
365 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
366 | int err; | |
367 | ||
368 | err = sun4v_intr_settarget(ino, cpuid); | |
369 | if (err != HV_EOK) | |
370 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
371 | "err(%d)\n", ino, cpuid, err); | |
372 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); | |
373 | if (err != HV_EOK) | |
374 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
375 | "err(%d)\n", ino, err); | |
376 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
377 | if (err != HV_EOK) | |
378 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", | |
379 | ino, err); | |
088dd1f8 DM |
380 | } |
381 | ||
d5dedd45 | 382 | static int sun4v_set_affinity(unsigned int virt_irq, |
0de26520 | 383 | const struct cpumask *mask) |
b53bcb67 | 384 | { |
45b3f4cc | 385 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 DM |
386 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
387 | int err; | |
388 | ||
389 | err = sun4v_intr_settarget(ino, cpuid); | |
390 | if (err != HV_EOK) | |
391 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
392 | "err(%d)\n", ino, cpuid, err); | |
d5dedd45 YL |
393 | |
394 | return 0; | |
b53bcb67 DM |
395 | } |
396 | ||
e18e2a00 | 397 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 398 | { |
45b3f4cc | 399 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 | 400 | int err; |
1da177e4 | 401 | |
77182300 DM |
402 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
403 | if (err != HV_EOK) | |
404 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " | |
405 | "err(%d)\n", ino, err); | |
e18e2a00 | 406 | } |
1da177e4 | 407 | |
8d57d3ad | 408 | static void sun4v_irq_eoi(unsigned int virt_irq) |
e18e2a00 | 409 | { |
45b3f4cc | 410 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
5a606b72 | 411 | struct irq_desc *desc = irq_desc + virt_irq; |
77182300 | 412 | int err; |
5a606b72 DM |
413 | |
414 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
415 | return; | |
1da177e4 | 416 | |
77182300 DM |
417 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
418 | if (err != HV_EOK) | |
419 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
420 | "err(%d)\n", ino, err); | |
1da177e4 LT |
421 | } |
422 | ||
4a907dec DM |
423 | static void sun4v_virq_enable(unsigned int virt_irq) |
424 | { | |
77182300 DM |
425 | unsigned long cpuid, dev_handle, dev_ino; |
426 | int err; | |
427 | ||
428 | cpuid = irq_choose_cpu(virt_irq); | |
429 | ||
45b3f4cc DM |
430 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
431 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
77182300 DM |
432 | |
433 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
434 | if (err != HV_EOK) | |
435 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
436 | "err(%d)\n", | |
437 | dev_handle, dev_ino, cpuid, err); | |
438 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
439 | HV_INTR_STATE_IDLE); | |
440 | if (err != HV_EOK) | |
441 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
442 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
443 | dev_handle, dev_ino, err); | |
444 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
445 | HV_INTR_ENABLED); | |
446 | if (err != HV_EOK) | |
447 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
448 | "HV_INTR_ENABLED): err(%d)\n", | |
449 | dev_handle, dev_ino, err); | |
4a907dec DM |
450 | } |
451 | ||
d5dedd45 | 452 | static int sun4v_virt_set_affinity(unsigned int virt_irq, |
0de26520 | 453 | const struct cpumask *mask) |
b53bcb67 | 454 | { |
77182300 DM |
455 | unsigned long cpuid, dev_handle, dev_ino; |
456 | int err; | |
b53bcb67 | 457 | |
77182300 | 458 | cpuid = irq_choose_cpu(virt_irq); |
b53bcb67 | 459 | |
45b3f4cc DM |
460 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
461 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
b53bcb67 | 462 | |
77182300 DM |
463 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
464 | if (err != HV_EOK) | |
465 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
466 | "err(%d)\n", | |
467 | dev_handle, dev_ino, cpuid, err); | |
d5dedd45 YL |
468 | |
469 | return 0; | |
b53bcb67 DM |
470 | } |
471 | ||
4a907dec DM |
472 | static void sun4v_virq_disable(unsigned int virt_irq) |
473 | { | |
77182300 DM |
474 | unsigned long dev_handle, dev_ino; |
475 | int err; | |
476 | ||
45b3f4cc DM |
477 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
478 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
77182300 DM |
479 | |
480 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
481 | HV_INTR_DISABLED); | |
482 | if (err != HV_EOK) | |
483 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
484 | "HV_INTR_DISABLED): err(%d)\n", | |
485 | dev_handle, dev_ino, err); | |
4a907dec DM |
486 | } |
487 | ||
8d57d3ad | 488 | static void sun4v_virq_eoi(unsigned int virt_irq) |
4a907dec | 489 | { |
5a606b72 | 490 | struct irq_desc *desc = irq_desc + virt_irq; |
77182300 DM |
491 | unsigned long dev_handle, dev_ino; |
492 | int err; | |
5a606b72 DM |
493 | |
494 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
495 | return; | |
4a907dec | 496 | |
45b3f4cc DM |
497 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
498 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
4a907dec | 499 | |
77182300 DM |
500 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
501 | HV_INTR_STATE_IDLE); | |
502 | if (err != HV_EOK) | |
503 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
504 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
505 | dev_handle, dev_ino, err); | |
4a907dec DM |
506 | } |
507 | ||
729e7d7e | 508 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
509 | .typename = "sun4u", |
510 | .enable = sun4u_irq_enable, | |
511 | .disable = sun4u_irq_disable, | |
8d57d3ad | 512 | .eoi = sun4u_irq_eoi, |
b53bcb67 | 513 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 514 | }; |
088dd1f8 | 515 | |
729e7d7e | 516 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
517 | .typename = "sun4v", |
518 | .enable = sun4v_irq_enable, | |
519 | .disable = sun4v_irq_disable, | |
8d57d3ad | 520 | .eoi = sun4v_irq_eoi, |
b53bcb67 | 521 | .set_affinity = sun4v_set_affinity, |
e18e2a00 | 522 | }; |
1da177e4 | 523 | |
4a907dec DM |
524 | static struct irq_chip sun4v_virq = { |
525 | .typename = "vsun4v", | |
526 | .enable = sun4v_virq_enable, | |
527 | .disable = sun4v_virq_disable, | |
8d57d3ad | 528 | .eoi = sun4v_virq_eoi, |
b53bcb67 | 529 | .set_affinity = sun4v_virt_set_affinity, |
4a907dec DM |
530 | }; |
531 | ||
edde08f2 | 532 | static void pre_flow_handler(unsigned int virt_irq, |
8d57d3ad DM |
533 | struct irq_desc *desc) |
534 | { | |
535 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); | |
536 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; | |
537 | ||
538 | data->pre_handler(ino, data->arg1, data->arg2); | |
539 | ||
540 | handle_fasteoi_irq(virt_irq, desc); | |
541 | } | |
542 | ||
e18e2a00 DM |
543 | void irq_install_pre_handler(int virt_irq, |
544 | void (*func)(unsigned int, void *, void *), | |
545 | void *arg1, void *arg2) | |
546 | { | |
68c92186 | 547 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
8d57d3ad | 548 | struct irq_desc *desc = irq_desc + virt_irq; |
088dd1f8 | 549 | |
e18e2a00 | 550 | data->pre_handler = func; |
8d57d3ad DM |
551 | data->arg1 = arg1; |
552 | data->arg2 = arg2; | |
24ac26d4 | 553 | |
8d57d3ad | 554 | desc->handle_irq = pre_flow_handler; |
e18e2a00 | 555 | } |
1da177e4 | 556 | |
e18e2a00 DM |
557 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
558 | { | |
559 | struct ino_bucket *bucket; | |
560 | struct irq_handler_data *data; | |
42d5f99b | 561 | unsigned int virt_irq; |
e18e2a00 | 562 | int ino; |
1da177e4 | 563 | |
e18e2a00 | 564 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 565 | |
861fe906 | 566 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 | 567 | bucket = &ivector_table[ino]; |
42d5f99b DM |
568 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
569 | if (!virt_irq) { | |
256c1df3 | 570 | virt_irq = virt_irq_alloc(0, ino); |
42d5f99b | 571 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
572 | set_irq_chip_and_handler_name(virt_irq, |
573 | &sun4u_irq, | |
574 | handle_fasteoi_irq, | |
575 | "IVEC"); | |
fd0504c3 | 576 | } |
1da177e4 | 577 | |
42d5f99b | 578 | data = get_irq_chip_data(virt_irq); |
68c92186 | 579 | if (unlikely(data)) |
e18e2a00 | 580 | goto out; |
fd0504c3 | 581 | |
e18e2a00 DM |
582 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
583 | if (unlikely(!data)) { | |
584 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
585 | prom_halt(); | |
1da177e4 | 586 | } |
42d5f99b | 587 | set_irq_chip_data(virt_irq, data); |
1da177e4 | 588 | |
e18e2a00 DM |
589 | data->imap = imap; |
590 | data->iclr = iclr; | |
1da177e4 | 591 | |
e18e2a00 | 592 | out: |
42d5f99b | 593 | return virt_irq; |
e18e2a00 | 594 | } |
1da177e4 | 595 | |
4a907dec DM |
596 | static unsigned int sun4v_build_common(unsigned long sysino, |
597 | struct irq_chip *chip) | |
1da177e4 | 598 | { |
8047e247 | 599 | struct ino_bucket *bucket; |
e18e2a00 | 600 | struct irq_handler_data *data; |
42d5f99b | 601 | unsigned int virt_irq; |
8047e247 | 602 | |
e18e2a00 | 603 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 604 | |
e18e2a00 | 605 | bucket = &ivector_table[sysino]; |
42d5f99b DM |
606 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
607 | if (!virt_irq) { | |
256c1df3 | 608 | virt_irq = virt_irq_alloc(0, sysino); |
42d5f99b | 609 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
610 | set_irq_chip_and_handler_name(virt_irq, chip, |
611 | handle_fasteoi_irq, | |
612 | "IVEC"); | |
1da177e4 | 613 | } |
1da177e4 | 614 | |
42d5f99b | 615 | data = get_irq_chip_data(virt_irq); |
68c92186 | 616 | if (unlikely(data)) |
1da177e4 | 617 | goto out; |
1da177e4 | 618 | |
e18e2a00 DM |
619 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
620 | if (unlikely(!data)) { | |
621 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
622 | prom_halt(); | |
623 | } | |
42d5f99b | 624 | set_irq_chip_data(virt_irq, data); |
1da177e4 | 625 | |
e18e2a00 DM |
626 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
627 | * is done by hypervisor calls on sun4v platforms, not by direct | |
628 | * register accesses. | |
629 | */ | |
630 | data->imap = ~0UL; | |
631 | data->iclr = ~0UL; | |
1da177e4 | 632 | |
e18e2a00 | 633 | out: |
42d5f99b | 634 | return virt_irq; |
e18e2a00 | 635 | } |
1da177e4 | 636 | |
4a907dec DM |
637 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
638 | { | |
639 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
640 | ||
641 | return sun4v_build_common(sysino, &sun4v_irq); | |
642 | } | |
643 | ||
644 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
645 | { | |
b80e6998 | 646 | struct irq_handler_data *data; |
b80e6998 | 647 | unsigned long hv_err, cookie; |
b7c2a757 DM |
648 | struct ino_bucket *bucket; |
649 | struct irq_desc *desc; | |
42d5f99b | 650 | unsigned int virt_irq; |
b80e6998 DM |
651 | |
652 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); | |
653 | if (unlikely(!bucket)) | |
654 | return 0; | |
42d5f99b DM |
655 | __flush_dcache_range((unsigned long) bucket, |
656 | ((unsigned long) bucket + | |
657 | sizeof(struct ino_bucket))); | |
b80e6998 | 658 | |
256c1df3 | 659 | virt_irq = virt_irq_alloc(devhandle, devino); |
42d5f99b | 660 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
661 | |
662 | set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, | |
663 | handle_fasteoi_irq, | |
664 | "IVEC"); | |
4a907dec | 665 | |
b80e6998 DM |
666 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
667 | if (unlikely(!data)) | |
668 | return 0; | |
4a907dec | 669 | |
b7c2a757 DM |
670 | /* In order to make the LDC channel startup sequence easier, |
671 | * especially wrt. locking, we do not let request_irq() enable | |
672 | * the interrupt. | |
673 | */ | |
674 | desc = irq_desc + virt_irq; | |
675 | desc->status |= IRQ_NOAUTOEN; | |
676 | ||
42d5f99b | 677 | set_irq_chip_data(virt_irq, data); |
4a907dec | 678 | |
b80e6998 DM |
679 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
680 | * is done by hypervisor calls on sun4v platforms, not by direct | |
681 | * register accesses. | |
682 | */ | |
683 | data->imap = ~0UL; | |
684 | data->iclr = ~0UL; | |
685 | ||
686 | cookie = ~__pa(bucket); | |
687 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); | |
4a907dec DM |
688 | if (hv_err) { |
689 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
690 | "err=%lu\n", devhandle, devino, hv_err); | |
691 | prom_halt(); | |
692 | } | |
693 | ||
42d5f99b | 694 | return virt_irq; |
4a907dec DM |
695 | } |
696 | ||
e18e2a00 DM |
697 | void ack_bad_irq(unsigned int virt_irq) |
698 | { | |
45b3f4cc | 699 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
ab66a50e | 700 | |
77182300 DM |
701 | if (!ino) |
702 | ino = 0xdeadbeef; | |
6a76267f | 703 | |
e18e2a00 DM |
704 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
705 | ino, virt_irq); | |
1da177e4 LT |
706 | } |
707 | ||
4f70f7a9 DM |
708 | void *hardirq_stack[NR_CPUS]; |
709 | void *softirq_stack[NR_CPUS]; | |
710 | ||
711 | static __attribute__((always_inline)) void *set_hardirq_stack(void) | |
712 | { | |
713 | void *orig_sp, *sp = hardirq_stack[smp_processor_id()]; | |
714 | ||
715 | __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp)); | |
716 | if (orig_sp < sp || | |
717 | orig_sp > (sp + THREAD_SIZE)) { | |
718 | sp += THREAD_SIZE - 192 - STACK_BIAS; | |
719 | __asm__ __volatile__("mov %0, %%sp" : : "r" (sp)); | |
720 | } | |
721 | ||
722 | return orig_sp; | |
723 | } | |
724 | static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp) | |
725 | { | |
726 | __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp)); | |
727 | } | |
728 | ||
1da177e4 LT |
729 | void handler_irq(int irq, struct pt_regs *regs) |
730 | { | |
eb2d8d60 | 731 | unsigned long pstate, bucket_pa; |
6d24c8dc | 732 | struct pt_regs *old_regs; |
4f70f7a9 | 733 | void *orig_sp; |
1da177e4 | 734 | |
1da177e4 | 735 | clear_softint(1 << irq); |
1da177e4 | 736 | |
6d24c8dc | 737 | old_regs = set_irq_regs(regs); |
1da177e4 | 738 | irq_enter(); |
1da177e4 | 739 | |
a650d383 DM |
740 | /* Grab an atomic snapshot of the pending IVECs. */ |
741 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
742 | "wrpr %0, %3, %%pstate\n\t" | |
743 | "ldx [%2], %1\n\t" | |
744 | "stx %%g0, [%2]\n\t" | |
745 | "wrpr %0, 0x0, %%pstate\n\t" | |
eb2d8d60 DM |
746 | : "=&r" (pstate), "=&r" (bucket_pa) |
747 | : "r" (irq_work_pa(smp_processor_id())), | |
a650d383 DM |
748 | "i" (PSTATE_IE) |
749 | : "memory"); | |
750 | ||
4f70f7a9 DM |
751 | orig_sp = set_hardirq_stack(); |
752 | ||
eb2d8d60 | 753 | while (bucket_pa) { |
8d57d3ad | 754 | struct irq_desc *desc; |
eb2d8d60 DM |
755 | unsigned long next_pa; |
756 | unsigned int virt_irq; | |
1da177e4 | 757 | |
42d5f99b DM |
758 | next_pa = bucket_get_chain_pa(bucket_pa); |
759 | virt_irq = bucket_get_virt_irq(bucket_pa); | |
760 | bucket_clear_chain_pa(bucket_pa); | |
fd0504c3 | 761 | |
8d57d3ad DM |
762 | desc = irq_desc + virt_irq; |
763 | ||
d0cac39e DM |
764 | if (!(desc->status & IRQ_DISABLED)) |
765 | desc->handle_irq(virt_irq, desc); | |
eb2d8d60 DM |
766 | |
767 | bucket_pa = next_pa; | |
1da177e4 | 768 | } |
e18e2a00 | 769 | |
4f70f7a9 DM |
770 | restore_hardirq_stack(orig_sp); |
771 | ||
1da177e4 | 772 | irq_exit(); |
6d24c8dc | 773 | set_irq_regs(old_regs); |
1da177e4 LT |
774 | } |
775 | ||
4f70f7a9 DM |
776 | void do_softirq(void) |
777 | { | |
778 | unsigned long flags; | |
779 | ||
780 | if (in_interrupt()) | |
781 | return; | |
782 | ||
783 | local_irq_save(flags); | |
784 | ||
785 | if (local_softirq_pending()) { | |
786 | void *orig_sp, *sp = softirq_stack[smp_processor_id()]; | |
787 | ||
788 | sp += THREAD_SIZE - 192 - STACK_BIAS; | |
789 | ||
790 | __asm__ __volatile__("mov %%sp, %0\n\t" | |
791 | "mov %1, %%sp" | |
792 | : "=&r" (orig_sp) | |
793 | : "r" (sp)); | |
794 | __do_softirq(); | |
795 | __asm__ __volatile__("mov %0, %%sp" | |
796 | : : "r" (orig_sp)); | |
797 | } | |
798 | ||
799 | local_irq_restore(flags); | |
800 | } | |
801 | ||
e0204409 DM |
802 | #ifdef CONFIG_HOTPLUG_CPU |
803 | void fixup_irqs(void) | |
804 | { | |
805 | unsigned int irq; | |
806 | ||
807 | for (irq = 0; irq < NR_IRQS; irq++) { | |
808 | unsigned long flags; | |
809 | ||
810 | spin_lock_irqsave(&irq_desc[irq].lock, flags); | |
811 | if (irq_desc[irq].action && | |
812 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | |
813 | if (irq_desc[irq].chip->set_affinity) | |
814 | irq_desc[irq].chip->set_affinity(irq, | |
e65e49d0 | 815 | irq_desc[irq].affinity); |
e0204409 DM |
816 | } |
817 | spin_unlock_irqrestore(&irq_desc[irq].lock, flags); | |
818 | } | |
2eb2f779 DM |
819 | |
820 | tick_ops->disable_irq(); | |
e0204409 DM |
821 | } |
822 | #endif | |
823 | ||
cdd5186f DM |
824 | struct sun5_timer { |
825 | u64 count0; | |
826 | u64 limit0; | |
827 | u64 count1; | |
828 | u64 limit1; | |
829 | }; | |
1da177e4 | 830 | |
cdd5186f | 831 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
832 | static u64 prom_limit0, prom_limit1; |
833 | ||
834 | static void map_prom_timers(void) | |
835 | { | |
25c7581b | 836 | struct device_node *dp; |
6a23acf3 | 837 | const unsigned int *addr; |
1da177e4 LT |
838 | |
839 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
840 | dp = of_find_node_by_path("/"); |
841 | dp = dp->child; | |
842 | while (dp) { | |
843 | if (!strcmp(dp->name, "counter-timer")) | |
844 | break; | |
845 | dp = dp->sibling; | |
846 | } | |
1da177e4 LT |
847 | |
848 | /* Assume if node is not present, PROM uses different tick mechanism | |
849 | * which we should not care about. | |
850 | */ | |
25c7581b | 851 | if (!dp) { |
1da177e4 LT |
852 | prom_timers = (struct sun5_timer *) 0; |
853 | return; | |
854 | } | |
855 | ||
856 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
857 | addr = of_get_property(dp, "address", NULL); |
858 | if (!addr) { | |
1da177e4 LT |
859 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
860 | prom_timers = (struct sun5_timer *) 0; | |
861 | return; | |
862 | } | |
863 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
864 | } | |
865 | ||
866 | static void kill_prom_timer(void) | |
867 | { | |
868 | if (!prom_timers) | |
869 | return; | |
870 | ||
871 | /* Save them away for later. */ | |
872 | prom_limit0 = prom_timers->limit0; | |
873 | prom_limit1 = prom_timers->limit1; | |
874 | ||
875 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
876 | * We turn both off here just to be paranoid. | |
877 | */ | |
878 | prom_timers->limit0 = 0; | |
879 | prom_timers->limit1 = 0; | |
880 | ||
881 | /* Wheee, eat the interrupt packet too... */ | |
882 | __asm__ __volatile__( | |
883 | " mov 0x40, %%g2\n" | |
884 | " ldxa [%%g0] %0, %%g1\n" | |
885 | " ldxa [%%g2] %1, %%g1\n" | |
886 | " stxa %%g0, [%%g0] %0\n" | |
887 | " membar #Sync\n" | |
888 | : /* no outputs */ | |
889 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
890 | : "g1", "g2"); | |
891 | } | |
892 | ||
9843099f | 893 | void notrace init_irqwork_curcpu(void) |
1da177e4 | 894 | { |
1da177e4 LT |
895 | int cpu = hard_smp_processor_id(); |
896 | ||
eb2d8d60 | 897 | trap_block[cpu].irq_worklist_pa = 0UL; |
1da177e4 LT |
898 | } |
899 | ||
5cbc3073 DM |
900 | /* Please be very careful with register_one_mondo() and |
901 | * sun4v_register_mondo_queues(). | |
902 | * | |
903 | * On SMP this gets invoked from the CPU trampoline before | |
904 | * the cpu has fully taken over the trap table from OBP, | |
905 | * and it's kernel stack + %g6 thread register state is | |
906 | * not fully cooked yet. | |
907 | * | |
908 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
909 | * from these two routines. | |
910 | */ | |
911 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 912 | { |
5cbc3073 | 913 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
914 | unsigned long status; |
915 | ||
916 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
917 | if (status != HV_EOK) { | |
918 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
919 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
920 | prom_halt(); |
921 | } | |
922 | } | |
923 | ||
9843099f | 924 | void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 925 | { |
b5a37e96 DM |
926 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
927 | ||
5cbc3073 DM |
928 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
929 | tb->cpu_mondo_qmask); | |
930 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
931 | tb->dev_mondo_qmask); | |
932 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
933 | tb->resum_qmask); | |
934 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
935 | tb->nonresum_qmask); | |
b5a37e96 DM |
936 | } |
937 | ||
b434e719 | 938 | static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 939 | { |
5cbc3073 | 940 | unsigned long size = PAGE_ALIGN(qmask + 1); |
719023fb | 941 | void *p = __alloc_bootmem(size, size, 0); |
5cbc3073 | 942 | if (!p) { |
b5a37e96 DM |
943 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
944 | prom_halt(); | |
945 | } | |
946 | ||
5cbc3073 | 947 | *pa_ptr = __pa(p); |
b5a37e96 DM |
948 | } |
949 | ||
b434e719 | 950 | static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 951 | { |
5cbc3073 | 952 | unsigned long size = PAGE_ALIGN(qmask + 1); |
719023fb | 953 | void *p = __alloc_bootmem(size, size, 0); |
5b0c0572 | 954 | |
5cbc3073 | 955 | if (!p) { |
5b0c0572 DM |
956 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
957 | prom_halt(); | |
958 | } | |
959 | ||
5cbc3073 | 960 | *pa_ptr = __pa(p); |
5b0c0572 DM |
961 | } |
962 | ||
b434e719 | 963 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
964 | { |
965 | #ifdef CONFIG_SMP | |
b5a37e96 | 966 | void *page; |
1d2f1f90 DM |
967 | |
968 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
969 | ||
719023fb | 970 | page = alloc_bootmem_pages(PAGE_SIZE); |
1d2f1f90 DM |
971 | if (!page) { |
972 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
973 | prom_halt(); | |
974 | } | |
975 | ||
976 | tb->cpu_mondo_block_pa = __pa(page); | |
977 | tb->cpu_list_pa = __pa(page + 64); | |
978 | #endif | |
979 | } | |
980 | ||
b434e719 DM |
981 | /* Allocate mondo and error queues for all possible cpus. */ |
982 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 983 | { |
b434e719 | 984 | int cpu; |
ac29c11d | 985 | |
b434e719 DM |
986 | for_each_possible_cpu(cpu) { |
987 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 988 | |
b434e719 DM |
989 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
990 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
991 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); | |
992 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
993 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
994 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, | |
995 | tb->nonresum_qmask); | |
43f58923 DM |
996 | } |
997 | } | |
998 | ||
999 | static void __init init_send_mondo_info(void) | |
1000 | { | |
1001 | int cpu; | |
1002 | ||
1003 | for_each_possible_cpu(cpu) { | |
1004 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 1005 | |
b434e719 | 1006 | init_cpu_send_mondo_info(tb); |
72aff53f | 1007 | } |
ac29c11d DM |
1008 | } |
1009 | ||
e18e2a00 DM |
1010 | static struct irqaction timer_irq_action = { |
1011 | .name = "timer", | |
1012 | }; | |
1013 | ||
1da177e4 LT |
1014 | /* Only invoked on boot processor. */ |
1015 | void __init init_IRQ(void) | |
1016 | { | |
10397e40 DM |
1017 | unsigned long size; |
1018 | ||
1da177e4 LT |
1019 | map_prom_timers(); |
1020 | kill_prom_timer(); | |
1da177e4 | 1021 | |
10397e40 | 1022 | size = sizeof(struct ino_bucket) * NUM_IVECS; |
719023fb | 1023 | ivector_table = alloc_bootmem(size); |
10397e40 DM |
1024 | if (!ivector_table) { |
1025 | prom_printf("Fatal error, cannot allocate ivector_table\n"); | |
1026 | prom_halt(); | |
1027 | } | |
42d5f99b DM |
1028 | __flush_dcache_range((unsigned long) ivector_table, |
1029 | ((unsigned long) ivector_table) + size); | |
10397e40 DM |
1030 | |
1031 | ivector_table_pa = __pa(ivector_table); | |
eb2d8d60 | 1032 | |
ac29c11d | 1033 | if (tlb_type == hypervisor) |
b434e719 | 1034 | sun4v_init_mondo_queues(); |
ac29c11d | 1035 | |
43f58923 DM |
1036 | init_send_mondo_info(); |
1037 | ||
1038 | if (tlb_type == hypervisor) { | |
1039 | /* Load up the boot cpu's entries. */ | |
1040 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
1041 | } | |
1042 | ||
1da177e4 LT |
1043 | /* We need to clear any IRQ's pending in the soft interrupt |
1044 | * registers, a spurious one could be left around from the | |
1045 | * PROM timer which we just disabled. | |
1046 | */ | |
1047 | clear_softint(get_softint()); | |
1048 | ||
1049 | /* Now that ivector table is initialized, it is safe | |
1050 | * to receive IRQ vector traps. We will normally take | |
1051 | * one or two right now, in case some device PROM used | |
1052 | * to boot us wants to speak to us. We just ignore them. | |
1053 | */ | |
1054 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
1055 | "or %%g1, %0, %%g1\n\t" | |
1056 | "wrpr %%g1, 0x0, %%pstate" | |
1057 | : /* No outputs */ | |
1058 | : "i" (PSTATE_IE) | |
1059 | : "g1"); | |
1da177e4 | 1060 | |
e18e2a00 | 1061 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 1062 | } |