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5213a780 KE |
1 | /* |
2 | * Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB | |
3 | * Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB | |
4 | */ | |
5 | ||
6 | #include <linux/kernel.h> | |
5213a780 KE |
7 | #include <linux/errno.h> |
8 | #include <linux/mutex.h> | |
5213a780 KE |
9 | #include <linux/of.h> |
10 | #include <linux/of_platform.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/of_device.h> | |
62f08283 TK |
13 | #include <linux/clocksource.h> |
14 | #include <linux/clockchips.h> | |
8401707f | 15 | |
5213a780 KE |
16 | #include <asm/oplib.h> |
17 | #include <asm/timer.h> | |
18 | #include <asm/prom.h> | |
19 | #include <asm/leon.h> | |
20 | #include <asm/leon_amba.h> | |
8401707f KE |
21 | #include <asm/traps.h> |
22 | #include <asm/cacheflush.h> | |
4c6773c3 | 23 | #include <asm/smp.h> |
01dae0f0 | 24 | #include <asm/setup.h> |
5213a780 | 25 | |
93bb32f6 | 26 | #include "kernel.h" |
5213a780 KE |
27 | #include "prom.h" |
28 | #include "irq.h" | |
29 | ||
53aea7ca DH |
30 | struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; /* interrupt controller base address */ |
31 | struct leon3_gptimer_regs_map *leon3_gptimer_regs; /* timer controller base address */ | |
5213a780 KE |
32 | |
33 | int leondebug_irq_disable; | |
34 | int leon_debug_irqout; | |
35 | static int dummy_master_l10_counter; | |
7279b82c | 36 | unsigned long amba_system_id; |
d61a38b2 | 37 | static DEFINE_SPINLOCK(leon_irq_lock); |
5213a780 | 38 | |
53aea7ca | 39 | unsigned long leon3_gptimer_irq; /* interrupt controller irq number */ |
2791c1a4 | 40 | unsigned long leon3_gptimer_idx; /* Timer Index (0..6) within Timer Core */ |
5213a780 | 41 | unsigned int sparc_leon_eirq; |
a481b5d0 | 42 | #define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu]) |
4c6773c3 DH |
43 | #define LEON_IACK (&leon3_irqctrl_regs->iclear) |
44 | #define LEON_DO_ACK_HW 1 | |
5213a780 | 45 | |
4c6773c3 DH |
46 | /* Return the last ACKed IRQ by the Extended IRQ controller. It has already |
47 | * been (automatically) ACKed when the CPU takes the trap. | |
48 | */ | |
49 | static inline unsigned int leon_eirq_get(int cpu) | |
5213a780 KE |
50 | { |
51 | return LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->intid[cpu]) & 0x1f; | |
52 | } | |
53 | ||
4c6773c3 DH |
54 | /* Handle one or multiple IRQs from the extended interrupt controller */ |
55 | static void leon_handle_ext_irq(unsigned int irq, struct irq_desc *desc) | |
5213a780 | 56 | { |
4c6773c3 | 57 | unsigned int eirq; |
20424d85 | 58 | struct irq_bucket *p; |
01dae0f0 | 59 | int cpu = sparc_leon3_cpuid(); |
4c6773c3 DH |
60 | |
61 | eirq = leon_eirq_get(cpu); | |
20424d85 AL |
62 | p = irq_map[eirq]; |
63 | if ((eirq & 0x10) && p && p->irq) /* bit4 tells if IRQ happened */ | |
64 | generic_handle_irq(p->irq); | |
5213a780 KE |
65 | } |
66 | ||
67 | /* The extended IRQ controller has been found, this function registers it */ | |
4c6773c3 | 68 | void leon_eirq_setup(unsigned int eirq) |
5213a780 | 69 | { |
4c6773c3 DH |
70 | unsigned long mask, oldmask; |
71 | unsigned int veirq; | |
5213a780 | 72 | |
4c6773c3 DH |
73 | if (eirq < 1 || eirq > 0xf) { |
74 | printk(KERN_ERR "LEON EXT IRQ NUMBER BAD: %d\n", eirq); | |
75 | return; | |
5213a780 KE |
76 | } |
77 | ||
4c6773c3 DH |
78 | veirq = leon_build_device_irq(eirq, leon_handle_ext_irq, "extirq", 0); |
79 | ||
80 | /* | |
81 | * Unmask the Extended IRQ, the IRQs routed through the Ext-IRQ | |
82 | * controller have a mask-bit of their own, so this is safe. | |
83 | */ | |
84 | irq_link(veirq); | |
85 | mask = 1 << eirq; | |
01dae0f0 DH |
86 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(boot_cpu_id)); |
87 | LEON3_BYPASS_STORE_PA(LEON_IMASK(boot_cpu_id), (oldmask | mask)); | |
4c6773c3 | 88 | sparc_leon_eirq = eirq; |
5213a780 KE |
89 | } |
90 | ||
4ba22b16 | 91 | unsigned long leon_get_irqmask(unsigned int irq) |
5213a780 KE |
92 | { |
93 | unsigned long mask; | |
94 | ||
95 | if (!irq || ((irq > 0xf) && !sparc_leon_eirq) | |
96 | || ((irq > 0x1f) && sparc_leon_eirq)) { | |
97 | printk(KERN_ERR | |
98 | "leon_get_irqmask: false irq number: %d\n", irq); | |
99 | mask = 0; | |
100 | } else { | |
101 | mask = LEON_HARD_INT(irq); | |
102 | } | |
103 | return mask; | |
104 | } | |
105 | ||
5eb1f4fc DH |
106 | #ifdef CONFIG_SMP |
107 | static int irq_choose_cpu(const struct cpumask *affinity) | |
108 | { | |
109 | cpumask_t mask; | |
110 | ||
0b5f9c00 RR |
111 | cpumask_and(&mask, cpu_online_mask, affinity); |
112 | if (cpumask_equal(&mask, cpu_online_mask) || cpumask_empty(&mask)) | |
01dae0f0 | 113 | return boot_cpu_id; |
5eb1f4fc | 114 | else |
0b5f9c00 | 115 | return cpumask_first(&mask); |
5eb1f4fc DH |
116 | } |
117 | #else | |
01dae0f0 | 118 | #define irq_choose_cpu(affinity) boot_cpu_id |
5eb1f4fc DH |
119 | #endif |
120 | ||
121 | static int leon_set_affinity(struct irq_data *data, const struct cpumask *dest, | |
122 | bool force) | |
123 | { | |
124 | unsigned long mask, oldmask, flags; | |
125 | int oldcpu, newcpu; | |
126 | ||
127 | mask = (unsigned long)data->chip_data; | |
128 | oldcpu = irq_choose_cpu(data->affinity); | |
129 | newcpu = irq_choose_cpu(dest); | |
130 | ||
131 | if (oldcpu == newcpu) | |
132 | goto out; | |
133 | ||
134 | /* unmask on old CPU first before enabling on the selected CPU */ | |
135 | spin_lock_irqsave(&leon_irq_lock, flags); | |
136 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(oldcpu)); | |
137 | LEON3_BYPASS_STORE_PA(LEON_IMASK(oldcpu), (oldmask & ~mask)); | |
138 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(newcpu)); | |
139 | LEON3_BYPASS_STORE_PA(LEON_IMASK(newcpu), (oldmask | mask)); | |
140 | spin_unlock_irqrestore(&leon_irq_lock, flags); | |
141 | out: | |
142 | return IRQ_SET_MASK_OK; | |
143 | } | |
144 | ||
6baa9b20 | 145 | static void leon_unmask_irq(struct irq_data *data) |
5213a780 | 146 | { |
a481b5d0 | 147 | unsigned long mask, oldmask, flags; |
5eb1f4fc | 148 | int cpu; |
6baa9b20 SR |
149 | |
150 | mask = (unsigned long)data->chip_data; | |
5eb1f4fc | 151 | cpu = irq_choose_cpu(data->affinity); |
d61a38b2 | 152 | spin_lock_irqsave(&leon_irq_lock, flags); |
5eb1f4fc DH |
153 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(cpu)); |
154 | LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask | mask)); | |
d61a38b2 | 155 | spin_unlock_irqrestore(&leon_irq_lock, flags); |
5213a780 KE |
156 | } |
157 | ||
6baa9b20 | 158 | static void leon_mask_irq(struct irq_data *data) |
5213a780 | 159 | { |
a481b5d0 | 160 | unsigned long mask, oldmask, flags; |
5eb1f4fc | 161 | int cpu; |
6baa9b20 SR |
162 | |
163 | mask = (unsigned long)data->chip_data; | |
5eb1f4fc | 164 | cpu = irq_choose_cpu(data->affinity); |
d61a38b2 | 165 | spin_lock_irqsave(&leon_irq_lock, flags); |
5eb1f4fc DH |
166 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(cpu)); |
167 | LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask & ~mask)); | |
d61a38b2 | 168 | spin_unlock_irqrestore(&leon_irq_lock, flags); |
5213a780 KE |
169 | } |
170 | ||
6baa9b20 SR |
171 | static unsigned int leon_startup_irq(struct irq_data *data) |
172 | { | |
173 | irq_link(data->irq); | |
174 | leon_unmask_irq(data); | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static void leon_shutdown_irq(struct irq_data *data) | |
179 | { | |
180 | leon_mask_irq(data); | |
181 | irq_unlink(data->irq); | |
182 | } | |
183 | ||
4c6773c3 DH |
184 | /* Used by external level sensitive IRQ handlers on the LEON: ACK IRQ ctrl */ |
185 | static void leon_eoi_irq(struct irq_data *data) | |
186 | { | |
187 | unsigned long mask = (unsigned long)data->chip_data; | |
188 | ||
189 | if (mask & LEON_DO_ACK_HW) | |
190 | LEON3_BYPASS_STORE_PA(LEON_IACK, mask & ~LEON_DO_ACK_HW); | |
191 | } | |
192 | ||
6baa9b20 | 193 | static struct irq_chip leon_irq = { |
5eb1f4fc DH |
194 | .name = "leon", |
195 | .irq_startup = leon_startup_irq, | |
196 | .irq_shutdown = leon_shutdown_irq, | |
197 | .irq_mask = leon_mask_irq, | |
198 | .irq_unmask = leon_unmask_irq, | |
199 | .irq_eoi = leon_eoi_irq, | |
200 | .irq_set_affinity = leon_set_affinity, | |
6baa9b20 SR |
201 | }; |
202 | ||
4c6773c3 DH |
203 | /* |
204 | * Build a LEON IRQ for the edge triggered LEON IRQ controller: | |
205 | * Edge (normal) IRQ - handle_simple_irq, ack=DONT-CARE, never ack | |
206 | * Level IRQ (PCI|Level-GPIO) - handle_fasteoi_irq, ack=1, ack after ISR | |
207 | * Per-CPU Edge - handle_percpu_irq, ack=0 | |
208 | */ | |
209 | unsigned int leon_build_device_irq(unsigned int real_irq, | |
210 | irq_flow_handler_t flow_handler, | |
211 | const char *name, int do_ack) | |
6baa9b20 SR |
212 | { |
213 | unsigned int irq; | |
214 | unsigned long mask; | |
6e4741e7 | 215 | struct irq_desc *desc; |
6baa9b20 SR |
216 | |
217 | irq = 0; | |
4ba22b16 | 218 | mask = leon_get_irqmask(real_irq); |
6baa9b20 SR |
219 | if (mask == 0) |
220 | goto out; | |
221 | ||
222 | irq = irq_alloc(real_irq, real_irq); | |
223 | if (irq == 0) | |
224 | goto out; | |
225 | ||
4c6773c3 DH |
226 | if (do_ack) |
227 | mask |= LEON_DO_ACK_HW; | |
228 | ||
6e4741e7 AL |
229 | desc = irq_to_desc(irq); |
230 | if (!desc || !desc->handle_irq || desc->handle_irq == handle_bad_irq) { | |
231 | irq_set_chip_and_handler_name(irq, &leon_irq, | |
232 | flow_handler, name); | |
233 | irq_set_chip_data(irq, (void *)mask); | |
234 | } | |
6baa9b20 SR |
235 | |
236 | out: | |
237 | return irq; | |
238 | } | |
239 | ||
4c6773c3 DH |
240 | static unsigned int _leon_build_device_irq(struct platform_device *op, |
241 | unsigned int real_irq) | |
242 | { | |
243 | return leon_build_device_irq(real_irq, handle_simple_irq, "edge", 0); | |
244 | } | |
245 | ||
5d07b786 DH |
246 | void leon_update_virq_handling(unsigned int virq, |
247 | irq_flow_handler_t flow_handler, | |
248 | const char *name, int do_ack) | |
249 | { | |
250 | unsigned long mask = (unsigned long)irq_get_chip_data(virq); | |
251 | ||
252 | mask &= ~LEON_DO_ACK_HW; | |
253 | if (do_ack) | |
254 | mask |= LEON_DO_ACK_HW; | |
255 | ||
256 | irq_set_chip_and_handler_name(virq, &leon_irq, | |
257 | flow_handler, name); | |
258 | irq_set_chip_data(virq, (void *)mask); | |
259 | } | |
260 | ||
62f08283 TK |
261 | static u32 leon_cycles_offset(void) |
262 | { | |
263 | u32 rld, val, off; | |
264 | rld = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld); | |
265 | val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); | |
266 | off = rld - val; | |
267 | return rld - val; | |
268 | } | |
269 | ||
270 | #ifdef CONFIG_SMP | |
271 | ||
272 | /* smp clockevent irq */ | |
273 | irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused) | |
274 | { | |
275 | struct clock_event_device *ce; | |
276 | int cpu = smp_processor_id(); | |
277 | ||
278 | leon_clear_profile_irq(cpu); | |
279 | ||
1ffbc51a AL |
280 | if (cpu == boot_cpu_id) |
281 | timer_interrupt(irq, NULL); | |
282 | ||
62f08283 TK |
283 | ce = &per_cpu(sparc32_clockevent, cpu); |
284 | ||
285 | irq_enter(); | |
286 | if (ce->event_handler) | |
287 | ce->event_handler(ce); | |
288 | irq_exit(); | |
289 | ||
290 | return IRQ_HANDLED; | |
291 | } | |
292 | ||
293 | #endif /* CONFIG_SMP */ | |
294 | ||
295 | void __init leon_init_timers(void) | |
5213a780 | 296 | { |
4c6773c3 | 297 | int irq, eirq; |
2791c1a4 | 298 | struct device_node *rootnp, *np, *nnp; |
53aea7ca DH |
299 | struct property *pp; |
300 | int len; | |
01dae0f0 | 301 | int icsel; |
2791c1a4 | 302 | int ampopts; |
6baa9b20 | 303 | int err; |
1ffbc51a | 304 | u32 config; |
5213a780 | 305 | |
62f08283 TK |
306 | sparc_config.get_cycles_offset = leon_cycles_offset; |
307 | sparc_config.cs_period = 1000000 / HZ; | |
308 | sparc_config.features |= FEAT_L10_CLOCKSOURCE; | |
309 | ||
310 | #ifndef CONFIG_SMP | |
311 | sparc_config.features |= FEAT_L10_CLOCKEVENT; | |
312 | #endif | |
313 | ||
5213a780 KE |
314 | leondebug_irq_disable = 0; |
315 | leon_debug_irqout = 0; | |
316 | master_l10_counter = (unsigned int *)&dummy_master_l10_counter; | |
317 | dummy_master_l10_counter = 0; | |
318 | ||
53aea7ca DH |
319 | rootnp = of_find_node_by_path("/ambapp0"); |
320 | if (!rootnp) | |
321 | goto bad; | |
7279b82c DH |
322 | |
323 | /* Find System ID: GRLIB build ID and optional CHIP ID */ | |
324 | pp = of_find_property(rootnp, "systemid", &len); | |
325 | if (pp) | |
326 | amba_system_id = *(unsigned long *)pp->value; | |
327 | ||
328 | /* Find IRQMP IRQ Controller Registers base adr otherwise bail out */ | |
53aea7ca | 329 | np = of_find_node_by_name(rootnp, "GAISLER_IRQMP"); |
9742e72c DH |
330 | if (!np) { |
331 | np = of_find_node_by_name(rootnp, "01_00d"); | |
332 | if (!np) | |
333 | goto bad; | |
334 | } | |
53aea7ca DH |
335 | pp = of_find_property(np, "reg", &len); |
336 | if (!pp) | |
337 | goto bad; | |
338 | leon3_irqctrl_regs = *(struct leon3_irqctrl_regs_map **)pp->value; | |
339 | ||
340 | /* Find GPTIMER Timer Registers base address otherwise bail out. */ | |
2791c1a4 DH |
341 | nnp = rootnp; |
342 | do { | |
343 | np = of_find_node_by_name(nnp, "GAISLER_GPTIMER"); | |
344 | if (!np) { | |
345 | np = of_find_node_by_name(nnp, "01_011"); | |
346 | if (!np) | |
347 | goto bad; | |
348 | } | |
349 | ||
350 | ampopts = 0; | |
351 | pp = of_find_property(np, "ampopts", &len); | |
352 | if (pp) { | |
353 | ampopts = *(int *)pp->value; | |
354 | if (ampopts == 0) { | |
355 | /* Skip this instance, resource already | |
356 | * allocated by other OS */ | |
357 | nnp = np; | |
358 | continue; | |
359 | } | |
360 | } | |
361 | ||
362 | /* Select Timer-Instance on Timer Core. Default is zero */ | |
363 | leon3_gptimer_idx = ampopts & 0x7; | |
364 | ||
365 | pp = of_find_property(np, "reg", &len); | |
366 | if (pp) | |
367 | leon3_gptimer_regs = *(struct leon3_gptimer_regs_map **) | |
368 | pp->value; | |
369 | pp = of_find_property(np, "interrupts", &len); | |
370 | if (pp) | |
371 | leon3_gptimer_irq = *(unsigned int *)pp->value; | |
372 | } while (0); | |
53aea7ca | 373 | |
a481b5d0 DH |
374 | if (!(leon3_gptimer_regs && leon3_irqctrl_regs && leon3_gptimer_irq)) |
375 | goto bad; | |
376 | ||
377 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val, 0); | |
378 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld, | |
379 | (((1000000 / HZ) - 1))); | |
380 | LEON3_BYPASS_STORE_PA( | |
2791c1a4 | 381 | &leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 0); |
5213a780 | 382 | |
a481b5d0 DH |
383 | /* |
384 | * The IRQ controller may (if implemented) consist of multiple | |
385 | * IRQ controllers, each mapped on a 4Kb boundary. | |
386 | * Each CPU may be routed to different IRQCTRLs, however | |
387 | * we assume that all CPUs (in SMP system) is routed to the | |
388 | * same IRQ Controller, and for non-SMP only one IRQCTRL is | |
389 | * accessed anyway. | |
390 | * In AMP systems, Linux must run on CPU0 for the time being. | |
391 | */ | |
01dae0f0 DH |
392 | icsel = LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->icsel[boot_cpu_id/8]); |
393 | icsel = (icsel >> ((7 - (boot_cpu_id&0x7)) * 4)) & 0xf; | |
a481b5d0 DH |
394 | leon3_irqctrl_regs += icsel; |
395 | ||
970def65 DH |
396 | /* Mask all IRQs on boot-cpu IRQ controller */ |
397 | LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[boot_cpu_id], 0); | |
398 | ||
a481b5d0 DH |
399 | /* Probe extended IRQ controller */ |
400 | eirq = (LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->mpstatus) | |
401 | >> 16) & 0xf; | |
402 | if (eirq != 0) | |
403 | leon_eirq_setup(eirq); | |
404 | ||
10f0d07c DH |
405 | #ifdef CONFIG_SMP |
406 | { | |
407 | unsigned long flags; | |
408 | ||
409 | /* | |
410 | * In SMP, sun4m adds a IPI handler to IRQ trap handler that | |
411 | * LEON never must take, sun4d and LEON overwrites the branch | |
412 | * with a NOP. | |
413 | */ | |
414 | local_irq_save(flags); | |
415 | patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */ | |
5d83d666 | 416 | local_ops->cache_all(); |
10f0d07c DH |
417 | local_irq_restore(flags); |
418 | } | |
419 | #endif | |
420 | ||
1ffbc51a AL |
421 | config = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config); |
422 | if (config & (1 << LEON3_GPTIMER_SEPIRQ)) | |
423 | leon3_gptimer_irq += leon3_gptimer_idx; | |
424 | else if ((config & LEON3_GPTIMER_TIMERS) > 1) | |
425 | pr_warn("GPTIMER uses shared irqs, using other timers of the same core will fail.\n"); | |
8401707f KE |
426 | |
427 | #ifdef CONFIG_SMP | |
a481b5d0 | 428 | /* Install per-cpu IRQ handler for broadcasted ticker */ |
1ffbc51a | 429 | irq = leon_build_device_irq(leon3_gptimer_irq, handle_percpu_irq, |
a481b5d0 | 430 | "per-cpu", 0); |
62f08283 | 431 | err = request_irq(irq, leon_percpu_timer_ce_interrupt, |
1ffbc51a AL |
432 | IRQF_PERCPU | IRQF_TIMER, "timer", NULL); |
433 | #else | |
434 | irq = _leon_build_device_irq(NULL, leon3_gptimer_irq); | |
435 | err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); | |
436 | #endif | |
a481b5d0 | 437 | if (err) { |
1ffbc51a | 438 | pr_err("Unable to attach timer IRQ%d\n", irq); |
a481b5d0 DH |
439 | prom_halt(); |
440 | } | |
1ffbc51a | 441 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, |
a481b5d0 DH |
442 | LEON3_GPTIMER_EN | |
443 | LEON3_GPTIMER_RL | | |
444 | LEON3_GPTIMER_LD | | |
445 | LEON3_GPTIMER_IRQEN); | |
53aea7ca DH |
446 | return; |
447 | bad: | |
448 | printk(KERN_ERR "No Timer/irqctrl found\n"); | |
449 | BUG(); | |
450 | return; | |
5213a780 KE |
451 | } |
452 | ||
08c9388f | 453 | static void leon_clear_clock_irq(void) |
5213a780 KE |
454 | { |
455 | } | |
456 | ||
08c9388f | 457 | static void leon_load_profile_irq(int cpu, unsigned int limit) |
5213a780 | 458 | { |
5213a780 KE |
459 | } |
460 | ||
5213a780 KE |
461 | void __init leon_trans_init(struct device_node *dp) |
462 | { | |
463 | if (strcmp(dp->type, "cpu") == 0 && strcmp(dp->name, "<NULL>") == 0) { | |
464 | struct property *p; | |
465 | p = of_find_property(dp, "mid", (void *)0); | |
466 | if (p) { | |
467 | int mid; | |
468 | dp->name = prom_early_alloc(5 + 1); | |
469 | memcpy(&mid, p->value, p->length); | |
470 | sprintf((char *)dp->name, "cpu%.2d", mid); | |
471 | } | |
472 | } | |
473 | } | |
474 | ||
8401707f | 475 | #ifdef CONFIG_SMP |
8401707f KE |
476 | void leon_clear_profile_irq(int cpu) |
477 | { | |
478 | } | |
479 | ||
480 | void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu) | |
481 | { | |
482 | unsigned long mask, flags, *addr; | |
4ba22b16 | 483 | mask = leon_get_irqmask(irq_nr); |
d61a38b2 | 484 | spin_lock_irqsave(&leon_irq_lock, flags); |
a481b5d0 DH |
485 | addr = (unsigned long *)LEON_IMASK(cpu); |
486 | LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask)); | |
d61a38b2 | 487 | spin_unlock_irqrestore(&leon_irq_lock, flags); |
8401707f KE |
488 | } |
489 | ||
490 | #endif | |
491 | ||
5213a780 KE |
492 | void __init leon_init_IRQ(void) |
493 | { | |
472bc4f2 SR |
494 | sparc_config.init_timers = leon_init_timers; |
495 | sparc_config.build_device_irq = _leon_build_device_irq; | |
08c9388f SR |
496 | sparc_config.clock_rate = 1000000; |
497 | sparc_config.clear_clock_irq = leon_clear_clock_irq; | |
498 | sparc_config.load_profile_irq = leon_load_profile_irq; | |
5213a780 | 499 | } |