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1da177e4 LT |
1 | /* |
2 | * pcic.c: MicroSPARC-IIep PCI controller support | |
3 | * | |
4 | * Copyright (C) 1998 V. Roganov and G. Raiko | |
5 | * | |
6 | * Code is derived from Ultra/PCI PSYCHO controller support, see that | |
7 | * for author info. | |
8 | * | |
9 | * Support for diverse IIep based platforms by Pete Zaitcev. | |
10 | * CP-1200 by Eric Brower. | |
11 | */ | |
12 | ||
1da177e4 LT |
13 | #include <linux/kernel.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/jiffies.h> | |
19 | ||
1da177e4 LT |
20 | #include <asm/swift.h> /* for cache flushing. */ |
21 | #include <asm/io.h> | |
22 | ||
23 | #include <linux/ctype.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/time.h> | |
26 | #include <linux/timex.h> | |
27 | #include <linux/interrupt.h> | |
28 | ||
29 | #include <asm/irq.h> | |
30 | #include <asm/oplib.h> | |
942a6bdd | 31 | #include <asm/prom.h> |
1da177e4 | 32 | #include <asm/pcic.h> |
0299b137 | 33 | #include <asm/timex.h> |
1da177e4 LT |
34 | #include <asm/timer.h> |
35 | #include <asm/uaccess.h> | |
c2baeb05 | 36 | #include <asm/irq_regs.h> |
1da177e4 | 37 | |
32231a66 | 38 | #include "irq.h" |
1da177e4 | 39 | |
1da177e4 LT |
40 | /* |
41 | * I studied different documents and many live PROMs both from 2.30 | |
42 | * family and 3.xx versions. I came to the amazing conclusion: there is | |
43 | * absolutely no way to route interrupts in IIep systems relying on | |
44 | * information which PROM presents. We must hardcode interrupt routing | |
45 | * schematics. And this actually sucks. -- zaitcev 1999/05/12 | |
46 | * | |
47 | * To find irq for a device we determine which routing map | |
48 | * is in effect or, in other words, on which machine we are running. | |
49 | * We use PROM name for this although other techniques may be used | |
50 | * in special cases (Gleb reports a PROMless IIep based system). | |
51 | * Once we know the map we take device configuration address and | |
52 | * find PCIC pin number where INT line goes. Then we may either program | |
53 | * preferred irq into the PCIC or supply the preexisting irq to the device. | |
54 | */ | |
55 | struct pcic_ca2irq { | |
56 | unsigned char busno; /* PCI bus number */ | |
57 | unsigned char devfn; /* Configuration address */ | |
58 | unsigned char pin; /* PCIC external interrupt pin */ | |
59 | unsigned char irq; /* Preferred IRQ (mappable in PCIC) */ | |
60 | unsigned int force; /* Enforce preferred IRQ */ | |
61 | }; | |
62 | ||
63 | struct pcic_sn2list { | |
64 | char *sysname; | |
65 | struct pcic_ca2irq *intmap; | |
66 | int mapdim; | |
67 | }; | |
68 | ||
69 | /* | |
70 | * JavaEngine-1 apparently has different versions. | |
71 | * | |
72 | * According to communications with Sun folks, for P2 build 501-4628-03: | |
73 | * pin 0 - parallel, audio; | |
74 | * pin 1 - Ethernet; | |
75 | * pin 2 - su; | |
76 | * pin 3 - PS/2 kbd and mouse. | |
77 | * | |
78 | * OEM manual (805-1486): | |
79 | * pin 0: Ethernet | |
80 | * pin 1: All EBus | |
81 | * pin 2: IGA (unused) | |
82 | * pin 3: Not connected | |
83 | * OEM manual says that 501-4628 & 501-4811 are the same thing, | |
84 | * only the latter has NAND flash in place. | |
85 | * | |
86 | * So far unofficial Sun wins over the OEM manual. Poor OEMs... | |
87 | */ | |
88 | static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */ | |
89 | { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */ | |
90 | { 0, 0x01, 1, 6, 1 }, /* Happy Meal */ | |
91 | { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */ | |
92 | }; | |
93 | ||
94 | /* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */ | |
95 | static struct pcic_ca2irq pcic_i_jse[] = { | |
96 | { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ | |
97 | { 0, 0x01, 1, 6, 0 }, /* hme */ | |
98 | { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */ | |
99 | { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */ | |
100 | { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */ | |
101 | { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */ | |
102 | { 0, 0x80, 5, 11, 0 }, /* EIDE */ | |
103 | /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */ | |
104 | { 0, 0xA0, 4, 9, 0 }, /* USB */ | |
105 | /* | |
106 | * Some pins belong to non-PCI devices, we hardcode them in drivers. | |
107 | * sun4m timers - irq 10, 14 | |
108 | * PC style RTC - pin 7, irq 4 ? | |
109 | * Smart card, Parallel - pin 4 shared with USB, ISA | |
110 | * audio - pin 3, irq 5 ? | |
111 | */ | |
112 | }; | |
113 | ||
114 | /* SPARCengine-6 was the original release name of CP1200. | |
115 | * The documentation differs between the two versions | |
116 | */ | |
117 | static struct pcic_ca2irq pcic_i_se6[] = { | |
118 | { 0, 0x08, 0, 2, 0 }, /* SCSI */ | |
119 | { 0, 0x01, 1, 6, 0 }, /* HME */ | |
120 | { 0, 0x00, 3, 13, 0 }, /* EBus */ | |
121 | }; | |
122 | ||
123 | /* | |
124 | * Krups (courtesy of Varol Kaptan) | |
125 | * No documentation available, but it was easy to guess | |
126 | * because it was very similar to Espresso. | |
127 | * | |
128 | * pin 0 - kbd, mouse, serial; | |
129 | * pin 1 - Ethernet; | |
130 | * pin 2 - igs (we do not use it); | |
131 | * pin 3 - audio; | |
132 | * pin 4,5,6 - unused; | |
133 | * pin 7 - RTC (from P2 onwards as David B. says). | |
134 | */ | |
135 | static struct pcic_ca2irq pcic_i_jk[] = { | |
136 | { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ | |
137 | { 0, 0x01, 1, 6, 0 }, /* hme */ | |
138 | }; | |
139 | ||
140 | /* | |
141 | * Several entries in this list may point to the same routing map | |
142 | * as several PROMs may be installed on the same physical board. | |
143 | */ | |
144 | #define SN2L_INIT(name, map) \ | |
940fdc6e | 145 | { name, map, ARRAY_SIZE(map) } |
1da177e4 LT |
146 | |
147 | static struct pcic_sn2list pcic_known_sysnames[] = { | |
148 | SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */ | |
149 | SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */ | |
150 | SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */ | |
151 | SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */ | |
152 | SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */ | |
153 | { NULL, NULL, 0 } | |
154 | }; | |
155 | ||
156 | /* | |
157 | * Only one PCIC per IIep, | |
158 | * and since we have no SMP IIep, only one per system. | |
159 | */ | |
160 | static int pcic0_up; | |
161 | static struct linux_pcic pcic0; | |
162 | ||
f8ad23a4 | 163 | void __iomem *pcic_regs; |
1da177e4 LT |
164 | volatile int pcic_speculative; |
165 | volatile int pcic_trapped; | |
166 | ||
1da177e4 LT |
167 | |
168 | #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3)) | |
169 | ||
170 | static int pcic_read_config_dword(unsigned int busno, unsigned int devfn, | |
171 | int where, u32 *value) | |
172 | { | |
173 | struct linux_pcic *pcic; | |
174 | unsigned long flags; | |
175 | ||
176 | pcic = &pcic0; | |
177 | ||
178 | local_irq_save(flags); | |
179 | #if 0 /* does not fail here */ | |
180 | pcic_speculative = 1; | |
181 | pcic_trapped = 0; | |
182 | #endif | |
183 | writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); | |
184 | #if 0 /* does not fail here */ | |
185 | nop(); | |
186 | if (pcic_trapped) { | |
187 | local_irq_restore(flags); | |
188 | *value = ~0; | |
189 | return 0; | |
190 | } | |
191 | #endif | |
192 | pcic_speculative = 2; | |
193 | pcic_trapped = 0; | |
194 | *value = readl(pcic->pcic_config_space_data + (where&4)); | |
195 | nop(); | |
196 | if (pcic_trapped) { | |
197 | pcic_speculative = 0; | |
198 | local_irq_restore(flags); | |
199 | *value = ~0; | |
200 | return 0; | |
201 | } | |
202 | pcic_speculative = 0; | |
203 | local_irq_restore(flags); | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static int pcic_read_config(struct pci_bus *bus, unsigned int devfn, | |
208 | int where, int size, u32 *val) | |
209 | { | |
210 | unsigned int v; | |
211 | ||
212 | if (bus->number != 0) return -EINVAL; | |
213 | switch (size) { | |
214 | case 1: | |
215 | pcic_read_config_dword(bus->number, devfn, where&~3, &v); | |
216 | *val = 0xff & (v >> (8*(where & 3))); | |
217 | return 0; | |
218 | case 2: | |
219 | if (where&1) return -EINVAL; | |
220 | pcic_read_config_dword(bus->number, devfn, where&~3, &v); | |
221 | *val = 0xffff & (v >> (8*(where & 3))); | |
222 | return 0; | |
223 | case 4: | |
224 | if (where&3) return -EINVAL; | |
225 | pcic_read_config_dword(bus->number, devfn, where&~3, val); | |
226 | return 0; | |
227 | } | |
228 | return -EINVAL; | |
229 | } | |
230 | ||
231 | static int pcic_write_config_dword(unsigned int busno, unsigned int devfn, | |
232 | int where, u32 value) | |
233 | { | |
234 | struct linux_pcic *pcic; | |
235 | unsigned long flags; | |
236 | ||
237 | pcic = &pcic0; | |
238 | ||
239 | local_irq_save(flags); | |
240 | writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); | |
241 | writel(value, pcic->pcic_config_space_data + (where&4)); | |
242 | local_irq_restore(flags); | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int pcic_write_config(struct pci_bus *bus, unsigned int devfn, | |
247 | int where, int size, u32 val) | |
248 | { | |
249 | unsigned int v; | |
250 | ||
251 | if (bus->number != 0) return -EINVAL; | |
252 | switch (size) { | |
253 | case 1: | |
254 | pcic_read_config_dword(bus->number, devfn, where&~3, &v); | |
255 | v = (v & ~(0xff << (8*(where&3)))) | | |
256 | ((0xff&val) << (8*(where&3))); | |
257 | return pcic_write_config_dword(bus->number, devfn, where&~3, v); | |
258 | case 2: | |
259 | if (where&1) return -EINVAL; | |
260 | pcic_read_config_dword(bus->number, devfn, where&~3, &v); | |
261 | v = (v & ~(0xffff << (8*(where&3)))) | | |
262 | ((0xffff&val) << (8*(where&3))); | |
263 | return pcic_write_config_dword(bus->number, devfn, where&~3, v); | |
264 | case 4: | |
265 | if (where&3) return -EINVAL; | |
266 | return pcic_write_config_dword(bus->number, devfn, where, val); | |
267 | } | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | static struct pci_ops pcic_ops = { | |
272 | .read = pcic_read_config, | |
273 | .write = pcic_write_config, | |
274 | }; | |
275 | ||
276 | /* | |
277 | * On sparc64 pcibios_init() calls pci_controller_probe(). | |
278 | * We want PCIC probed little ahead so that interrupt controller | |
279 | * would be operational. | |
280 | */ | |
281 | int __init pcic_probe(void) | |
282 | { | |
283 | struct linux_pcic *pcic; | |
284 | struct linux_prom_registers regs[PROMREG_MAX]; | |
285 | struct linux_pbm_info* pbm; | |
286 | char namebuf[64]; | |
287 | int node; | |
288 | int err; | |
289 | ||
290 | if (pcic0_up) { | |
291 | prom_printf("PCIC: called twice!\n"); | |
292 | prom_halt(); | |
293 | } | |
294 | pcic = &pcic0; | |
295 | ||
296 | node = prom_getchild (prom_root_node); | |
297 | node = prom_searchsiblings (node, "pci"); | |
298 | if (node == 0) | |
299 | return -ENODEV; | |
300 | /* | |
301 | * Map in PCIC register set, config space, and IO base | |
302 | */ | |
303 | err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs)); | |
304 | if (err == 0 || err == -1) { | |
305 | prom_printf("PCIC: Error, cannot get PCIC registers " | |
306 | "from PROM.\n"); | |
307 | prom_halt(); | |
308 | } | |
309 | ||
310 | pcic0_up = 1; | |
311 | ||
312 | pcic->pcic_res_regs.name = "pcic_registers"; | |
313 | pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size); | |
314 | if (!pcic->pcic_regs) { | |
315 | prom_printf("PCIC: Error, cannot map PCIC registers.\n"); | |
316 | prom_halt(); | |
317 | } | |
318 | ||
319 | pcic->pcic_res_io.name = "pcic_io"; | |
320 | if ((pcic->pcic_io = (unsigned long) | |
321 | ioremap(regs[1].phys_addr, 0x10000)) == 0) { | |
322 | prom_printf("PCIC: Error, cannot map PCIC IO Base.\n"); | |
323 | prom_halt(); | |
324 | } | |
325 | ||
326 | pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr"; | |
327 | if ((pcic->pcic_config_space_addr = | |
328 | ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) { | |
794b26e0 | 329 | prom_printf("PCIC: Error, cannot map " |
1da177e4 LT |
330 | "PCI Configuration Space Address.\n"); |
331 | prom_halt(); | |
332 | } | |
333 | ||
334 | /* | |
335 | * Docs say three least significant bits in address and data | |
336 | * must be the same. Thus, we need adjust size of data. | |
337 | */ | |
338 | pcic->pcic_res_cfg_data.name = "pcic_cfg_data"; | |
339 | if ((pcic->pcic_config_space_data = | |
340 | ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) { | |
794b26e0 | 341 | prom_printf("PCIC: Error, cannot map " |
1da177e4 LT |
342 | "PCI Configuration Space Data.\n"); |
343 | prom_halt(); | |
344 | } | |
345 | ||
346 | pbm = &pcic->pbm; | |
347 | pbm->prom_node = node; | |
348 | prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; | |
349 | strcpy(pbm->prom_name, namebuf); | |
350 | ||
351 | { | |
352 | extern volatile int t_nmi[1]; | |
353 | extern int pcic_nmi_trap_patch[1]; | |
354 | ||
355 | t_nmi[0] = pcic_nmi_trap_patch[0]; | |
356 | t_nmi[1] = pcic_nmi_trap_patch[1]; | |
357 | t_nmi[2] = pcic_nmi_trap_patch[2]; | |
358 | t_nmi[3] = pcic_nmi_trap_patch[3]; | |
359 | swift_flush_dcache(); | |
360 | pcic_regs = pcic->pcic_regs; | |
361 | } | |
362 | ||
363 | prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0; | |
364 | { | |
365 | struct pcic_sn2list *p; | |
366 | ||
367 | for (p = pcic_known_sysnames; p->sysname != NULL; p++) { | |
368 | if (strcmp(namebuf, p->sysname) == 0) | |
369 | break; | |
370 | } | |
371 | pcic->pcic_imap = p->intmap; | |
372 | pcic->pcic_imdim = p->mapdim; | |
373 | } | |
374 | if (pcic->pcic_imap == NULL) { | |
375 | /* | |
376 | * We do not panic here for the sake of embedded systems. | |
377 | */ | |
378 | printk("PCIC: System %s is unknown, cannot route interrupts\n", | |
379 | namebuf); | |
380 | } | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic) | |
386 | { | |
387 | struct linux_pbm_info *pbm = &pcic->pbm; | |
388 | ||
389 | pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm); | |
390 | #if 0 /* deadwood transplanted from sparc64 */ | |
391 | pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node); | |
392 | pci_record_assignments(pbm, pbm->pci_bus); | |
393 | pci_assign_unassigned(pbm, pbm->pci_bus); | |
394 | pci_fixup_irq(pbm, pbm->pci_bus); | |
395 | #endif | |
396 | } | |
397 | ||
398 | /* | |
399 | * Main entry point from the PCI subsystem. | |
400 | */ | |
401 | static int __init pcic_init(void) | |
402 | { | |
403 | struct linux_pcic *pcic; | |
404 | ||
405 | /* | |
406 | * PCIC should be initialized at start of the timer. | |
407 | * So, here we report the presence of PCIC and do some magic passes. | |
408 | */ | |
409 | if(!pcic0_up) | |
410 | return 0; | |
411 | pcic = &pcic0; | |
412 | ||
413 | /* | |
414 | * Switch off IOTLB translation. | |
415 | */ | |
416 | writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE, | |
417 | pcic->pcic_regs+PCI_DVMA_CONTROL); | |
418 | ||
419 | /* | |
420 | * Increase mapped size for PCI memory space (DMA access). | |
421 | * Should be done in that order (size first, address second). | |
422 | * Why we couldn't set up 4GB and forget about it? XXX | |
423 | */ | |
424 | writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0); | |
425 | writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY, | |
426 | pcic->pcic_regs+PCI_BASE_ADDRESS_0); | |
427 | ||
428 | pcic_pbm_scan_bus(pcic); | |
429 | ||
1da177e4 LT |
430 | return 0; |
431 | } | |
432 | ||
433 | int pcic_present(void) | |
434 | { | |
435 | return pcic0_up; | |
436 | } | |
437 | ||
3a29db32 | 438 | static int __devinit pdev_to_pnode(struct linux_pbm_info *pbm, |
1da177e4 LT |
439 | struct pci_dev *pdev) |
440 | { | |
441 | struct linux_prom_pci_registers regs[PROMREG_MAX]; | |
442 | int err; | |
443 | int node = prom_getchild(pbm->prom_node); | |
444 | ||
445 | while(node) { | |
446 | err = prom_getproperty(node, "reg", | |
447 | (char *)®s[0], sizeof(regs)); | |
448 | if(err != 0 && err != -1) { | |
449 | unsigned long devfn = (regs[0].which_io >> 8) & 0xff; | |
450 | if(devfn == pdev->devfn) | |
451 | return node; | |
452 | } | |
453 | node = prom_getsibling(node); | |
454 | } | |
455 | return 0; | |
456 | } | |
457 | ||
458 | static inline struct pcidev_cookie *pci_devcookie_alloc(void) | |
459 | { | |
460 | return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC); | |
461 | } | |
462 | ||
463 | static void pcic_map_pci_device(struct linux_pcic *pcic, | |
464 | struct pci_dev *dev, int node) | |
465 | { | |
466 | char namebuf[64]; | |
467 | unsigned long address; | |
468 | unsigned long flags; | |
469 | int j; | |
470 | ||
471 | if (node == 0 || node == -1) { | |
472 | strcpy(namebuf, "???"); | |
473 | } else { | |
474 | prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; | |
475 | } | |
476 | ||
477 | for (j = 0; j < 6; j++) { | |
478 | address = dev->resource[j].start; | |
479 | if (address == 0) break; /* are sequential */ | |
480 | flags = dev->resource[j].flags; | |
481 | if ((flags & IORESOURCE_IO) != 0) { | |
482 | if (address < 0x10000) { | |
483 | /* | |
484 | * A device responds to I/O cycles on PCI. | |
485 | * We generate these cycles with memory | |
486 | * access into the fixed map (phys 0x30000000). | |
487 | * | |
488 | * Since a device driver does not want to | |
489 | * do ioremap() before accessing PC-style I/O, | |
490 | * we supply virtual, ready to access address. | |
491 | * | |
d61780c0 JG |
492 | * Note that request_region() |
493 | * works for these devices. | |
1da177e4 LT |
494 | * |
495 | * XXX Neat trick, but it's a *bad* idea | |
496 | * to shit into regions like that. | |
497 | * What if we want to allocate one more | |
498 | * PCI base address... | |
499 | */ | |
500 | dev->resource[j].start = | |
501 | pcic->pcic_io + address; | |
502 | dev->resource[j].end = 1; /* XXX */ | |
503 | dev->resource[j].flags = | |
504 | (flags & ~IORESOURCE_IO) | IORESOURCE_MEM; | |
505 | } else { | |
506 | /* | |
507 | * OOPS... PCI Spec allows this. Sun does | |
508 | * not have any devices getting above 64K | |
509 | * so it must be user with a weird I/O | |
510 | * board in a PCI slot. We must remap it | |
511 | * under 64K but it is not done yet. XXX | |
512 | */ | |
794b26e0 JP |
513 | printk("PCIC: Skipping I/O space at 0x%lx, " |
514 | "this will Oops if a driver attaches " | |
1da177e4 LT |
515 | "device '%s' at %02x:%02x)\n", address, |
516 | namebuf, dev->bus->number, dev->devfn); | |
517 | } | |
518 | } | |
519 | } | |
520 | } | |
521 | ||
522 | static void | |
523 | pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node) | |
524 | { | |
525 | struct pcic_ca2irq *p; | |
526 | int i, ivec; | |
527 | char namebuf[64]; | |
528 | ||
529 | if (node == 0 || node == -1) { | |
530 | strcpy(namebuf, "???"); | |
531 | } else { | |
532 | prom_getstring(node, "name", namebuf, sizeof(namebuf)); | |
533 | } | |
534 | ||
535 | if ((p = pcic->pcic_imap) == 0) { | |
536 | dev->irq = 0; | |
537 | return; | |
538 | } | |
539 | for (i = 0; i < pcic->pcic_imdim; i++) { | |
540 | if (p->busno == dev->bus->number && p->devfn == dev->devfn) | |
541 | break; | |
542 | p++; | |
543 | } | |
544 | if (i >= pcic->pcic_imdim) { | |
545 | printk("PCIC: device %s devfn %02x:%02x not found in %d\n", | |
546 | namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim); | |
547 | dev->irq = 0; | |
548 | return; | |
549 | } | |
550 | ||
551 | i = p->pin; | |
552 | if (i >= 0 && i < 4) { | |
553 | ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); | |
554 | dev->irq = ivec >> (i << 2) & 0xF; | |
555 | } else if (i >= 4 && i < 8) { | |
556 | ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); | |
557 | dev->irq = ivec >> ((i-4) << 2) & 0xF; | |
558 | } else { /* Corrupted map */ | |
559 | printk("PCIC: BAD PIN %d\n", i); for (;;) {} | |
560 | } | |
561 | /* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */ | |
562 | ||
563 | /* | |
564 | * dev->irq=0 means PROM did not bother to program the upper | |
565 | * half of PCIC. This happens on JS-E with PROM 3.11, for instance. | |
566 | */ | |
567 | if (dev->irq == 0 || p->force) { | |
568 | if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */ | |
569 | printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {} | |
570 | } | |
571 | printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n", | |
572 | p->irq, p->pin, dev->bus->number, dev->devfn); | |
573 | dev->irq = p->irq; | |
574 | ||
575 | i = p->pin; | |
576 | if (i >= 4) { | |
577 | ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); | |
578 | ivec &= ~(0xF << ((i - 4) << 2)); | |
579 | ivec |= p->irq << ((i - 4) << 2); | |
580 | writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI); | |
581 | } else { | |
582 | ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); | |
583 | ivec &= ~(0xF << (i << 2)); | |
584 | ivec |= p->irq << (i << 2); | |
585 | writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO); | |
586 | } | |
587 | } | |
1da177e4 LT |
588 | } |
589 | ||
590 | /* | |
591 | * Normally called from {do_}pci_scan_bus... | |
592 | */ | |
f6b45da1 | 593 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1da177e4 LT |
594 | { |
595 | struct pci_dev *dev; | |
596 | int i, has_io, has_mem; | |
597 | unsigned int cmd; | |
598 | struct linux_pcic *pcic; | |
599 | /* struct linux_pbm_info* pbm = &pcic->pbm; */ | |
600 | int node; | |
601 | struct pcidev_cookie *pcp; | |
602 | ||
603 | if (!pcic0_up) { | |
604 | printk("pcibios_fixup_bus: no PCIC\n"); | |
605 | return; | |
606 | } | |
607 | pcic = &pcic0; | |
608 | ||
609 | /* | |
610 | * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus); | |
611 | */ | |
612 | if (bus->number != 0) { | |
613 | printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number); | |
614 | return; | |
615 | } | |
616 | ||
617 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
618 | ||
619 | /* | |
620 | * Comment from i386 branch: | |
621 | * There are buggy BIOSes that forget to enable I/O and memory | |
622 | * access to PCI devices. We try to fix this, but we need to | |
623 | * be sure that the BIOS didn't forget to assign an address | |
624 | * to the device. [mj] | |
625 | * OBP is a case of such BIOS :-) | |
626 | */ | |
627 | has_io = has_mem = 0; | |
628 | for(i=0; i<6; i++) { | |
629 | unsigned long f = dev->resource[i].flags; | |
630 | if (f & IORESOURCE_IO) { | |
631 | has_io = 1; | |
632 | } else if (f & IORESOURCE_MEM) | |
633 | has_mem = 1; | |
634 | } | |
635 | pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); | |
636 | if (has_io && !(cmd & PCI_COMMAND_IO)) { | |
637 | printk("PCIC: Enabling I/O for device %02x:%02x\n", | |
638 | dev->bus->number, dev->devfn); | |
639 | cmd |= PCI_COMMAND_IO; | |
640 | pcic_write_config(dev->bus, dev->devfn, | |
641 | PCI_COMMAND, 2, cmd); | |
642 | } | |
643 | if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) { | |
644 | printk("PCIC: Enabling memory for device %02x:%02x\n", | |
645 | dev->bus->number, dev->devfn); | |
646 | cmd |= PCI_COMMAND_MEMORY; | |
647 | pcic_write_config(dev->bus, dev->devfn, | |
648 | PCI_COMMAND, 2, cmd); | |
649 | } | |
650 | ||
651 | node = pdev_to_pnode(&pcic->pbm, dev); | |
652 | if(node == 0) | |
653 | node = -1; | |
654 | ||
655 | /* cookies */ | |
656 | pcp = pci_devcookie_alloc(); | |
657 | pcp->pbm = &pcic->pbm; | |
942a6bdd | 658 | pcp->prom_node = of_find_node_by_phandle(node); |
1da177e4 LT |
659 | dev->sysdata = pcp; |
660 | ||
661 | /* fixing I/O to look like memory */ | |
662 | if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE) | |
663 | pcic_map_pci_device(pcic, dev, node); | |
664 | ||
665 | pcic_fill_irq(pcic, dev, node); | |
666 | } | |
667 | } | |
668 | ||
669 | /* | |
356d1647 | 670 | * pcic_pin_to_irq() is exported to bus probing code |
1da177e4 LT |
671 | */ |
672 | unsigned int | |
ee5ac9dd | 673 | pcic_pin_to_irq(unsigned int pin, const char *name) |
1da177e4 LT |
674 | { |
675 | struct linux_pcic *pcic = &pcic0; | |
676 | unsigned int irq; | |
677 | unsigned int ivec; | |
678 | ||
679 | if (pin < 4) { | |
680 | ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); | |
681 | irq = ivec >> (pin << 2) & 0xF; | |
682 | } else if (pin < 8) { | |
683 | ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); | |
684 | irq = ivec >> ((pin-4) << 2) & 0xF; | |
685 | } else { /* Corrupted map */ | |
686 | printk("PCIC: BAD PIN %d FOR %s\n", pin, name); | |
687 | for (;;) {} /* XXX Cannot panic properly in case of PROLL */ | |
688 | } | |
689 | /* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */ | |
690 | return irq; | |
691 | } | |
692 | ||
693 | /* Makes compiler happy */ | |
694 | static volatile int pcic_timer_dummy; | |
695 | ||
696 | static void pcic_clear_clock_irq(void) | |
697 | { | |
698 | pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT); | |
699 | } | |
700 | ||
0d84438d | 701 | static irqreturn_t pcic_timer_handler (int irq, void *h) |
1da177e4 LT |
702 | { |
703 | write_seqlock(&xtime_lock); /* Dummy, to show that we remember */ | |
704 | pcic_clear_clock_irq(); | |
3171a030 | 705 | do_timer(1); |
aa02cd2d | 706 | write_sequnlock(&xtime_lock); |
1da177e4 | 707 | #ifndef CONFIG_SMP |
0d84438d | 708 | update_process_times(user_mode(get_irq_regs())); |
1da177e4 | 709 | #endif |
1da177e4 LT |
710 | return IRQ_HANDLED; |
711 | } | |
712 | ||
713 | #define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */ | |
714 | #define TICK_TIMER_LIMIT ((100*1000000/4)/100) | |
715 | ||
0299b137 JS |
716 | u32 pci_gettimeoffset(void) |
717 | { | |
718 | /* | |
719 | * We divide all by 100 | |
720 | * to have microsecond resolution and to avoid overflow | |
721 | */ | |
722 | unsigned long count = | |
723 | readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW; | |
724 | count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100); | |
725 | return count * 1000; | |
726 | } | |
727 | ||
728 | ||
1da177e4 LT |
729 | void __init pci_time_init(void) |
730 | { | |
731 | struct linux_pcic *pcic = &pcic0; | |
732 | unsigned long v; | |
733 | int timer_irq, irq; | |
734 | ||
0299b137 JS |
735 | do_arch_gettimeoffset = pci_gettimeoffset; |
736 | ||
1da177e4 LT |
737 | btfixup(); |
738 | ||
739 | writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); | |
740 | /* PROM should set appropriate irq */ | |
741 | v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ); | |
742 | timer_irq = PCI_COUNTER_IRQ_SYS(v); | |
743 | writel (PCI_COUNTER_IRQ_SET(timer_irq, 0), | |
744 | pcic->pcic_regs+PCI_COUNTER_IRQ); | |
745 | irq = request_irq(timer_irq, pcic_timer_handler, | |
67413202 | 746 | (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL); |
1da177e4 LT |
747 | if (irq) { |
748 | prom_printf("time_init: unable to attach IRQ%d\n", timer_irq); | |
749 | prom_halt(); | |
750 | } | |
751 | local_irq_enable(); | |
752 | } | |
753 | ||
1da177e4 LT |
754 | |
755 | #if 0 | |
756 | static void watchdog_reset() { | |
757 | writeb(0, pcic->pcic_regs+PCI_SYS_STATUS); | |
758 | } | |
759 | #endif | |
760 | ||
761 | /* | |
762 | * Other archs parse arguments here. | |
763 | */ | |
f6b45da1 | 764 | char * __devinit pcibios_setup(char *str) |
1da177e4 LT |
765 | { |
766 | return str; | |
767 | } | |
768 | ||
3b7a17fc | 769 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
b26b2d49 | 770 | resource_size_t size, resource_size_t align) |
1da177e4 | 771 | { |
b26b2d49 | 772 | return res->start; |
1da177e4 LT |
773 | } |
774 | ||
775 | int pcibios_enable_device(struct pci_dev *pdev, int mask) | |
776 | { | |
777 | return 0; | |
778 | } | |
779 | ||
780 | /* | |
781 | * NMI | |
782 | */ | |
783 | void pcic_nmi(unsigned int pend, struct pt_regs *regs) | |
784 | { | |
785 | ||
786 | pend = flip_dword(pend); | |
787 | ||
788 | if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) { | |
789 | /* | |
790 | * XXX On CP-1200 PCI #SERR may happen, we do not know | |
791 | * what to do about it yet. | |
792 | */ | |
793 | printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n", | |
794 | pend, (int)regs->pc, pcic_speculative); | |
795 | for (;;) { } | |
796 | } | |
797 | pcic_speculative = 0; | |
798 | pcic_trapped = 1; | |
799 | regs->pc = regs->npc; | |
800 | regs->npc += 4; | |
801 | } | |
802 | ||
803 | static inline unsigned long get_irqmask(int irq_nr) | |
804 | { | |
805 | return 1 << irq_nr; | |
806 | } | |
807 | ||
1da177e4 LT |
808 | static void pcic_disable_irq(unsigned int irq_nr) |
809 | { | |
810 | unsigned long mask, flags; | |
811 | ||
812 | mask = get_irqmask(irq_nr); | |
813 | local_irq_save(flags); | |
814 | writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); | |
815 | local_irq_restore(flags); | |
816 | } | |
817 | ||
818 | static void pcic_enable_irq(unsigned int irq_nr) | |
819 | { | |
820 | unsigned long mask, flags; | |
821 | ||
822 | mask = get_irqmask(irq_nr); | |
823 | local_irq_save(flags); | |
824 | writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); | |
825 | local_irq_restore(flags); | |
826 | } | |
827 | ||
1da177e4 LT |
828 | static void pcic_load_profile_irq(int cpu, unsigned int limit) |
829 | { | |
830 | printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); | |
831 | } | |
832 | ||
833 | /* We assume the caller has disabled local interrupts when these are called, | |
834 | * or else very bizarre behavior will result. | |
835 | */ | |
836 | static void pcic_disable_pil_irq(unsigned int pil) | |
837 | { | |
838 | writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); | |
839 | } | |
840 | ||
841 | static void pcic_enable_pil_irq(unsigned int pil) | |
842 | { | |
843 | writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); | |
844 | } | |
845 | ||
846 | void __init sun4m_pci_init_IRQ(void) | |
847 | { | |
848 | BTFIXUPSET_CALL(enable_irq, pcic_enable_irq, BTFIXUPCALL_NORM); | |
849 | BTFIXUPSET_CALL(disable_irq, pcic_disable_irq, BTFIXUPCALL_NORM); | |
850 | BTFIXUPSET_CALL(enable_pil_irq, pcic_enable_pil_irq, BTFIXUPCALL_NORM); | |
851 | BTFIXUPSET_CALL(disable_pil_irq, pcic_disable_pil_irq, BTFIXUPCALL_NORM); | |
852 | BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM); | |
1da177e4 | 853 | BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM); |
1da177e4 LT |
854 | } |
855 | ||
856 | int pcibios_assign_resource(struct pci_dev *pdev, int resource) | |
857 | { | |
858 | return -ENXIO; | |
859 | } | |
860 | ||
f6d0f9ea DM |
861 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
862 | { | |
863 | struct pcidev_cookie *pc = pdev->sysdata; | |
864 | ||
865 | return pc->prom_node; | |
866 | } | |
867 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
868 | ||
1da177e4 LT |
869 | /* |
870 | * This probably belongs here rather than ioport.c because | |
871 | * we do not want this crud linked into SBus kernels. | |
872 | * Also, think for a moment about likes of floppy.c that | |
873 | * include architecture specific parts. They may want to redefine ins/outs. | |
874 | * | |
d1a78c32 | 875 | * We do not use horrible macros here because we want to |
1da177e4 LT |
876 | * advance pointer by sizeof(size). |
877 | */ | |
878 | void outsb(unsigned long addr, const void *src, unsigned long count) | |
879 | { | |
880 | while (count) { | |
881 | count -= 1; | |
882 | outb(*(const char *)src, addr); | |
883 | src += 1; | |
884 | /* addr += 1; */ | |
885 | } | |
886 | } | |
6943f3da | 887 | EXPORT_SYMBOL(outsb); |
1da177e4 LT |
888 | |
889 | void outsw(unsigned long addr, const void *src, unsigned long count) | |
890 | { | |
891 | while (count) { | |
892 | count -= 2; | |
893 | outw(*(const short *)src, addr); | |
894 | src += 2; | |
895 | /* addr += 2; */ | |
896 | } | |
897 | } | |
6943f3da | 898 | EXPORT_SYMBOL(outsw); |
1da177e4 LT |
899 | |
900 | void outsl(unsigned long addr, const void *src, unsigned long count) | |
901 | { | |
902 | while (count) { | |
903 | count -= 4; | |
904 | outl(*(const long *)src, addr); | |
905 | src += 4; | |
906 | /* addr += 4; */ | |
907 | } | |
908 | } | |
6943f3da | 909 | EXPORT_SYMBOL(outsl); |
1da177e4 LT |
910 | |
911 | void insb(unsigned long addr, void *dst, unsigned long count) | |
912 | { | |
913 | while (count) { | |
914 | count -= 1; | |
915 | *(unsigned char *)dst = inb(addr); | |
916 | dst += 1; | |
917 | /* addr += 1; */ | |
918 | } | |
919 | } | |
6943f3da | 920 | EXPORT_SYMBOL(insb); |
1da177e4 LT |
921 | |
922 | void insw(unsigned long addr, void *dst, unsigned long count) | |
923 | { | |
924 | while (count) { | |
925 | count -= 2; | |
926 | *(unsigned short *)dst = inw(addr); | |
927 | dst += 2; | |
928 | /* addr += 2; */ | |
929 | } | |
930 | } | |
6943f3da | 931 | EXPORT_SYMBOL(insw); |
1da177e4 LT |
932 | |
933 | void insl(unsigned long addr, void *dst, unsigned long count) | |
934 | { | |
935 | while (count) { | |
936 | count -= 4; | |
937 | /* | |
938 | * XXX I am sure we are in for an unaligned trap here. | |
939 | */ | |
940 | *(unsigned long *)dst = inl(addr); | |
941 | dst += 4; | |
942 | /* addr += 4; */ | |
943 | } | |
944 | } | |
6943f3da | 945 | EXPORT_SYMBOL(insl); |
1da177e4 LT |
946 | |
947 | subsys_initcall(pcic_init); |