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cdd6c482 | 1 | /* Performance event support for sparc64. |
59abbd1e | 2 | * |
4f6dbe4a | 3 | * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net> |
59abbd1e | 4 | * |
cdd6c482 | 5 | * This code is based almost entirely upon the x86 perf event |
59abbd1e DM |
6 | * code, which is: |
7 | * | |
8 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
9 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
10 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
11 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
12 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
59abbd1e | 16 | #include <linux/kprobes.h> |
667f0cee | 17 | #include <linux/ftrace.h> |
59abbd1e DM |
18 | #include <linux/kernel.h> |
19 | #include <linux/kdebug.h> | |
20 | #include <linux/mutex.h> | |
21 | ||
4f6dbe4a | 22 | #include <asm/stacktrace.h> |
59abbd1e | 23 | #include <asm/cpudata.h> |
4f6dbe4a | 24 | #include <asm/uaccess.h> |
59abbd1e DM |
25 | #include <asm/atomic.h> |
26 | #include <asm/nmi.h> | |
27 | #include <asm/pcr.h> | |
28 | ||
cb1b8209 | 29 | #include "kernel.h" |
4f6dbe4a DM |
30 | #include "kstack.h" |
31 | ||
59abbd1e DM |
32 | /* Sparc64 chips have two performance counters, 32-bits each, with |
33 | * overflow interrupts generated on transition from 0xffffffff to 0. | |
34 | * The counters are accessed in one go using a 64-bit register. | |
35 | * | |
36 | * Both counters are controlled using a single control register. The | |
37 | * only way to stop all sampling is to clear all of the context (user, | |
38 | * supervisor, hypervisor) sampling enable bits. But these bits apply | |
39 | * to both counters, thus the two counters can't be enabled/disabled | |
40 | * individually. | |
41 | * | |
42 | * The control register has two event fields, one for each of the two | |
43 | * counters. It's thus nearly impossible to have one counter going | |
44 | * while keeping the other one stopped. Therefore it is possible to | |
45 | * get overflow interrupts for counters not currently "in use" and | |
46 | * that condition must be checked in the overflow interrupt handler. | |
47 | * | |
48 | * So we use a hack, in that we program inactive counters with the | |
49 | * "sw_count0" and "sw_count1" events. These count how many times | |
50 | * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an | |
51 | * unusual way to encode a NOP and therefore will not trigger in | |
52 | * normal code. | |
53 | */ | |
54 | ||
cdd6c482 | 55 | #define MAX_HWEVENTS 2 |
59abbd1e DM |
56 | #define MAX_PERIOD ((1UL << 32) - 1) |
57 | ||
58 | #define PIC_UPPER_INDEX 0 | |
59 | #define PIC_LOWER_INDEX 1 | |
e7bef6b0 | 60 | #define PIC_NO_INDEX -1 |
59abbd1e | 61 | |
cdd6c482 | 62 | struct cpu_hw_events { |
e7bef6b0 DM |
63 | /* Number of events currently scheduled onto this cpu. |
64 | * This tells how many entries in the arrays below | |
65 | * are valid. | |
66 | */ | |
67 | int n_events; | |
68 | ||
69 | /* Number of new events added since the last hw_perf_disable(). | |
70 | * This works because the perf event layer always adds new | |
71 | * events inside of a perf_{disable,enable}() sequence. | |
72 | */ | |
73 | int n_added; | |
74 | ||
75 | /* Array of events current scheduled on this cpu. */ | |
76 | struct perf_event *event[MAX_HWEVENTS]; | |
77 | ||
78 | /* Array of encoded longs, specifying the %pcr register | |
79 | * encoding and the mask of PIC counters this even can | |
80 | * be scheduled on. See perf_event_encode() et al. | |
81 | */ | |
82 | unsigned long events[MAX_HWEVENTS]; | |
83 | ||
84 | /* The current counter index assigned to an event. When the | |
85 | * event hasn't been programmed into the cpu yet, this will | |
86 | * hold PIC_NO_INDEX. The event->hw.idx value tells us where | |
87 | * we ought to schedule the event. | |
88 | */ | |
89 | int current_idx[MAX_HWEVENTS]; | |
90 | ||
91 | /* Software copy of %pcr register on this cpu. */ | |
d1751388 | 92 | u64 pcr; |
e7bef6b0 DM |
93 | |
94 | /* Enabled/disable state. */ | |
d1751388 | 95 | int enabled; |
a13c3afd LM |
96 | |
97 | unsigned int group_flag; | |
59abbd1e | 98 | }; |
cdd6c482 | 99 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; |
59abbd1e | 100 | |
e7bef6b0 DM |
101 | /* An event map describes the characteristics of a performance |
102 | * counter event. In particular it gives the encoding as well as | |
103 | * a mask telling which counters the event can be measured on. | |
104 | */ | |
59abbd1e DM |
105 | struct perf_event_map { |
106 | u16 encoding; | |
107 | u8 pic_mask; | |
108 | #define PIC_NONE 0x00 | |
109 | #define PIC_UPPER 0x01 | |
110 | #define PIC_LOWER 0x02 | |
111 | }; | |
112 | ||
e7bef6b0 | 113 | /* Encode a perf_event_map entry into a long. */ |
a72a8a5f DM |
114 | static unsigned long perf_event_encode(const struct perf_event_map *pmap) |
115 | { | |
116 | return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask; | |
117 | } | |
118 | ||
e7bef6b0 DM |
119 | static u8 perf_event_get_msk(unsigned long val) |
120 | { | |
121 | return val & 0xff; | |
122 | } | |
123 | ||
124 | static u64 perf_event_get_enc(unsigned long val) | |
a72a8a5f | 125 | { |
e7bef6b0 | 126 | return val >> 16; |
a72a8a5f DM |
127 | } |
128 | ||
2ce4da2e DM |
129 | #define C(x) PERF_COUNT_HW_CACHE_##x |
130 | ||
131 | #define CACHE_OP_UNSUPPORTED 0xfffe | |
132 | #define CACHE_OP_NONSENSE 0xffff | |
133 | ||
134 | typedef struct perf_event_map cache_map_t | |
135 | [PERF_COUNT_HW_CACHE_MAX] | |
136 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
137 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
138 | ||
59abbd1e DM |
139 | struct sparc_pmu { |
140 | const struct perf_event_map *(*event_map)(int); | |
2ce4da2e | 141 | const cache_map_t *cache_map; |
59abbd1e DM |
142 | int max_events; |
143 | int upper_shift; | |
144 | int lower_shift; | |
145 | int event_mask; | |
91b9286d | 146 | int hv_bit; |
496c07e3 | 147 | int irq_bit; |
660d1376 DM |
148 | int upper_nop; |
149 | int lower_nop; | |
59abbd1e DM |
150 | }; |
151 | ||
28e8f9be | 152 | static const struct perf_event_map ultra3_perfmon_event_map[] = { |
59abbd1e DM |
153 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, |
154 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, | |
155 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, | |
156 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, | |
157 | }; | |
158 | ||
28e8f9be | 159 | static const struct perf_event_map *ultra3_event_map(int event_id) |
59abbd1e | 160 | { |
28e8f9be | 161 | return &ultra3_perfmon_event_map[event_id]; |
59abbd1e DM |
162 | } |
163 | ||
28e8f9be | 164 | static const cache_map_t ultra3_cache_map = { |
2ce4da2e DM |
165 | [C(L1D)] = { |
166 | [C(OP_READ)] = { | |
167 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | |
168 | [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, | |
169 | }, | |
170 | [C(OP_WRITE)] = { | |
171 | [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER }, | |
172 | [C(RESULT_MISS)] = { 0x0a, PIC_UPPER }, | |
173 | }, | |
174 | [C(OP_PREFETCH)] = { | |
175 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
176 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
177 | }, | |
178 | }, | |
179 | [C(L1I)] = { | |
180 | [C(OP_READ)] = { | |
181 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | |
182 | [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, | |
183 | }, | |
184 | [ C(OP_WRITE) ] = { | |
185 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
186 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
187 | }, | |
188 | [ C(OP_PREFETCH) ] = { | |
189 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
190 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
191 | }, | |
192 | }, | |
193 | [C(LL)] = { | |
194 | [C(OP_READ)] = { | |
195 | [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, }, | |
196 | [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, }, | |
197 | }, | |
198 | [C(OP_WRITE)] = { | |
199 | [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER }, | |
200 | [C(RESULT_MISS)] = { 0x0c, PIC_UPPER }, | |
201 | }, | |
202 | [C(OP_PREFETCH)] = { | |
203 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
204 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
205 | }, | |
206 | }, | |
207 | [C(DTLB)] = { | |
208 | [C(OP_READ)] = { | |
209 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
210 | [C(RESULT_MISS)] = { 0x12, PIC_UPPER, }, | |
211 | }, | |
212 | [ C(OP_WRITE) ] = { | |
213 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
214 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
215 | }, | |
216 | [ C(OP_PREFETCH) ] = { | |
217 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
218 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
219 | }, | |
220 | }, | |
221 | [C(ITLB)] = { | |
222 | [C(OP_READ)] = { | |
223 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
224 | [C(RESULT_MISS)] = { 0x11, PIC_UPPER, }, | |
225 | }, | |
226 | [ C(OP_WRITE) ] = { | |
227 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
228 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
229 | }, | |
230 | [ C(OP_PREFETCH) ] = { | |
231 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
232 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
233 | }, | |
234 | }, | |
235 | [C(BPU)] = { | |
236 | [C(OP_READ)] = { | |
237 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
238 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
239 | }, | |
240 | [ C(OP_WRITE) ] = { | |
241 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
242 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
243 | }, | |
244 | [ C(OP_PREFETCH) ] = { | |
245 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
246 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
247 | }, | |
248 | }, | |
249 | }; | |
250 | ||
28e8f9be DM |
251 | static const struct sparc_pmu ultra3_pmu = { |
252 | .event_map = ultra3_event_map, | |
253 | .cache_map = &ultra3_cache_map, | |
254 | .max_events = ARRAY_SIZE(ultra3_perfmon_event_map), | |
59abbd1e DM |
255 | .upper_shift = 11, |
256 | .lower_shift = 4, | |
257 | .event_mask = 0x3f, | |
660d1376 DM |
258 | .upper_nop = 0x1c, |
259 | .lower_nop = 0x14, | |
59abbd1e DM |
260 | }; |
261 | ||
7eebda60 DM |
262 | /* Niagara1 is very limited. The upper PIC is hard-locked to count |
263 | * only instructions, so it is free running which creates all kinds of | |
6e804251 | 264 | * problems. Some hardware designs make one wonder if the creator |
7eebda60 DM |
265 | * even looked at how this stuff gets used by software. |
266 | */ | |
267 | static const struct perf_event_map niagara1_perfmon_event_map[] = { | |
268 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER }, | |
269 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER }, | |
270 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE }, | |
271 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER }, | |
272 | }; | |
273 | ||
274 | static const struct perf_event_map *niagara1_event_map(int event_id) | |
275 | { | |
276 | return &niagara1_perfmon_event_map[event_id]; | |
277 | } | |
278 | ||
279 | static const cache_map_t niagara1_cache_map = { | |
280 | [C(L1D)] = { | |
281 | [C(OP_READ)] = { | |
282 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
283 | [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, | |
284 | }, | |
285 | [C(OP_WRITE)] = { | |
286 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
287 | [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, | |
288 | }, | |
289 | [C(OP_PREFETCH)] = { | |
290 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
291 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
292 | }, | |
293 | }, | |
294 | [C(L1I)] = { | |
295 | [C(OP_READ)] = { | |
296 | [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER }, | |
297 | [C(RESULT_MISS)] = { 0x02, PIC_LOWER, }, | |
298 | }, | |
299 | [ C(OP_WRITE) ] = { | |
300 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
301 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
302 | }, | |
303 | [ C(OP_PREFETCH) ] = { | |
304 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
305 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
306 | }, | |
307 | }, | |
308 | [C(LL)] = { | |
309 | [C(OP_READ)] = { | |
310 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
311 | [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, | |
312 | }, | |
313 | [C(OP_WRITE)] = { | |
314 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
315 | [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, | |
316 | }, | |
317 | [C(OP_PREFETCH)] = { | |
318 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
319 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
320 | }, | |
321 | }, | |
322 | [C(DTLB)] = { | |
323 | [C(OP_READ)] = { | |
324 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
325 | [C(RESULT_MISS)] = { 0x05, PIC_LOWER, }, | |
326 | }, | |
327 | [ C(OP_WRITE) ] = { | |
328 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
329 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
330 | }, | |
331 | [ C(OP_PREFETCH) ] = { | |
332 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
333 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
334 | }, | |
335 | }, | |
336 | [C(ITLB)] = { | |
337 | [C(OP_READ)] = { | |
338 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
339 | [C(RESULT_MISS)] = { 0x04, PIC_LOWER, }, | |
340 | }, | |
341 | [ C(OP_WRITE) ] = { | |
342 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
343 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
344 | }, | |
345 | [ C(OP_PREFETCH) ] = { | |
346 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
347 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
348 | }, | |
349 | }, | |
350 | [C(BPU)] = { | |
351 | [C(OP_READ)] = { | |
352 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
353 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
354 | }, | |
355 | [ C(OP_WRITE) ] = { | |
356 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
357 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
358 | }, | |
359 | [ C(OP_PREFETCH) ] = { | |
360 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
361 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
362 | }, | |
363 | }, | |
364 | }; | |
365 | ||
366 | static const struct sparc_pmu niagara1_pmu = { | |
367 | .event_map = niagara1_event_map, | |
368 | .cache_map = &niagara1_cache_map, | |
369 | .max_events = ARRAY_SIZE(niagara1_perfmon_event_map), | |
370 | .upper_shift = 0, | |
371 | .lower_shift = 4, | |
372 | .event_mask = 0x7, | |
373 | .upper_nop = 0x0, | |
374 | .lower_nop = 0x0, | |
375 | }; | |
376 | ||
b73d8847 DM |
377 | static const struct perf_event_map niagara2_perfmon_event_map[] = { |
378 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER }, | |
379 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER }, | |
380 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER }, | |
381 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER }, | |
382 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER }, | |
383 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER }, | |
384 | }; | |
385 | ||
cdd6c482 | 386 | static const struct perf_event_map *niagara2_event_map(int event_id) |
b73d8847 | 387 | { |
cdd6c482 | 388 | return &niagara2_perfmon_event_map[event_id]; |
b73d8847 DM |
389 | } |
390 | ||
d0b86480 DM |
391 | static const cache_map_t niagara2_cache_map = { |
392 | [C(L1D)] = { | |
393 | [C(OP_READ)] = { | |
394 | [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, | |
395 | [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, | |
396 | }, | |
397 | [C(OP_WRITE)] = { | |
398 | [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, | |
399 | [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, | |
400 | }, | |
401 | [C(OP_PREFETCH)] = { | |
402 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
403 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
404 | }, | |
405 | }, | |
406 | [C(L1I)] = { | |
407 | [C(OP_READ)] = { | |
408 | [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, }, | |
409 | [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, }, | |
410 | }, | |
411 | [ C(OP_WRITE) ] = { | |
412 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
413 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
414 | }, | |
415 | [ C(OP_PREFETCH) ] = { | |
416 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
417 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
418 | }, | |
419 | }, | |
420 | [C(LL)] = { | |
421 | [C(OP_READ)] = { | |
422 | [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, | |
423 | [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, }, | |
424 | }, | |
425 | [C(OP_WRITE)] = { | |
426 | [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, | |
427 | [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, }, | |
428 | }, | |
429 | [C(OP_PREFETCH)] = { | |
430 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
431 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
432 | }, | |
433 | }, | |
434 | [C(DTLB)] = { | |
435 | [C(OP_READ)] = { | |
436 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
437 | [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, }, | |
438 | }, | |
439 | [ C(OP_WRITE) ] = { | |
440 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
441 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
442 | }, | |
443 | [ C(OP_PREFETCH) ] = { | |
444 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
445 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
446 | }, | |
447 | }, | |
448 | [C(ITLB)] = { | |
449 | [C(OP_READ)] = { | |
450 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
451 | [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, }, | |
452 | }, | |
453 | [ C(OP_WRITE) ] = { | |
454 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
455 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
456 | }, | |
457 | [ C(OP_PREFETCH) ] = { | |
458 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
459 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
460 | }, | |
461 | }, | |
462 | [C(BPU)] = { | |
463 | [C(OP_READ)] = { | |
464 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
465 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
466 | }, | |
467 | [ C(OP_WRITE) ] = { | |
468 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
469 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
470 | }, | |
471 | [ C(OP_PREFETCH) ] = { | |
472 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
473 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
474 | }, | |
475 | }, | |
476 | }; | |
477 | ||
b73d8847 DM |
478 | static const struct sparc_pmu niagara2_pmu = { |
479 | .event_map = niagara2_event_map, | |
d0b86480 | 480 | .cache_map = &niagara2_cache_map, |
b73d8847 DM |
481 | .max_events = ARRAY_SIZE(niagara2_perfmon_event_map), |
482 | .upper_shift = 19, | |
483 | .lower_shift = 6, | |
484 | .event_mask = 0xfff, | |
485 | .hv_bit = 0x8, | |
de23cf3c | 486 | .irq_bit = 0x30, |
b73d8847 DM |
487 | .upper_nop = 0x220, |
488 | .lower_nop = 0x220, | |
489 | }; | |
490 | ||
59abbd1e DM |
491 | static const struct sparc_pmu *sparc_pmu __read_mostly; |
492 | ||
cdd6c482 | 493 | static u64 event_encoding(u64 event_id, int idx) |
59abbd1e DM |
494 | { |
495 | if (idx == PIC_UPPER_INDEX) | |
cdd6c482 | 496 | event_id <<= sparc_pmu->upper_shift; |
59abbd1e | 497 | else |
cdd6c482 IM |
498 | event_id <<= sparc_pmu->lower_shift; |
499 | return event_id; | |
59abbd1e DM |
500 | } |
501 | ||
502 | static u64 mask_for_index(int idx) | |
503 | { | |
504 | return event_encoding(sparc_pmu->event_mask, idx); | |
505 | } | |
506 | ||
507 | static u64 nop_for_index(int idx) | |
508 | { | |
509 | return event_encoding(idx == PIC_UPPER_INDEX ? | |
660d1376 DM |
510 | sparc_pmu->upper_nop : |
511 | sparc_pmu->lower_nop, idx); | |
59abbd1e DM |
512 | } |
513 | ||
d1751388 | 514 | static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) |
59abbd1e DM |
515 | { |
516 | u64 val, mask = mask_for_index(idx); | |
517 | ||
d1751388 DM |
518 | val = cpuc->pcr; |
519 | val &= ~mask; | |
520 | val |= hwc->config; | |
521 | cpuc->pcr = val; | |
522 | ||
523 | pcr_ops->write(cpuc->pcr); | |
59abbd1e DM |
524 | } |
525 | ||
d1751388 | 526 | static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) |
59abbd1e DM |
527 | { |
528 | u64 mask = mask_for_index(idx); | |
529 | u64 nop = nop_for_index(idx); | |
d1751388 | 530 | u64 val; |
59abbd1e | 531 | |
d1751388 DM |
532 | val = cpuc->pcr; |
533 | val &= ~mask; | |
534 | val |= nop; | |
535 | cpuc->pcr = val; | |
536 | ||
537 | pcr_ops->write(cpuc->pcr); | |
59abbd1e DM |
538 | } |
539 | ||
59abbd1e DM |
540 | static u32 read_pmc(int idx) |
541 | { | |
542 | u64 val; | |
543 | ||
544 | read_pic(val); | |
545 | if (idx == PIC_UPPER_INDEX) | |
546 | val >>= 32; | |
547 | ||
548 | return val & 0xffffffff; | |
549 | } | |
550 | ||
551 | static void write_pmc(int idx, u64 val) | |
552 | { | |
553 | u64 shift, mask, pic; | |
554 | ||
555 | shift = 0; | |
556 | if (idx == PIC_UPPER_INDEX) | |
557 | shift = 32; | |
558 | ||
559 | mask = ((u64) 0xffffffff) << shift; | |
560 | val <<= shift; | |
561 | ||
562 | read_pic(pic); | |
563 | pic &= ~mask; | |
564 | pic |= val; | |
565 | write_pic(pic); | |
566 | } | |
567 | ||
e7bef6b0 DM |
568 | static u64 sparc_perf_event_update(struct perf_event *event, |
569 | struct hw_perf_event *hwc, int idx) | |
570 | { | |
571 | int shift = 64 - 32; | |
572 | u64 prev_raw_count, new_raw_count; | |
573 | s64 delta; | |
574 | ||
575 | again: | |
e7850595 | 576 | prev_raw_count = local64_read(&hwc->prev_count); |
e7bef6b0 DM |
577 | new_raw_count = read_pmc(idx); |
578 | ||
e7850595 | 579 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
e7bef6b0 DM |
580 | new_raw_count) != prev_raw_count) |
581 | goto again; | |
582 | ||
583 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
584 | delta >>= shift; | |
585 | ||
e7850595 PZ |
586 | local64_add(delta, &event->count); |
587 | local64_sub(delta, &hwc->period_left); | |
e7bef6b0 DM |
588 | |
589 | return new_raw_count; | |
590 | } | |
591 | ||
cdd6c482 | 592 | static int sparc_perf_event_set_period(struct perf_event *event, |
d29862f0 | 593 | struct hw_perf_event *hwc, int idx) |
59abbd1e | 594 | { |
e7850595 | 595 | s64 left = local64_read(&hwc->period_left); |
59abbd1e DM |
596 | s64 period = hwc->sample_period; |
597 | int ret = 0; | |
598 | ||
599 | if (unlikely(left <= -period)) { | |
600 | left = period; | |
e7850595 | 601 | local64_set(&hwc->period_left, left); |
59abbd1e DM |
602 | hwc->last_period = period; |
603 | ret = 1; | |
604 | } | |
605 | ||
606 | if (unlikely(left <= 0)) { | |
607 | left += period; | |
e7850595 | 608 | local64_set(&hwc->period_left, left); |
59abbd1e DM |
609 | hwc->last_period = period; |
610 | ret = 1; | |
611 | } | |
612 | if (left > MAX_PERIOD) | |
613 | left = MAX_PERIOD; | |
614 | ||
e7850595 | 615 | local64_set(&hwc->prev_count, (u64)-left); |
59abbd1e DM |
616 | |
617 | write_pmc(idx, (u64)(-left) & 0xffffffff); | |
618 | ||
cdd6c482 | 619 | perf_event_update_userpage(event); |
59abbd1e DM |
620 | |
621 | return ret; | |
622 | } | |
623 | ||
e7bef6b0 DM |
624 | /* If performance event entries have been added, move existing |
625 | * events around (if necessary) and then assign new entries to | |
626 | * counters. | |
627 | */ | |
628 | static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr) | |
59abbd1e | 629 | { |
e7bef6b0 | 630 | int i; |
59abbd1e | 631 | |
e7bef6b0 DM |
632 | if (!cpuc->n_added) |
633 | goto out; | |
59abbd1e | 634 | |
e7bef6b0 DM |
635 | /* Read in the counters which are moving. */ |
636 | for (i = 0; i < cpuc->n_events; i++) { | |
637 | struct perf_event *cp = cpuc->event[i]; | |
59abbd1e | 638 | |
e7bef6b0 DM |
639 | if (cpuc->current_idx[i] != PIC_NO_INDEX && |
640 | cpuc->current_idx[i] != cp->hw.idx) { | |
641 | sparc_perf_event_update(cp, &cp->hw, | |
642 | cpuc->current_idx[i]); | |
643 | cpuc->current_idx[i] = PIC_NO_INDEX; | |
644 | } | |
645 | } | |
59abbd1e | 646 | |
e7bef6b0 DM |
647 | /* Assign to counters all unassigned events. */ |
648 | for (i = 0; i < cpuc->n_events; i++) { | |
649 | struct perf_event *cp = cpuc->event[i]; | |
650 | struct hw_perf_event *hwc = &cp->hw; | |
651 | int idx = hwc->idx; | |
652 | u64 enc; | |
653 | ||
654 | if (cpuc->current_idx[i] != PIC_NO_INDEX) | |
655 | continue; | |
656 | ||
657 | sparc_perf_event_set_period(cp, hwc, idx); | |
658 | cpuc->current_idx[i] = idx; | |
659 | ||
660 | enc = perf_event_get_enc(cpuc->events[i]); | |
b7d45c3f | 661 | pcr &= ~mask_for_index(idx); |
a4eaf7f1 PZ |
662 | if (hwc->state & PERF_HES_STOPPED) |
663 | pcr |= nop_for_index(idx); | |
664 | else | |
665 | pcr |= event_encoding(enc, idx); | |
e7bef6b0 DM |
666 | } |
667 | out: | |
668 | return pcr; | |
59abbd1e DM |
669 | } |
670 | ||
a4eaf7f1 | 671 | static void sparc_pmu_enable(struct pmu *pmu) |
59abbd1e | 672 | { |
e7bef6b0 DM |
673 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
674 | u64 pcr; | |
59abbd1e | 675 | |
e7bef6b0 DM |
676 | if (cpuc->enabled) |
677 | return; | |
59abbd1e | 678 | |
e7bef6b0 DM |
679 | cpuc->enabled = 1; |
680 | barrier(); | |
59abbd1e | 681 | |
e7bef6b0 DM |
682 | pcr = cpuc->pcr; |
683 | if (!cpuc->n_events) { | |
684 | pcr = 0; | |
685 | } else { | |
686 | pcr = maybe_change_configuration(cpuc, pcr); | |
59abbd1e | 687 | |
e7bef6b0 DM |
688 | /* We require that all of the events have the same |
689 | * configuration, so just fetch the settings from the | |
690 | * first entry. | |
691 | */ | |
692 | cpuc->pcr = pcr | cpuc->event[0]->hw.config_base; | |
693 | } | |
59abbd1e | 694 | |
e7bef6b0 DM |
695 | pcr_ops->write(cpuc->pcr); |
696 | } | |
697 | ||
a4eaf7f1 | 698 | static void sparc_pmu_disable(struct pmu *pmu) |
e7bef6b0 DM |
699 | { |
700 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
701 | u64 val; | |
702 | ||
703 | if (!cpuc->enabled) | |
704 | return; | |
705 | ||
706 | cpuc->enabled = 0; | |
707 | cpuc->n_added = 0; | |
708 | ||
709 | val = cpuc->pcr; | |
710 | val &= ~(PCR_UTRACE | PCR_STRACE | | |
711 | sparc_pmu->hv_bit | sparc_pmu->irq_bit); | |
712 | cpuc->pcr = val; | |
713 | ||
714 | pcr_ops->write(cpuc->pcr); | |
59abbd1e DM |
715 | } |
716 | ||
a4eaf7f1 PZ |
717 | static int active_event_index(struct cpu_hw_events *cpuc, |
718 | struct perf_event *event) | |
719 | { | |
720 | int i; | |
721 | ||
722 | for (i = 0; i < cpuc->n_events; i++) { | |
723 | if (cpuc->event[i] == event) | |
724 | break; | |
725 | } | |
726 | BUG_ON(i == cpuc->n_events); | |
727 | return cpuc->current_idx[i]; | |
728 | } | |
729 | ||
730 | static void sparc_pmu_start(struct perf_event *event, int flags) | |
731 | { | |
732 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
733 | int idx = active_event_index(cpuc, event); | |
734 | ||
735 | if (flags & PERF_EF_RELOAD) { | |
736 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
737 | sparc_perf_event_set_period(event, &event->hw, idx); | |
738 | } | |
739 | ||
740 | event->hw.state = 0; | |
741 | ||
742 | sparc_pmu_enable_event(cpuc, &event->hw, idx); | |
743 | } | |
744 | ||
745 | static void sparc_pmu_stop(struct perf_event *event, int flags) | |
746 | { | |
747 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
748 | int idx = active_event_index(cpuc, event); | |
749 | ||
750 | if (!(event->hw.state & PERF_HES_STOPPED)) { | |
751 | sparc_pmu_disable_event(cpuc, &event->hw, idx); | |
752 | event->hw.state |= PERF_HES_STOPPED; | |
753 | } | |
754 | ||
755 | if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) { | |
756 | sparc_perf_event_update(event, &event->hw, idx); | |
757 | event->hw.state |= PERF_HES_UPTODATE; | |
758 | } | |
759 | } | |
760 | ||
761 | static void sparc_pmu_del(struct perf_event *event, int _flags) | |
59abbd1e | 762 | { |
cdd6c482 | 763 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
e7bef6b0 DM |
764 | unsigned long flags; |
765 | int i; | |
59abbd1e | 766 | |
e7bef6b0 | 767 | local_irq_save(flags); |
33696fc0 | 768 | perf_pmu_disable(event->pmu); |
e7bef6b0 DM |
769 | |
770 | for (i = 0; i < cpuc->n_events; i++) { | |
771 | if (event == cpuc->event[i]) { | |
a4eaf7f1 PZ |
772 | /* Absorb the final count and turn off the |
773 | * event. | |
774 | */ | |
775 | sparc_pmu_stop(event, PERF_EF_UPDATE); | |
e7bef6b0 DM |
776 | |
777 | /* Shift remaining entries down into | |
778 | * the existing slot. | |
779 | */ | |
780 | while (++i < cpuc->n_events) { | |
781 | cpuc->event[i - 1] = cpuc->event[i]; | |
782 | cpuc->events[i - 1] = cpuc->events[i]; | |
783 | cpuc->current_idx[i - 1] = | |
784 | cpuc->current_idx[i]; | |
785 | } | |
786 | ||
e7bef6b0 | 787 | perf_event_update_userpage(event); |
59abbd1e | 788 | |
e7bef6b0 DM |
789 | cpuc->n_events--; |
790 | break; | |
791 | } | |
792 | } | |
59abbd1e | 793 | |
33696fc0 | 794 | perf_pmu_enable(event->pmu); |
e7bef6b0 DM |
795 | local_irq_restore(flags); |
796 | } | |
797 | ||
cdd6c482 | 798 | static void sparc_pmu_read(struct perf_event *event) |
59abbd1e | 799 | { |
e7bef6b0 DM |
800 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
801 | int idx = active_event_index(cpuc, event); | |
cdd6c482 | 802 | struct hw_perf_event *hwc = &event->hw; |
d1751388 | 803 | |
e7bef6b0 | 804 | sparc_perf_event_update(event, hwc, idx); |
59abbd1e DM |
805 | } |
806 | ||
cdd6c482 | 807 | static atomic_t active_events = ATOMIC_INIT(0); |
59abbd1e DM |
808 | static DEFINE_MUTEX(pmc_grab_mutex); |
809 | ||
d1751388 DM |
810 | static void perf_stop_nmi_watchdog(void *unused) |
811 | { | |
812 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
813 | ||
814 | stop_nmi_watchdog(NULL); | |
815 | cpuc->pcr = pcr_ops->read(); | |
816 | } | |
817 | ||
cdd6c482 | 818 | void perf_event_grab_pmc(void) |
59abbd1e | 819 | { |
cdd6c482 | 820 | if (atomic_inc_not_zero(&active_events)) |
59abbd1e DM |
821 | return; |
822 | ||
823 | mutex_lock(&pmc_grab_mutex); | |
cdd6c482 | 824 | if (atomic_read(&active_events) == 0) { |
59abbd1e | 825 | if (atomic_read(&nmi_active) > 0) { |
d1751388 | 826 | on_each_cpu(perf_stop_nmi_watchdog, NULL, 1); |
59abbd1e DM |
827 | BUG_ON(atomic_read(&nmi_active) != 0); |
828 | } | |
cdd6c482 | 829 | atomic_inc(&active_events); |
59abbd1e DM |
830 | } |
831 | mutex_unlock(&pmc_grab_mutex); | |
832 | } | |
833 | ||
cdd6c482 | 834 | void perf_event_release_pmc(void) |
59abbd1e | 835 | { |
cdd6c482 | 836 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) { |
59abbd1e DM |
837 | if (atomic_read(&nmi_active) == 0) |
838 | on_each_cpu(start_nmi_watchdog, NULL, 1); | |
839 | mutex_unlock(&pmc_grab_mutex); | |
840 | } | |
841 | } | |
842 | ||
2ce4da2e DM |
843 | static const struct perf_event_map *sparc_map_cache_event(u64 config) |
844 | { | |
845 | unsigned int cache_type, cache_op, cache_result; | |
846 | const struct perf_event_map *pmap; | |
847 | ||
848 | if (!sparc_pmu->cache_map) | |
849 | return ERR_PTR(-ENOENT); | |
850 | ||
851 | cache_type = (config >> 0) & 0xff; | |
852 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
853 | return ERR_PTR(-EINVAL); | |
854 | ||
855 | cache_op = (config >> 8) & 0xff; | |
856 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
857 | return ERR_PTR(-EINVAL); | |
858 | ||
859 | cache_result = (config >> 16) & 0xff; | |
860 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
861 | return ERR_PTR(-EINVAL); | |
862 | ||
863 | pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); | |
864 | ||
865 | if (pmap->encoding == CACHE_OP_UNSUPPORTED) | |
866 | return ERR_PTR(-ENOENT); | |
867 | ||
868 | if (pmap->encoding == CACHE_OP_NONSENSE) | |
869 | return ERR_PTR(-EINVAL); | |
870 | ||
871 | return pmap; | |
872 | } | |
873 | ||
cdd6c482 | 874 | static void hw_perf_event_destroy(struct perf_event *event) |
59abbd1e | 875 | { |
cdd6c482 | 876 | perf_event_release_pmc(); |
59abbd1e DM |
877 | } |
878 | ||
a72a8a5f DM |
879 | /* Make sure all events can be scheduled into the hardware at |
880 | * the same time. This is simplified by the fact that we only | |
881 | * need to support 2 simultaneous HW events. | |
e7bef6b0 DM |
882 | * |
883 | * As a side effect, the evts[]->hw.idx values will be assigned | |
884 | * on success. These are pending indexes. When the events are | |
885 | * actually programmed into the chip, these values will propagate | |
886 | * to the per-cpu cpuc->current_idx[] slots, see the code in | |
887 | * maybe_change_configuration() for details. | |
a72a8a5f | 888 | */ |
e7bef6b0 DM |
889 | static int sparc_check_constraints(struct perf_event **evts, |
890 | unsigned long *events, int n_ev) | |
a72a8a5f | 891 | { |
e7bef6b0 DM |
892 | u8 msk0 = 0, msk1 = 0; |
893 | int idx0 = 0; | |
894 | ||
895 | /* This case is possible when we are invoked from | |
896 | * hw_perf_group_sched_in(). | |
897 | */ | |
898 | if (!n_ev) | |
899 | return 0; | |
900 | ||
15ac9a39 | 901 | if (n_ev > MAX_HWEVENTS) |
e7bef6b0 DM |
902 | return -1; |
903 | ||
904 | msk0 = perf_event_get_msk(events[0]); | |
905 | if (n_ev == 1) { | |
906 | if (msk0 & PIC_LOWER) | |
907 | idx0 = 1; | |
908 | goto success; | |
909 | } | |
910 | BUG_ON(n_ev != 2); | |
911 | msk1 = perf_event_get_msk(events[1]); | |
912 | ||
913 | /* If both events can go on any counter, OK. */ | |
914 | if (msk0 == (PIC_UPPER | PIC_LOWER) && | |
915 | msk1 == (PIC_UPPER | PIC_LOWER)) | |
916 | goto success; | |
917 | ||
918 | /* If one event is limited to a specific counter, | |
919 | * and the other can go on both, OK. | |
920 | */ | |
921 | if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) && | |
922 | msk1 == (PIC_UPPER | PIC_LOWER)) { | |
923 | if (msk0 & PIC_LOWER) | |
924 | idx0 = 1; | |
925 | goto success; | |
a72a8a5f DM |
926 | } |
927 | ||
e7bef6b0 DM |
928 | if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) && |
929 | msk0 == (PIC_UPPER | PIC_LOWER)) { | |
930 | if (msk1 & PIC_UPPER) | |
931 | idx0 = 1; | |
932 | goto success; | |
933 | } | |
934 | ||
935 | /* If the events are fixed to different counters, OK. */ | |
936 | if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) || | |
937 | (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) { | |
938 | if (msk0 & PIC_LOWER) | |
939 | idx0 = 1; | |
940 | goto success; | |
941 | } | |
942 | ||
943 | /* Otherwise, there is a conflict. */ | |
a72a8a5f | 944 | return -1; |
e7bef6b0 DM |
945 | |
946 | success: | |
947 | evts[0]->hw.idx = idx0; | |
948 | if (n_ev == 2) | |
949 | evts[1]->hw.idx = idx0 ^ 1; | |
950 | return 0; | |
a72a8a5f DM |
951 | } |
952 | ||
01552f76 DM |
953 | static int check_excludes(struct perf_event **evts, int n_prev, int n_new) |
954 | { | |
955 | int eu = 0, ek = 0, eh = 0; | |
956 | struct perf_event *event; | |
957 | int i, n, first; | |
958 | ||
959 | n = n_prev + n_new; | |
960 | if (n <= 1) | |
961 | return 0; | |
962 | ||
963 | first = 1; | |
964 | for (i = 0; i < n; i++) { | |
965 | event = evts[i]; | |
966 | if (first) { | |
967 | eu = event->attr.exclude_user; | |
968 | ek = event->attr.exclude_kernel; | |
969 | eh = event->attr.exclude_hv; | |
970 | first = 0; | |
971 | } else if (event->attr.exclude_user != eu || | |
972 | event->attr.exclude_kernel != ek || | |
973 | event->attr.exclude_hv != eh) { | |
974 | return -EAGAIN; | |
975 | } | |
976 | } | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
981 | static int collect_events(struct perf_event *group, int max_count, | |
e7bef6b0 DM |
982 | struct perf_event *evts[], unsigned long *events, |
983 | int *current_idx) | |
01552f76 DM |
984 | { |
985 | struct perf_event *event; | |
986 | int n = 0; | |
987 | ||
988 | if (!is_software_event(group)) { | |
989 | if (n >= max_count) | |
990 | return -1; | |
991 | evts[n] = group; | |
e7bef6b0 DM |
992 | events[n] = group->hw.event_base; |
993 | current_idx[n++] = PIC_NO_INDEX; | |
01552f76 DM |
994 | } |
995 | list_for_each_entry(event, &group->sibling_list, group_entry) { | |
996 | if (!is_software_event(event) && | |
997 | event->state != PERF_EVENT_STATE_OFF) { | |
998 | if (n >= max_count) | |
999 | return -1; | |
1000 | evts[n] = event; | |
e7bef6b0 DM |
1001 | events[n] = event->hw.event_base; |
1002 | current_idx[n++] = PIC_NO_INDEX; | |
01552f76 DM |
1003 | } |
1004 | } | |
1005 | return n; | |
1006 | } | |
1007 | ||
a4eaf7f1 | 1008 | static int sparc_pmu_add(struct perf_event *event, int ef_flags) |
e7bef6b0 DM |
1009 | { |
1010 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1011 | int n0, ret = -EAGAIN; | |
1012 | unsigned long flags; | |
1013 | ||
1014 | local_irq_save(flags); | |
33696fc0 | 1015 | perf_pmu_disable(event->pmu); |
e7bef6b0 DM |
1016 | |
1017 | n0 = cpuc->n_events; | |
15ac9a39 | 1018 | if (n0 >= MAX_HWEVENTS) |
e7bef6b0 DM |
1019 | goto out; |
1020 | ||
1021 | cpuc->event[n0] = event; | |
1022 | cpuc->events[n0] = event->hw.event_base; | |
1023 | cpuc->current_idx[n0] = PIC_NO_INDEX; | |
1024 | ||
a4eaf7f1 PZ |
1025 | event->hw.state = PERF_HES_UPTODATE; |
1026 | if (!(ef_flags & PERF_EF_START)) | |
1027 | event->hw.state |= PERF_HES_STOPPED; | |
1028 | ||
a13c3afd LM |
1029 | /* |
1030 | * If group events scheduling transaction was started, | |
25985edc | 1031 | * skip the schedulability test here, it will be performed |
a13c3afd LM |
1032 | * at commit time(->commit_txn) as a whole |
1033 | */ | |
8d2cacbb | 1034 | if (cpuc->group_flag & PERF_EVENT_TXN) |
a13c3afd LM |
1035 | goto nocheck; |
1036 | ||
e7bef6b0 DM |
1037 | if (check_excludes(cpuc->event, n0, 1)) |
1038 | goto out; | |
1039 | if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) | |
1040 | goto out; | |
1041 | ||
a13c3afd | 1042 | nocheck: |
e7bef6b0 DM |
1043 | cpuc->n_events++; |
1044 | cpuc->n_added++; | |
1045 | ||
1046 | ret = 0; | |
1047 | out: | |
33696fc0 | 1048 | perf_pmu_enable(event->pmu); |
e7bef6b0 DM |
1049 | local_irq_restore(flags); |
1050 | return ret; | |
1051 | } | |
1052 | ||
b0a873eb | 1053 | static int sparc_pmu_event_init(struct perf_event *event) |
59abbd1e | 1054 | { |
cdd6c482 | 1055 | struct perf_event_attr *attr = &event->attr; |
01552f76 | 1056 | struct perf_event *evts[MAX_HWEVENTS]; |
cdd6c482 | 1057 | struct hw_perf_event *hwc = &event->hw; |
a72a8a5f | 1058 | unsigned long events[MAX_HWEVENTS]; |
e7bef6b0 | 1059 | int current_idx_dmy[MAX_HWEVENTS]; |
59abbd1e | 1060 | const struct perf_event_map *pmap; |
01552f76 | 1061 | int n; |
59abbd1e DM |
1062 | |
1063 | if (atomic_read(&nmi_active) < 0) | |
1064 | return -ENODEV; | |
1065 | ||
b0a873eb PZ |
1066 | switch (attr->type) { |
1067 | case PERF_TYPE_HARDWARE: | |
2ce4da2e DM |
1068 | if (attr->config >= sparc_pmu->max_events) |
1069 | return -EINVAL; | |
1070 | pmap = sparc_pmu->event_map(attr->config); | |
b0a873eb PZ |
1071 | break; |
1072 | ||
1073 | case PERF_TYPE_HW_CACHE: | |
2ce4da2e DM |
1074 | pmap = sparc_map_cache_event(attr->config); |
1075 | if (IS_ERR(pmap)) | |
1076 | return PTR_ERR(pmap); | |
b0a873eb PZ |
1077 | break; |
1078 | ||
1079 | case PERF_TYPE_RAW: | |
d0303d71 IM |
1080 | pmap = NULL; |
1081 | break; | |
59abbd1e | 1082 | |
b0a873eb PZ |
1083 | default: |
1084 | return -ENOENT; | |
1085 | ||
1086 | } | |
1087 | ||
b343ae51 DM |
1088 | if (pmap) { |
1089 | hwc->event_base = perf_event_encode(pmap); | |
1090 | } else { | |
d0303d71 IM |
1091 | /* |
1092 | * User gives us "(encoding << 16) | pic_mask" for | |
b343ae51 DM |
1093 | * PERF_TYPE_RAW events. |
1094 | */ | |
1095 | hwc->event_base = attr->config; | |
1096 | } | |
1097 | ||
e7bef6b0 | 1098 | /* We save the enable bits in the config_base. */ |
496c07e3 | 1099 | hwc->config_base = sparc_pmu->irq_bit; |
59abbd1e DM |
1100 | if (!attr->exclude_user) |
1101 | hwc->config_base |= PCR_UTRACE; | |
1102 | if (!attr->exclude_kernel) | |
1103 | hwc->config_base |= PCR_STRACE; | |
91b9286d DM |
1104 | if (!attr->exclude_hv) |
1105 | hwc->config_base |= sparc_pmu->hv_bit; | |
59abbd1e | 1106 | |
01552f76 DM |
1107 | n = 0; |
1108 | if (event->group_leader != event) { | |
1109 | n = collect_events(event->group_leader, | |
15ac9a39 | 1110 | MAX_HWEVENTS - 1, |
e7bef6b0 | 1111 | evts, events, current_idx_dmy); |
01552f76 DM |
1112 | if (n < 0) |
1113 | return -EINVAL; | |
1114 | } | |
a72a8a5f | 1115 | events[n] = hwc->event_base; |
01552f76 DM |
1116 | evts[n] = event; |
1117 | ||
1118 | if (check_excludes(evts, n, 1)) | |
1119 | return -EINVAL; | |
1120 | ||
e7bef6b0 | 1121 | if (sparc_check_constraints(evts, events, n + 1)) |
a72a8a5f DM |
1122 | return -EINVAL; |
1123 | ||
e7bef6b0 DM |
1124 | hwc->idx = PIC_NO_INDEX; |
1125 | ||
01552f76 DM |
1126 | /* Try to do all error checking before this point, as unwinding |
1127 | * state after grabbing the PMC is difficult. | |
1128 | */ | |
1129 | perf_event_grab_pmc(); | |
1130 | event->destroy = hw_perf_event_destroy; | |
1131 | ||
59abbd1e DM |
1132 | if (!hwc->sample_period) { |
1133 | hwc->sample_period = MAX_PERIOD; | |
1134 | hwc->last_period = hwc->sample_period; | |
e7850595 | 1135 | local64_set(&hwc->period_left, hwc->sample_period); |
59abbd1e DM |
1136 | } |
1137 | ||
59abbd1e DM |
1138 | return 0; |
1139 | } | |
1140 | ||
a13c3afd LM |
1141 | /* |
1142 | * Start group events scheduling transaction | |
1143 | * Set the flag to make pmu::enable() not perform the | |
1144 | * schedulability test, it will be performed at commit time | |
1145 | */ | |
51b0fe39 | 1146 | static void sparc_pmu_start_txn(struct pmu *pmu) |
a13c3afd LM |
1147 | { |
1148 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1149 | ||
33696fc0 | 1150 | perf_pmu_disable(pmu); |
8d2cacbb | 1151 | cpuhw->group_flag |= PERF_EVENT_TXN; |
a13c3afd LM |
1152 | } |
1153 | ||
1154 | /* | |
1155 | * Stop group events scheduling transaction | |
1156 | * Clear the flag and pmu::enable() will perform the | |
1157 | * schedulability test. | |
1158 | */ | |
51b0fe39 | 1159 | static void sparc_pmu_cancel_txn(struct pmu *pmu) |
a13c3afd LM |
1160 | { |
1161 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1162 | ||
8d2cacbb | 1163 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1164 | perf_pmu_enable(pmu); |
a13c3afd LM |
1165 | } |
1166 | ||
1167 | /* | |
1168 | * Commit group events scheduling transaction | |
1169 | * Perform the group schedulability test as a whole | |
1170 | * Return 0 if success | |
1171 | */ | |
51b0fe39 | 1172 | static int sparc_pmu_commit_txn(struct pmu *pmu) |
a13c3afd LM |
1173 | { |
1174 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1175 | int n; | |
1176 | ||
1177 | if (!sparc_pmu) | |
1178 | return -EINVAL; | |
1179 | ||
1180 | cpuc = &__get_cpu_var(cpu_hw_events); | |
1181 | n = cpuc->n_events; | |
1182 | if (check_excludes(cpuc->event, 0, n)) | |
1183 | return -EINVAL; | |
1184 | if (sparc_check_constraints(cpuc->event, cpuc->events, n)) | |
1185 | return -EAGAIN; | |
1186 | ||
8d2cacbb | 1187 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1188 | perf_pmu_enable(pmu); |
a13c3afd LM |
1189 | return 0; |
1190 | } | |
1191 | ||
51b0fe39 | 1192 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1193 | .pmu_enable = sparc_pmu_enable, |
1194 | .pmu_disable = sparc_pmu_disable, | |
b0a873eb | 1195 | .event_init = sparc_pmu_event_init, |
a4eaf7f1 PZ |
1196 | .add = sparc_pmu_add, |
1197 | .del = sparc_pmu_del, | |
1198 | .start = sparc_pmu_start, | |
1199 | .stop = sparc_pmu_stop, | |
59abbd1e | 1200 | .read = sparc_pmu_read, |
a13c3afd LM |
1201 | .start_txn = sparc_pmu_start_txn, |
1202 | .cancel_txn = sparc_pmu_cancel_txn, | |
1203 | .commit_txn = sparc_pmu_commit_txn, | |
59abbd1e DM |
1204 | }; |
1205 | ||
cdd6c482 | 1206 | void perf_event_print_debug(void) |
59abbd1e DM |
1207 | { |
1208 | unsigned long flags; | |
1209 | u64 pcr, pic; | |
1210 | int cpu; | |
1211 | ||
1212 | if (!sparc_pmu) | |
1213 | return; | |
1214 | ||
1215 | local_irq_save(flags); | |
1216 | ||
1217 | cpu = smp_processor_id(); | |
1218 | ||
1219 | pcr = pcr_ops->read(); | |
1220 | read_pic(pic); | |
1221 | ||
1222 | pr_info("\n"); | |
1223 | pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n", | |
1224 | cpu, pcr, pic); | |
1225 | ||
1226 | local_irq_restore(flags); | |
1227 | } | |
1228 | ||
cdd6c482 | 1229 | static int __kprobes perf_event_nmi_handler(struct notifier_block *self, |
d29862f0 | 1230 | unsigned long cmd, void *__args) |
59abbd1e DM |
1231 | { |
1232 | struct die_args *args = __args; | |
1233 | struct perf_sample_data data; | |
cdd6c482 | 1234 | struct cpu_hw_events *cpuc; |
59abbd1e | 1235 | struct pt_regs *regs; |
e7bef6b0 | 1236 | int i; |
59abbd1e | 1237 | |
cdd6c482 | 1238 | if (!atomic_read(&active_events)) |
59abbd1e DM |
1239 | return NOTIFY_DONE; |
1240 | ||
1241 | switch (cmd) { | |
1242 | case DIE_NMI: | |
1243 | break; | |
1244 | ||
1245 | default: | |
1246 | return NOTIFY_DONE; | |
1247 | } | |
1248 | ||
1249 | regs = args->regs; | |
1250 | ||
dc1d628a | 1251 | perf_sample_data_init(&data, 0); |
59abbd1e | 1252 | |
cdd6c482 | 1253 | cpuc = &__get_cpu_var(cpu_hw_events); |
e04ed38d DM |
1254 | |
1255 | /* If the PMU has the TOE IRQ enable bits, we need to do a | |
1256 | * dummy write to the %pcr to clear the overflow bits and thus | |
1257 | * the interrupt. | |
1258 | * | |
1259 | * Do this before we peek at the counters to determine | |
1260 | * overflow so we don't lose any events. | |
1261 | */ | |
1262 | if (sparc_pmu->irq_bit) | |
1263 | pcr_ops->write(cpuc->pcr); | |
1264 | ||
e7bef6b0 DM |
1265 | for (i = 0; i < cpuc->n_events; i++) { |
1266 | struct perf_event *event = cpuc->event[i]; | |
1267 | int idx = cpuc->current_idx[i]; | |
cdd6c482 | 1268 | struct hw_perf_event *hwc; |
59abbd1e DM |
1269 | u64 val; |
1270 | ||
cdd6c482 IM |
1271 | hwc = &event->hw; |
1272 | val = sparc_perf_event_update(event, hwc, idx); | |
59abbd1e DM |
1273 | if (val & (1ULL << 31)) |
1274 | continue; | |
1275 | ||
cdd6c482 IM |
1276 | data.period = event->hw.last_period; |
1277 | if (!sparc_perf_event_set_period(event, hwc, idx)) | |
59abbd1e DM |
1278 | continue; |
1279 | ||
a8b0ca17 | 1280 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1281 | sparc_pmu_stop(event, 0); |
59abbd1e DM |
1282 | } |
1283 | ||
1284 | return NOTIFY_STOP; | |
1285 | } | |
1286 | ||
cdd6c482 IM |
1287 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1288 | .notifier_call = perf_event_nmi_handler, | |
59abbd1e DM |
1289 | }; |
1290 | ||
1291 | static bool __init supported_pmu(void) | |
1292 | { | |
28e8f9be DM |
1293 | if (!strcmp(sparc_pmu_type, "ultra3") || |
1294 | !strcmp(sparc_pmu_type, "ultra3+") || | |
1295 | !strcmp(sparc_pmu_type, "ultra3i") || | |
1296 | !strcmp(sparc_pmu_type, "ultra4+")) { | |
1297 | sparc_pmu = &ultra3_pmu; | |
59abbd1e DM |
1298 | return true; |
1299 | } | |
7eebda60 DM |
1300 | if (!strcmp(sparc_pmu_type, "niagara")) { |
1301 | sparc_pmu = &niagara1_pmu; | |
1302 | return true; | |
1303 | } | |
b73d8847 DM |
1304 | if (!strcmp(sparc_pmu_type, "niagara2")) { |
1305 | sparc_pmu = &niagara2_pmu; | |
1306 | return true; | |
1307 | } | |
59abbd1e DM |
1308 | return false; |
1309 | } | |
1310 | ||
004417a6 | 1311 | int __init init_hw_perf_events(void) |
59abbd1e | 1312 | { |
cdd6c482 | 1313 | pr_info("Performance events: "); |
59abbd1e DM |
1314 | |
1315 | if (!supported_pmu()) { | |
1316 | pr_cont("No support for PMU type '%s'\n", sparc_pmu_type); | |
004417a6 | 1317 | return 0; |
59abbd1e DM |
1318 | } |
1319 | ||
1320 | pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); | |
1321 | ||
2e80a82a | 1322 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
cdd6c482 | 1323 | register_die_notifier(&perf_event_nmi_notifier); |
004417a6 PZ |
1324 | |
1325 | return 0; | |
59abbd1e | 1326 | } |
efc70d24 | 1327 | early_initcall(init_hw_perf_events); |
4f6dbe4a | 1328 | |
56962b44 FW |
1329 | void perf_callchain_kernel(struct perf_callchain_entry *entry, |
1330 | struct pt_regs *regs) | |
4f6dbe4a DM |
1331 | { |
1332 | unsigned long ksp, fp; | |
667f0cee DM |
1333 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1334 | int graph = 0; | |
1335 | #endif | |
4f6dbe4a | 1336 | |
56962b44 FW |
1337 | stack_trace_flush(); |
1338 | ||
70791ce9 | 1339 | perf_callchain_store(entry, regs->tpc); |
4f6dbe4a DM |
1340 | |
1341 | ksp = regs->u_regs[UREG_I6]; | |
1342 | fp = ksp + STACK_BIAS; | |
1343 | do { | |
1344 | struct sparc_stackf *sf; | |
1345 | struct pt_regs *regs; | |
1346 | unsigned long pc; | |
1347 | ||
1348 | if (!kstack_valid(current_thread_info(), fp)) | |
1349 | break; | |
1350 | ||
1351 | sf = (struct sparc_stackf *) fp; | |
1352 | regs = (struct pt_regs *) (sf + 1); | |
1353 | ||
1354 | if (kstack_is_trap_frame(current_thread_info(), regs)) { | |
1355 | if (user_mode(regs)) | |
1356 | break; | |
1357 | pc = regs->tpc; | |
1358 | fp = regs->u_regs[UREG_I6] + STACK_BIAS; | |
1359 | } else { | |
1360 | pc = sf->callers_pc; | |
1361 | fp = (unsigned long)sf->fp + STACK_BIAS; | |
1362 | } | |
70791ce9 | 1363 | perf_callchain_store(entry, pc); |
667f0cee DM |
1364 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1365 | if ((pc + 8UL) == (unsigned long) &return_to_handler) { | |
1366 | int index = current->curr_ret_stack; | |
1367 | if (current->ret_stack && index >= graph) { | |
1368 | pc = current->ret_stack[index - graph].ret; | |
70791ce9 | 1369 | perf_callchain_store(entry, pc); |
667f0cee DM |
1370 | graph++; |
1371 | } | |
1372 | } | |
1373 | #endif | |
4f6dbe4a DM |
1374 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1375 | } | |
1376 | ||
56962b44 FW |
1377 | static void perf_callchain_user_64(struct perf_callchain_entry *entry, |
1378 | struct pt_regs *regs) | |
4f6dbe4a DM |
1379 | { |
1380 | unsigned long ufp; | |
1381 | ||
70791ce9 | 1382 | perf_callchain_store(entry, regs->tpc); |
4f6dbe4a DM |
1383 | |
1384 | ufp = regs->u_regs[UREG_I6] + STACK_BIAS; | |
1385 | do { | |
1386 | struct sparc_stackf *usf, sf; | |
1387 | unsigned long pc; | |
1388 | ||
1389 | usf = (struct sparc_stackf *) ufp; | |
1390 | if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) | |
1391 | break; | |
1392 | ||
1393 | pc = sf.callers_pc; | |
1394 | ufp = (unsigned long)sf.fp + STACK_BIAS; | |
70791ce9 | 1395 | perf_callchain_store(entry, pc); |
4f6dbe4a DM |
1396 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1397 | } | |
1398 | ||
56962b44 FW |
1399 | static void perf_callchain_user_32(struct perf_callchain_entry *entry, |
1400 | struct pt_regs *regs) | |
4f6dbe4a DM |
1401 | { |
1402 | unsigned long ufp; | |
1403 | ||
70791ce9 | 1404 | perf_callchain_store(entry, regs->tpc); |
4f6dbe4a | 1405 | |
9e8307ec | 1406 | ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; |
4f6dbe4a DM |
1407 | do { |
1408 | struct sparc_stackf32 *usf, sf; | |
1409 | unsigned long pc; | |
1410 | ||
1411 | usf = (struct sparc_stackf32 *) ufp; | |
1412 | if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) | |
1413 | break; | |
1414 | ||
1415 | pc = sf.callers_pc; | |
1416 | ufp = (unsigned long)sf.fp; | |
70791ce9 | 1417 | perf_callchain_store(entry, pc); |
4f6dbe4a DM |
1418 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1419 | } | |
1420 | ||
56962b44 FW |
1421 | void |
1422 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
4f6dbe4a | 1423 | { |
56962b44 FW |
1424 | flushw_user(); |
1425 | if (test_thread_flag(TIF_32BIT)) | |
1426 | perf_callchain_user_32(entry, regs); | |
1427 | else | |
1428 | perf_callchain_user_64(entry, regs); | |
4f6dbe4a | 1429 | } |