[deliverable/linux.git] / arch / sparc / kernel / rtrap_64.S

/*
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#define		RTRAP_PSTATE		(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
#define		RTRAP_PSTATE_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
#define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)

		.text
		.align			32
__handle_softirq:
		call			do_softirq
		 nop
		ba,a,pt			%xcc, __handle_softirq_continue
		 nop
__handle_preemption:
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		/* Redo sched+sig checks */
		ldx			[%g6 + TI_FLAGS], %l0
		andcc			%l0, _TIF_NEED_RESCHED, %g0

		be,pt			%xcc, 1f
		 nop
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0

1:		andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		be,pt			%xcc, __handle_user_windows_continue
		 nop
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2

		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_user_windows_continue

		 andn			%l1, %l4, %l1
__handle_perfctrs:
		call			update_perfctrs
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldub			[%g6 + TI_WSAVED], %o2
		brz,pt			%o2, 1f
		 nop
		/* Redo userwin+sched+sig checks */
		call			fault_in_user_windows

		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, 1f

		 nop
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		ldx			[%g6 + TI_FLAGS], %l0
1:		andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0

		be,pt			%xcc, __handle_perfctrs_continue
		 sethi			%hi(TSTATE_PEF), %o0
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume

		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		ba,pt			%xcc, __handle_perfctrs_continue

		 sethi			%hi(TSTATE_PEF), %o0
__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_signal_continue
		 andn			%l1, %l4, %l1

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
		 */
		.globl			rtrap_nmi
rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
		ba,pt			%xcc, rtrap_no_irq_enable
		 wrpr			%l4, %pil

		.align			64
		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap:
#ifndef CONFIG_SMP
		sethi			%hi(per_cpu____cpu_data), %l0
		lduw			[%l0 + %lo(per_cpu____cpu_data)], %l1
#else
		sethi			%hi(per_cpu____cpu_data), %l0
		or			%l0, %lo(per_cpu____cpu_data), %l0
		lduw			[%l0 + %g5], %l1
#endif
		cmp			%l1, 0

		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		bne,pn			%icc, __handle_softirq
		 ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
__handle_softirq_continue:
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		wrpr			%l4, %pil
#endif
rtrap_no_irq_enable:
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with performance
		 * counters or user windows, we have to redo all of these
		 * sched+signal checks with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		bne,pn			%xcc, __handle_signal
__handle_signal_continue:
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
__handle_user_windows_continue:
		ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_PERFCTR, %g0
		sethi			%hi(TSTATE_PEF), %o0
		bne,pn			%xcc, __handle_perfctrs
__handle_perfctrs_continue:
		 andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		andn			%l1, TSTATE_SYSCALL, %l1
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup:
		rdpr	%cwp, %g1
		add	%g1, 1, %g1
		wrpr	%g1, 0x0, %cwp

		rdpr	%wstate, %g2
		sll	%g2, 3, %g2
		wrpr	%g2, 0x0, %wstate

		/* We know %canrestore and %otherwin are both zero.  */

		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g2
		mov	PRIMARY_CONTEXT, %g1

661:		stxa	%g2, [%g1] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g2, [%g1] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %g1
		flush	%g1

		or	%g4, FAULT_CODE_WINFIXUP, %g4
		stb	%g4, [%g6 + TI_FAULT_CODE]
		stx	%g5, [%g6 + TI_FAULT_ADDR]

		mov	%g6, %l1
		wrpr	%g0, 0x0, %tl

661:		nop
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(0)
		.previous

		wrpr	%g0, RTRAP_PSTATE, %pstate

		mov	%l1, %g6
		ldx	[%g6 + TI_TASK], %g4
		LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
		call	do_sparc64_fault
		 add	%sp, PTREGS_OFF, %o0
		ba,pt	%xcc, rtrap
		 nop

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 sethi			%hi(PREEMPT_ACTIVE), %l6
		stw			%l6, [%g6 + TI_PRE_COUNT]
		call			schedule
		 nop
		ba,pt			%xcc, rtrap
		 stw			%g0, [%g6 + TI_PRE_COUNT]
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/spitfire.h>
	13	#include <asm/head.h>
	14	#include <asm/visasm.h>
	15	#include <asm/processor.h>
	16
64f2dde3 DM	17	#define RTRAP_PSTATE (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_IE)
	18	#define RTRAP_PSTATE_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV)
	19	#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_AG)
1da177e4	20
1da177e4 LT	21	.text
	22	.align 32
	23	__handle_softirq:
	24	call do_softirq
	25	nop
	26	ba,a,pt %xcc, __handle_softirq_continue
	27	nop
	28	__handle_preemption:
	29	call schedule
	30	wrpr %g0, RTRAP_PSTATE, %pstate
	31	ba,pt %xcc, __handle_preemption_continue
	32	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	33
	34	__handle_user_windows:
	35	call fault_in_user_windows
	36	wrpr %g0, RTRAP_PSTATE, %pstate
	37	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	38	/* Redo sched+sig checks */
	39	ldx [%g6 + TI_FLAGS], %l0
	40	andcc %l0, _TIF_NEED_RESCHED, %g0
	41
	42	be,pt %xcc, 1f
	43	nop
	44	call schedule
	45	wrpr %g0, RTRAP_PSTATE, %pstate
	46	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	47	ldx [%g6 + TI_FLAGS], %l0
	48
e35a8925	49	1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4 LT	50	be,pt %xcc, __handle_user_windows_continue
1da177e4 LT	51	nop
2d7d5f05	52	mov %l5, %o1
2d7d5f05	53	add %sp, PTREGS_OFF, %o0
7697daaa	54	mov %l0, %o2
1da177e4 LT	55
	56	call do_notify_resume
	57	wrpr %g0, RTRAP_PSTATE, %pstate
	58	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	59	/* Signal delivery can modify pt_regs tstate, so we must
	60	* reload it.
	61	*/
	62	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	63	sethi %hi(0xf << 20), %l4
	64	and %l1, %l4, %l4
	65	ba,pt %xcc, __handle_user_windows_continue
	66
	67	andn %l1, %l4, %l1
	68	__handle_perfctrs:
	69	call update_perfctrs
	70	wrpr %g0, RTRAP_PSTATE, %pstate
	71	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	72	ldub [%g6 + TI_WSAVED], %o2
	73	brz,pt %o2, 1f
	74	nop
	75	/* Redo userwin+sched+sig checks */
	76	call fault_in_user_windows
	77
	78	wrpr %g0, RTRAP_PSTATE, %pstate
	79	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	80	ldx [%g6 + TI_FLAGS], %l0
	81	andcc %l0, _TIF_NEED_RESCHED, %g0
	82	be,pt %xcc, 1f
	83
	84	nop
	85	call schedule
	86	wrpr %g0, RTRAP_PSTATE, %pstate
	87	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	88	ldx [%g6 + TI_FLAGS], %l0
e35a8925	89	1: andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4 LT	90
	91	be,pt %xcc, __handle_perfctrs_continue
	92	sethi %hi(TSTATE_PEF), %o0
2d7d5f05	93	mov %l5, %o1
2d7d5f05	94	add %sp, PTREGS_OFF, %o0
7697daaa	95	mov %l0, %o2
1da177e4 LT	96	call do_notify_resume
	97
	98	wrpr %g0, RTRAP_PSTATE, %pstate
	99	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	100	/* Signal delivery can modify pt_regs tstate, so we must
	101	* reload it.
	102	*/
	103	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	104	sethi %hi(0xf << 20), %l4
	105	and %l1, %l4, %l4
	106	andn %l1, %l4, %l1
	107	ba,pt %xcc, __handle_perfctrs_continue
	108
	109	sethi %hi(TSTATE_PEF), %o0
	110	__handle_userfpu:
	111	rd %fprs, %l5
	112	andcc %l5, FPRS_FEF, %g0
	113	sethi %hi(TSTATE_PEF), %o0
	114	be,a,pn %icc, __handle_userfpu_continue
	115	andn %l1, %o0, %l1
	116	ba,a,pt %xcc, __handle_userfpu_continue
	117
	118	__handle_signal:
2d7d5f05	119	mov %l5, %o1
2d7d5f05	120	add %sp, PTREGS_OFF, %o0
7697daaa	121	mov %l0, %o2
1da177e4 LT	122	call do_notify_resume
	123	wrpr %g0, RTRAP_PSTATE, %pstate
	124	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	125
	126	/* Signal delivery can modify pt_regs tstate, so we must
	127	* reload it.
	128	*/
	129	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	130	sethi %hi(0xf << 20), %l4
	131	and %l1, %l4, %l4
	132	ba,pt %xcc, __handle_signal_continue
	133	andn %l1, %l4, %l1
	134
5565736e DM	135	/* When returning from a NMI (%pil==15) interrupt we want to
	136	* avoid running softirqs, doing IRQ tracing, preempting, etc.
	137	*/
	138	.globl rtrap_nmi
	139	rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	140	sethi %hi(0xf << 20), %l4
	141	and %l1, %l4, %l4
	142	andn %l1, %l4, %l1
	143	srl %l4, 20, %l4
	144	ba,pt %xcc, rtrap_no_irq_enable
	145	wrpr %l4, %pil
	146
1da177e4	147	.align 64
7697daaa	148	.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4	149	rtrap_irq:
1da177e4	150	rtrap:
d7ce78fd DM	151	#ifndef CONFIG_SMP
	152	sethi %hi(per_cpu____cpu_data), %l0
	153	lduw [%l0 + %lo(per_cpu____cpu_data)], %l1
	154	#else
	155	sethi %hi(per_cpu____cpu_data), %l0
	156	or %l0, %lo(per_cpu____cpu_data), %l0
	157	lduw [%l0 + %g5], %l1
	158	#endif
1da177e4 LT	159	cmp %l1, 0
	160
	161	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
	162	bne,pn %icc, __handle_softirq
	163	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	164	__handle_softirq_continue:
	165	rtrap_xcall:
	166	sethi %hi(0xf << 20), %l4
1da177e4	167	and %l1, %l4, %l4
10e26723 DM	168	andn %l1, %l4, %l1
	169	srl %l4, 20, %l4
	170	#ifdef CONFIG_TRACE_IRQFLAGS
	171	brnz,pn %l4, rtrap_no_irq_enable
	172	nop
	173	call trace_hardirqs_on
	174	nop
	175	wrpr %l4, %pil
10e26723	176	#endif
5565736e	177	rtrap_no_irq_enable:
10e26723	178	andcc %l1, TSTATE_PRIV, %l3
1da177e4	179	bne,pn %icc, to_kernel
10e26723	180	nop
1da177e4 LT	181
	182	/* We must hold IRQs off and atomically test schedule+signal
	183	* state, then hold them off all the way back to userspace.
10e26723 DM	184	* If we are returning to kernel, none of this matters. Note
	185	* that we are disabling interrupts via PSTATE_IE, not using
	186	* %pil.
1da177e4 LT	187	*
	188	* If we do not do this, there is a window where we would do
	189	* the tests, later the signal/resched event arrives but we do
	190	* not process it since we are still in kernel mode. It would
	191	* take until the next local IRQ before the signal/resched
	192	* event would be handled.
	193	*
	194	* This also means that if we have to deal with performance
	195	* counters or user windows, we have to redo all of these
	196	* sched+signal checks with IRQs disabled.
	197	*/
	198	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	199	wrpr 0, %pil
	200	__handle_preemption_continue:
	201	ldx [%g6 + TI_FLAGS], %l0
	202	sethi %hi(_TIF_USER_WORK_MASK), %o0
	203	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	204	andcc %l0, %o0, %g0
	205	sethi %hi(TSTATE_PEF), %o0
	206	be,pt %xcc, user_nowork
	207	andcc %l1, %o0, %g0
	208	andcc %l0, _TIF_NEED_RESCHED, %g0
	209	bne,pn %xcc, __handle_preemption
e35a8925	210	andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4 LT	211	bne,pn %xcc, __handle_signal
	212	__handle_signal_continue:
	213	ldub [%g6 + TI_WSAVED], %o2
	214	brnz,pn %o2, __handle_user_windows
	215	nop
	216	__handle_user_windows_continue:
	217	ldx [%g6 + TI_FLAGS], %l5
	218	andcc %l5, _TIF_PERFCTR, %g0
	219	sethi %hi(TSTATE_PEF), %o0
	220	bne,pn %xcc, __handle_perfctrs
	221	__handle_perfctrs_continue:
	222	andcc %l1, %o0, %g0
	223
	224	/* This fpdepth clear is necessary for non-syscall rtraps only */
	225	user_nowork:
	226	bne,pn %xcc, __handle_userfpu
	227	stb %g0, [%g6 + TI_FPDEPTH]
	228	__handle_userfpu_continue:
	229
	230	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	231	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	232
	233	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	234	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	235	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	236	brz,pt %l3, 1f
314981ac DM	237	mov %g6, %l2
314981ac DM	238
56fb4df6	239	/* Must do this before thread reg is clobbered below. */
ffe483d5	240	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	241	1:
74bf4312 DM	242	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	243	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	244
	245	/* Normal globals are restored, go to trap globals. */
	246	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	247	nop
af02bec6 DM	248	.section .sun4v_2insn_patch, "ax"
936f482a	249	.word 661b
af02bec6	250	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	251	SET_GL(1)
	252	.previous
	253
314981ac DM	254	mov %l2, %g6
314981ac DM	255
1da177e4 LT	256	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	257	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	258
	259	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	260	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	261	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	262	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	263	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	264	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	265	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	266	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	267
	268	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	269	wr %o3, %g0, %y
1da177e4 LT	270	wrpr %l4, 0x0, %pil
1da177e4 LT	271	wrpr %g0, 0x1, %tl
28e61036	272	andn %l1, TSTATE_SYSCALL, %l1
1da177e4 LT	273	wrpr %l1, %g0, %tstate
	274	wrpr %l2, %g0, %tpc
	275	wrpr %o2, %g0, %tnpc
	276
	277	brnz,pn %l3, kern_rtt
	278	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	279
	280	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	281	.section .sun4v_1insn_patch, "ax"
	282	.word 661b
	283	ldxa [%l7 + %l7] ASI_MMU, %l0
	284	.previous
	285
0835ae0f DM	286	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	287	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	288	or %l0, %l1, %l0
8b11bd12 DM	289
	290	661: stxa %l0, [%l7] ASI_DMMU
	291	.section .sun4v_1insn_patch, "ax"
	292	.word 661b
	293	stxa %l0, [%l7] ASI_MMU
	294	.previous
	295
4da808c3 DM	296	sethi %hi(KERNBASE), %l7
4da808c3 DM	297	flush %l7
1da177e4 LT	298	rdpr %wstate, %l1
	299	rdpr %otherwin, %l2
	300	srl %l1, 3, %l1
	301
	302	wrpr %l2, %g0, %canrestore
	303	wrpr %l1, %g0, %wstate
314ef685 DM	304	brnz,pt %l2, user_rtt_restore
	305	wrpr %g0, %g0, %otherwin
	306
	307	ldx [%g6 + TI_FLAGS], %g3
	308	wr %g0, ASI_AIUP, %asi
	309	rdpr %cwp, %g1
	310	andcc %g3, _TIF_32BIT, %g0
	311	sub %g1, 1, %g1
	312	bne,pt %xcc, user_rtt_fill_32bit
	313	wrpr %g1, %cwp
	314	ba,a,pt %xcc, user_rtt_fill_64bit
	315
	316	user_rtt_fill_fixup:
	317	rdpr %cwp, %g1
	318	add %g1, 1, %g1
	319	wrpr %g1, 0x0, %cwp
	320
	321	rdpr %wstate, %g2
	322	sll %g2, 3, %g2
	323	wrpr %g2, 0x0, %wstate
	324
	325	/* We know %canrestore and %otherwin are both zero. */
	326
	327	sethi %hi(sparc64_kern_pri_context), %g2
	328	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
	329	mov PRIMARY_CONTEXT, %g1
8b11bd12 DM	330
	331	661: stxa %g2, [%g1] ASI_DMMU
	332	.section .sun4v_1insn_patch, "ax"
	333	.word 661b
	334	stxa %g2, [%g1] ASI_MMU
	335	.previous
	336
314ef685 DM	337	sethi %hi(KERNBASE), %g1
	338	flush %g1
	339
	340	or %g4, FAULT_CODE_WINFIXUP, %g4
	341	stb %g4, [%g6 + TI_FAULT_CODE]
	342	stx %g5, [%g6 + TI_FAULT_ADDR]
	343
	344	mov %g6, %l1
	345	wrpr %g0, 0x0, %tl
936f482a DM	346
936f482a DM	347	661: nop
df7d6aec	348	.section .sun4v_1insn_patch, "ax"
936f482a DM	349	.word 661b
	350	SET_GL(0)
	351	.previous
	352
fc504928 DM	353	wrpr %g0, RTRAP_PSTATE, %pstate
fc504928 DM	354
314ef685 DM	355	mov %l1, %g6
	356	ldx [%g6 + TI_TASK], %g4
	357	LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
	358	call do_sparc64_fault
	359	add %sp, PTREGS_OFF, %o0
	360	ba,pt %xcc, rtrap
	361	nop
	362
	363	user_rtt_pre_restore:
	364	add %g1, 1, %g1
	365	wrpr %g1, 0x0, %cwp
	366
	367	user_rtt_restore:
1da177e4 LT	368	restore
	369	rdpr %canrestore, %g1
	370	wrpr %g1, 0x0, %cleanwin
	371	retry
	372	nop
	373
314ef685 DM	374	kern_rtt: rdpr %canrestore, %g1
	375	brz,pn %g1, kern_rtt_fill
	376	nop
	377	kern_rtt_restore:
ada44a04	378	stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685	379	restore
1da177e4	380	retry
314ef685	381
1da177e4 LT	382	to_kernel:
	383	#ifdef CONFIG_PREEMPT
	384	ldsw [%g6 + TI_PRE_COUNT], %l5
	385	brnz %l5, kern_fpucheck
	386	ldx [%g6 + TI_FLAGS], %l5
	387	andcc %l5, _TIF_NEED_RESCHED, %g0
	388	be,pt %xcc, kern_fpucheck
10e26723 DM	389	nop
10e26723 DM	390	cmp %l4, 0
1da177e4 LT	391	bne,pn %xcc, kern_fpucheck
	392	sethi %hi(PREEMPT_ACTIVE), %l6
	393	stw %l6, [%g6 + TI_PRE_COUNT]
	394	call schedule
	395	nop
	396	ba,pt %xcc, rtrap
	397	stw %g0, [%g6 + TI_PRE_COUNT]
	398	#endif
	399	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	400	brz,pt %l5, rt_continue
	401	srl %l5, 1, %o0
	402	add %g6, TI_FPSAVED, %l6
	403	ldub [%l6 + %o0], %l2
	404	sub %l5, 2, %l5
	405
	406	add %g6, TI_GSR, %o1
	407	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	408	be,pt %icc, 2f
	409	and %l2, FPRS_DL, %l6
	410	andcc %l2, FPRS_FEF, %g0
	411	be,pn %icc, 5f
	412	sll %o0, 3, %o5
	413	rd %fprs, %g1
	414
	415	wr %g1, FPRS_FEF, %fprs
	416	ldx [%o1 + %o5], %g1
	417	add %g6, TI_XFSR, %o1
1da177e4 LT	418	sll %o0, 8, %o2
	419	add %g6, TI_FPREGS, %o3
	420	brz,pn %l6, 1f
	421	add %g6, TI_FPREGS+0x40, %o4
	422
ba639933	423	membar #Sync
1da177e4 LT	424	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	425	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	426	membar #Sync
1da177e4 LT	427	1: andcc %l2, FPRS_DU, %g0
	428	be,pn %icc, 1f
	429	wr %g1, 0, %gsr
	430	add %o2, 0x80, %o2
ba639933	431	membar #Sync
1da177e4 LT	432	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	433	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	434	1: membar #Sync
	435	ldx [%o1 + %o5], %fsr
	436	2: stb %l5, [%g6 + TI_FPDEPTH]
	437	ba,pt %xcc, rt_continue
	438	nop
	439	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	440	sll %o0, 8, %o2
	441
	442	add %g6, TI_FPREGS+0x80, %o3
	443	add %g6, TI_FPREGS+0xc0, %o4
ba639933	444	membar #Sync
1da177e4 LT	445	ldda [%o3 + %o2] ASI_BLK_P, %f32
	446	ldda [%o4 + %o2] ASI_BLK_P, %f48
	447	membar #Sync
	448	wr %g0, FPRS_DU, %fprs
	449	ba,pt %xcc, rt_continue
	450	stb %l5, [%g6 + TI_FPDEPTH]