[deliverable/linux.git] / arch / sparc / kernel / setup_64.c

/*
 *  linux/arch/sparc64/kernel/setup.c
 *
 *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/syscalls.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/inet.h>
#include <linux/console.h>
#include <linux/root_dev.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/initrd.h>
#include <linux/module.h>

#include <asm/io.h>
#include <asm/processor.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/idprom.h>
#include <asm/head.h>
#include <asm/starfire.h>
#include <asm/mmu_context.h>
#include <asm/timer.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/mmu.h>
#include <asm/ns87303.h>
#include <asm/btext.h>
#include <asm/elf.h>
#include <asm/mdesc.h>
#include <asm/cacheflush.h>

#ifdef CONFIG_IP_PNP
#include <net/ipconfig.h>
#endif

#include "entry.h"
#include "kernel.h"

/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
 * operations in asm/ns87303.h
 */
DEFINE_SPINLOCK(ns87303_lock);
EXPORT_SYMBOL(ns87303_lock);

struct screen_info screen_info = {
	0, 0,			/* orig-x, orig-y */
	0,			/* unused */
	0,			/* orig-video-page */
	0,			/* orig-video-mode */
	128,			/* orig-video-cols */
	0, 0, 0,		/* unused, ega_bx, unused */
	54,			/* orig-video-lines */
	0,                      /* orig-video-isVGA */
	16                      /* orig-video-points */
};

static void
prom_console_write(struct console *con, const char *s, unsigned n)
{
	prom_write(s, n);
}

/* Exported for mm/init.c:paging_init. */
unsigned long cmdline_memory_size = 0;

static struct console prom_early_console = {
	.name =		"earlyprom",
	.write =	prom_console_write,
	.flags =	CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
	.index =	-1,
};

/* 
 * Process kernel command line switches that are specific to the
 * SPARC or that require special low-level processing.
 */
static void __init process_switch(char c)
{
	switch (c) {
	case 'd':
	case 's':
		break;
	case 'h':
		prom_printf("boot_flags_init: Halt!\n");
		prom_halt();
		break;
	case 'p':
		prom_early_console.flags &= ~CON_BOOT;
		break;
	case 'P':
		/* Force UltraSPARC-III P-Cache on. */
		if (tlb_type != cheetah) {
			printk("BOOT: Ignoring P-Cache force option.\n");
			break;
		}
		cheetah_pcache_forced_on = 1;
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
		cheetah_enable_pcache();
		break;

	default:
		printk("Unknown boot switch (-%c)\n", c);
		break;
	}
}

static void __init boot_flags_init(char *commands)
{
	while (*commands) {
		/* Move to the start of the next "argument". */
		while (*commands && *commands == ' ')
			commands++;

		/* Process any command switches, otherwise skip it. */
		if (*commands == '\0')
			break;
		if (*commands == '-') {
			commands++;
			while (*commands && *commands != ' ')
				process_switch(*commands++);
			continue;
		}
		if (!strncmp(commands, "mem=", 4))
			cmdline_memory_size = memparse(commands + 4, &commands);

		while (*commands && *commands != ' ')
			commands++;
	}
}

extern unsigned short root_flags;
extern unsigned short root_dev;
extern unsigned short ram_flags;
#define RAMDISK_IMAGE_START_MASK	0x07FF
#define RAMDISK_PROMPT_FLAG		0x8000
#define RAMDISK_LOAD_FLAG		0x4000

extern int root_mountflags;

char reboot_command[COMMAND_LINE_SIZE];

static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };

void __init per_cpu_patch(void)
{
	struct cpuid_patch_entry *p;
	unsigned long ver;
	int is_jbus;

	if (tlb_type == spitfire && !this_is_starfire)
		return;

	is_jbus = 0;
	if (tlb_type != hypervisor) {
		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
			   (ver >> 32UL) == __SERRANO_ID);
	}

	p = &__cpuid_patch;
	while (p < &__cpuid_patch_end) {
		unsigned long addr = p->addr;
		unsigned int *insns;

		switch (tlb_type) {
		case spitfire:
			insns = &p->starfire[0];
			break;
		case cheetah:
		case cheetah_plus:
			if (is_jbus)
				insns = &p->cheetah_jbus[0];
			else
				insns = &p->cheetah_safari[0];
			break;
		case hypervisor:
			insns = &p->sun4v[0];
			break;
		default:
			prom_printf("Unknown cpu type, halting.\n");
			prom_halt();
		}

		*(unsigned int *) (addr +  0) = insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		*(unsigned int *) (addr +  8) = insns[2];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  8));

		*(unsigned int *) (addr + 12) = insns[3];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr + 12));

		p++;
	}
}

void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
			     struct sun4v_1insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insn;
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		start++;
	}
}

void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

void __init sun4v_patch(void)
{
	extern void sun4v_hvapi_init(void);

	if (tlb_type != hypervisor)
		return;

	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
				&__sun4v_1insn_patch_end);

	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
				&__sun4v_2insn_patch_end);

	sun4v_hvapi_init();
}

static void __init popc_patch(void)
{
	struct popc_3insn_patch_entry *p3;
	struct popc_6insn_patch_entry *p6;

	p3 = &__popc_3insn_patch;
	while (p3 < &__popc_3insn_patch_end) {
		unsigned long i, addr = p3->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p3++;
	}

	p6 = &__popc_6insn_patch;
	while (p6 < &__popc_6insn_patch_end) {
		unsigned long i, addr = p6->addr;

		for (i = 0; i < 6; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p6++;
	}
}

static void __init pause_patch(void)
{
	struct pause_patch_entry *p;

	p = &__pause_3insn_patch;
	while (p < &__pause_3insn_patch_end) {
		unsigned long i, addr = p->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p++;
	}
}

#ifdef CONFIG_SMP
void __init boot_cpu_id_too_large(int cpu)
{
	prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
		    cpu, NR_CPUS);
	prom_halt();
}
#endif

/* On Ultra, we support all of the v8 capabilities. */
unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
				   HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
				   HWCAP_SPARC_V9);
EXPORT_SYMBOL(sparc64_elf_hwcap);

static const char *hwcaps[] = {
	"flush", "stbar", "swap", "muldiv", "v9",
	"ultra3", "blkinit", "n2",

	/* These strings are as they appear in the machine description
	 * 'hwcap-list' property for cpu nodes.
	 */
	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
	"ima", "cspare", "pause", "cbcond",
};

static const char *crypto_hwcaps[] = {
	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
};

void cpucap_info(struct seq_file *m)
{
	unsigned long caps = sparc64_elf_hwcap;
	int i, printed = 0;

	seq_puts(m, "cpucaps\t\t: ");
	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (caps & bit) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", hwcaps[i]);
			printed++;
		}
	}
	if (caps & HWCAP_SPARC_CRYPTO) {
		unsigned long cfr;

		__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			unsigned long bit = 1UL << i;
			if (cfr & bit) {
				seq_printf(m, "%s%s",
					   printed ? "," : "", crypto_hwcaps[i]);
				printed++;
			}
		}
	}
	seq_putc(m, '\n');
}

static void __init report_one_hwcap(int *printed, const char *name)
{
	if ((*printed) == 0)
		printk(KERN_INFO "CPU CAPS: [");
	printk(KERN_CONT "%s%s",
	       (*printed) ? "," : "", name);
	if (++(*printed) == 8) {
		printk(KERN_CONT "]\n");
		*printed = 0;
	}
}

static void __init report_crypto_hwcaps(int *printed)
{
	unsigned long cfr;
	int i;

	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));

	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (cfr & bit)
			report_one_hwcap(printed, crypto_hwcaps[i]);
	}
}

static void __init report_hwcaps(unsigned long caps)
{
	int i, printed = 0;

	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (caps & bit)
			report_one_hwcap(&printed, hwcaps[i]);
	}
	if (caps & HWCAP_SPARC_CRYPTO)
		report_crypto_hwcaps(&printed);
	if (printed != 0)
		printk(KERN_CONT "]\n");
}

static unsigned long __init mdesc_cpu_hwcap_list(void)
{
	struct mdesc_handle *hp;
	unsigned long caps = 0;
	const char *prop;
	int len;
	u64 pn;

	hp = mdesc_grab();
	if (!hp)
		return 0;

	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	if (pn == MDESC_NODE_NULL)
		goto out;

	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	if (!prop)
		goto out;

	while (len) {
		int i, plen;

		for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
			unsigned long bit = 1UL << i;

			if (!strcmp(prop, hwcaps[i])) {
				caps |= bit;
				break;
			}
		}
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			if (!strcmp(prop, crypto_hwcaps[i]))
				caps |= HWCAP_SPARC_CRYPTO;
		}

		plen = strlen(prop) + 1;
		prop += plen;
		len -= plen;
	}

out:
	mdesc_release(hp);
	return caps;
}

/* This yields a mask that user programs can use to figure out what
 * instruction set this cpu supports.
 */
static void __init init_sparc64_elf_hwcap(void)
{
	unsigned long cap = sparc64_elf_hwcap;
	unsigned long mdesc_caps;

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cap |= HWCAP_SPARC_ULTRA3;
	else if (tlb_type == hypervisor) {
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_BLKINIT;
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_N2;
	}

	cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);

	mdesc_caps = mdesc_cpu_hwcap_list();
	if (!mdesc_caps) {
		if (tlb_type == spitfire)
			cap |= AV_SPARC_VIS;
		if (tlb_type == cheetah || tlb_type == cheetah_plus)
			cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
		if (tlb_type == cheetah_plus) {
			unsigned long impl, ver;

			__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
			impl = ((ver >> 32) & 0xffff);
			if (impl == PANTHER_IMPL)
				cap |= AV_SPARC_POPC;
		}
		if (tlb_type == hypervisor) {
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
				cap |= AV_SPARC_ASI_BLK_INIT;
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
					AV_SPARC_ASI_BLK_INIT |
					AV_SPARC_POPC);
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
					AV_SPARC_FMAF);
		}
	}
	sparc64_elf_hwcap = cap | mdesc_caps;

	report_hwcaps(sparc64_elf_hwcap);

	if (sparc64_elf_hwcap & AV_SPARC_POPC)
		popc_patch();
	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
		pause_patch();
}

void __init setup_arch(char **cmdline_p)
{
	/* Initialize PROM console and command line. */
	*cmdline_p = prom_getbootargs();
	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
	parse_early_param();

	boot_flags_init(*cmdline_p);
#ifdef CONFIG_EARLYFB
	if (btext_find_display())
#endif
		register_console(&prom_early_console);

	if (tlb_type == hypervisor)
		printk("ARCH: SUN4V\n");
	else
		printk("ARCH: SUN4U\n");

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	idprom_init();

	if (!root_flags)
		root_mountflags &= ~MS_RDONLY;
	ROOT_DEV = old_decode_dev(root_dev);
#ifdef CONFIG_BLK_DEV_RAM
	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);	
#endif

	task_thread_info(&init_task)->kregs = &fake_swapper_regs;

#ifdef CONFIG_IP_PNP
	if (!ic_set_manually) {
		phandle chosen = prom_finddevice("/chosen");
		u32 cl, sv, gw;
		
		cl = prom_getintdefault (chosen, "client-ip", 0);
		sv = prom_getintdefault (chosen, "server-ip", 0);
		gw = prom_getintdefault (chosen, "gateway-ip", 0);
		if (cl && sv) {
			ic_myaddr = cl;
			ic_servaddr = sv;
			if (gw)
				ic_gateway = gw;
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
			ic_proto_enabled = 0;
#endif
		}
	}
#endif

	/* Get boot processor trap_block[] setup.  */
	init_cur_cpu_trap(current_thread_info());

	paging_init();
	init_sparc64_elf_hwcap();
}

extern int stop_a_enabled;

void sun_do_break(void)
{
	if (!stop_a_enabled)
		return;

	prom_printf("\n");
	flush_user_windows();

	prom_cmdline();
}
EXPORT_SYMBOL(sun_do_break);

int stop_a_enabled = 1;
EXPORT_SYMBOL(stop_a_enabled);
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* linux/arch/sparc64/kernel/setup.c
	3	*
	4	* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	6	*/
	7
	8	#include <linux/errno.h>
	9	#include <linux/sched.h>
	10	#include <linux/kernel.h>
	11	#include <linux/mm.h>
	12	#include <linux/stddef.h>
	13	#include <linux/unistd.h>
	14	#include <linux/ptrace.h>
1da177e4 LT	15	#include <asm/smp.h>
1da177e4 LT	16	#include <linux/user.h>
894673ee	17	#include <linux/screen_info.h>
1da177e4	18	#include <linux/delay.h>
1da177e4 LT	19	#include <linux/fs.h>
	20	#include <linux/seq_file.h>
	21	#include <linux/syscalls.h>
	22	#include <linux/kdev_t.h>
	23	#include <linux/major.h>
	24	#include <linux/string.h>
	25	#include <linux/init.h>
	26	#include <linux/inet.h>
	27	#include <linux/console.h>
	28	#include <linux/root_dev.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/cpu.h>
	31	#include <linux/initrd.h>
ac85fe8b	32	#include <linux/module.h>
1da177e4	33
1da177e4 LT	34	#include <asm/io.h>
	35	#include <asm/processor.h>
	36	#include <asm/oplib.h>
	37	#include <asm/page.h>
	38	#include <asm/pgtable.h>
	39	#include <asm/idprom.h>
	40	#include <asm/head.h>
	41	#include <asm/starfire.h>
	42	#include <asm/mmu_context.h>
	43	#include <asm/timer.h>
	44	#include <asm/sections.h>
	45	#include <asm/setup.h>
	46	#include <asm/mmu.h>
5cbc3073	47	#include <asm/ns87303.h>
c57ec52f	48	#include <asm/btext.h>
ac85fe8b DM	49	#include <asm/elf.h>
ac85fe8b DM	50	#include <asm/mdesc.h>
d550bbd4	51	#include <asm/cacheflush.h>
1da177e4 LT	52
	53	#ifdef CONFIG_IP_PNP
	54	#include <net/ipconfig.h>
	55	#endif
	56
3d5ae6b6	57	#include "entry.h"
53ae3419	58	#include "kernel.h"
3d5ae6b6	59
5cbc3073 DM	60	/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
	61	* operations in asm/ns87303.h
	62	*/
	63	DEFINE_SPINLOCK(ns87303_lock);
917c3660	64	EXPORT_SYMBOL(ns87303_lock);
5cbc3073	65
1da177e4 LT	66	struct screen_info screen_info = {
	67	0, 0, /* orig-x, orig-y */
	68	0, /* unused */
	69	0, /* orig-video-page */
	70	0, /* orig-video-mode */
	71	128, /* orig-video-cols */
	72	0, 0, 0, /* unused, ega_bx, unused */
	73	54, /* orig-video-lines */
	74	0, /* orig-video-isVGA */
	75	16 /* orig-video-points */
	76	};
	77
1da177e4 LT	78	static void
	79	prom_console_write(struct console con, const char s, unsigned n)
	80	{
	81	prom_write(s, n);
	82	}
	83
1da177e4 LT	84	/* Exported for mm/init.c:paging_init. */
	85	unsigned long cmdline_memory_size = 0;
	86
3c62a2d3 DM	87	static struct console prom_early_console = {
3c62a2d3 DM	88	.name = "earlyprom",
1da177e4	89	.write = prom_console_write,
db9a7fb1	90	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,
1da177e4 LT	91	.index = -1,
	92	};
	93
1da177e4 LT	94	/*
	95	* Process kernel command line switches that are specific to the
	96	* SPARC or that require special low-level processing.
	97	*/
	98	static void __init process_switch(char c)
	99	{
	100	switch (c) {
	101	case 'd':
1da177e4	102	case 's':
1da177e4 LT	103	break;
	104	case 'h':
	105	prom_printf("boot_flags_init: Halt!\n");
	106	prom_halt();
	107	break;
	108	case 'p':
11032c17	109	prom_early_console.flags &= ~CON_BOOT;
1da177e4	110	break;
816242da DM	111	case 'P':
	112	/* Force UltraSPARC-III P-Cache on. */
	113	if (tlb_type != cheetah) {
	114	printk("BOOT: Ignoring P-Cache force option.\n");
	115	break;
	116	}
	117	cheetah_pcache_forced_on = 1;
373d4d09	118	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
816242da DM	119	cheetah_enable_pcache();
	120	break;
	121
1da177e4 LT	122	default:
	123	printk("Unknown boot switch (-%c)\n", c);
	124	break;
	125	}
	126	}
	127
1da177e4 LT	128	static void __init boot_flags_init(char *commands)
	129	{
	130	while (*commands) {
	131	/* Move to the start of the next "argument". */
	132	while (commands && commands == ' ')
	133	commands++;
	134
	135	/* Process any command switches, otherwise skip it. */
	136	if (*commands == '\0')
	137	break;
	138	if (*commands == '-') {
	139	commands++;
	140	while (commands && commands != ' ')
	141	process_switch(*commands++);
	142	continue;
	143	}
7c21d533	144	if (!strncmp(commands, "mem=", 4))
	145	cmdline_memory_size = memparse(commands + 4, &commands);
	146
1da177e4 LT	147	while (commands && commands != ' ')
	148	commands++;
	149	}
	150	}
	151
1da177e4 LT	152	extern unsigned short root_flags;
	153	extern unsigned short root_dev;
	154	extern unsigned short ram_flags;
	155	#define RAMDISK_IMAGE_START_MASK 0x07FF
	156	#define RAMDISK_PROMPT_FLAG 0x8000
	157	#define RAMDISK_LOAD_FLAG 0x4000
	158
	159	extern int root_mountflags;
	160
	161	char reboot_command[COMMAND_LINE_SIZE];
	162
	163	static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
	164
951bc82c	165	void __init per_cpu_patch(void)
92704a1c	166	{
92704a1c DM	167	struct cpuid_patch_entry *p;
	168	unsigned long ver;
	169	int is_jbus;
	170
	171	if (tlb_type == spitfire && !this_is_starfire)
	172	return;
	173
d82ace7d DM	174	is_jbus = 0;
	175	if (tlb_type != hypervisor) {
	176	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
ebd8c56c DM	177	is_jbus = ((ver >> 32UL) == __JALAPENO_ID \|\|
ebd8c56c DM	178	(ver >> 32UL) == __SERRANO_ID);
d82ace7d	179	}
92704a1c DM	180
	181	p = &__cpuid_patch;
	182	while (p < &__cpuid_patch_end) {
	183	unsigned long addr = p->addr;
	184	unsigned int *insns;
	185
	186	switch (tlb_type) {
	187	case spitfire:
	188	insns = &p->starfire[0];
	189	break;
	190	case cheetah:
	191	case cheetah_plus:
	192	if (is_jbus)
	193	insns = &p->cheetah_jbus[0];
	194	else
	195	insns = &p->cheetah_safari[0];
	196	break;
d96b8153 DM	197	case hypervisor:
	198	insns = &p->sun4v[0];
	199	break;
92704a1c DM	200	default:
	201	prom_printf("Unknown cpu type, halting.\n");
	202	prom_halt();
6cb79b3f	203	}
92704a1c DM	204
92704a1c DM	205	(unsigned int ) (addr + 0) = insns[0];
840aaef8	206	wmb();
92704a1c DM	207	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	208
	209	(unsigned int ) (addr + 4) = insns[1];
840aaef8	210	wmb();
92704a1c DM	211	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	212
	213	(unsigned int ) (addr + 8) = insns[2];
840aaef8	214	wmb();
92704a1c DM	215	__asm__ __volatile__("flush %0" : : "r" (addr + 8));
	216
	217	(unsigned int ) (addr + 12) = insns[3];
840aaef8	218	wmb();
92704a1c DM	219	__asm__ __volatile__("flush %0" : : "r" (addr + 12));
	220
	221	p++;
	222	}
92704a1c DM	223	}
92704a1c DM	224
0b64120c DM	225	void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
0b64120c DM	226	struct sun4v_1insn_patch_entry *end)
936f482a	227	{
0b64120c DM	228	while (start < end) {
0b64120c DM	229	unsigned long addr = start->addr;
936f482a	230
0b64120c	231	(unsigned int ) (addr + 0) = start->insn;
840aaef8	232	wmb();
936f482a DM	233	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
936f482a DM	234
0b64120c	235	start++;
45fec05f	236	}
0b64120c	237	}
45fec05f	238
0b64120c DM	239	void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	240	struct sun4v_2insn_patch_entry *end)
	241	{
	242	while (start < end) {
	243	unsigned long addr = start->addr;
45fec05f	244
0b64120c	245	(unsigned int ) (addr + 0) = start->insns[0];
840aaef8	246	wmb();
45fec05f DM	247	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
45fec05f DM	248
0b64120c	249	(unsigned int ) (addr + 4) = start->insns[1];
840aaef8	250	wmb();
45fec05f DM	251	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
45fec05f DM	252
0b64120c	253	start++;
936f482a	254	}
0b64120c DM	255	}
	256
	257	void __init sun4v_patch(void)
	258	{
	259	extern void sun4v_hvapi_init(void);
	260
	261	if (tlb_type != hypervisor)
	262	return;
	263
	264	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
	265	&__sun4v_1insn_patch_end);
	266
	267	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
	268	&__sun4v_2insn_patch_end);
c7754d46 DM	269
c7754d46 DM	270	sun4v_hvapi_init();
936f482a DM	271	}
936f482a DM	272
ef7c4d46 DM	273	static void __init popc_patch(void)
	274	{
	275	struct popc_3insn_patch_entry *p3;
56d205cc	276	struct popc_6insn_patch_entry *p6;
ef7c4d46 DM	277
	278	p3 = &__popc_3insn_patch;
	279	while (p3 < &__popc_3insn_patch_end) {
56d205cc	280	unsigned long i, addr = p3->addr;
ef7c4d46	281
56d205cc DM	282	for (i = 0; i < 3; i++) {
	283	(unsigned int ) (addr + (i * 4)) = p3->insns[i];
	284	wmb();
	285	__asm__ __volatile__("flush %0"
	286	: : "r" (addr + (i * 4)));
	287	}
ef7c4d46	288
56d205cc DM	289	p3++;
56d205cc DM	290	}
ef7c4d46	291
56d205cc DM	292	p6 = &__popc_6insn_patch;
	293	while (p6 < &__popc_6insn_patch_end) {
	294	unsigned long i, addr = p6->addr;
ef7c4d46	295
56d205cc DM	296	for (i = 0; i < 6; i++) {
	297	(unsigned int ) (addr + (i * 4)) = p6->insns[i];
	298	wmb();
	299	__asm__ __volatile__("flush %0"
	300	: : "r" (addr + (i * 4)));
	301	}
	302
	303	p6++;
ef7c4d46 DM	304	}
	305	}
	306
e9b9eb59 DM	307	static void __init pause_patch(void)
	308	{
	309	struct pause_patch_entry *p;
	310
187818cd DM	311	p = &__pause_3insn_patch;
187818cd DM	312	while (p < &__pause_3insn_patch_end) {
e9b9eb59 DM	313	unsigned long i, addr = p->addr;
	314
	315	for (i = 0; i < 3; i++) {
	316	(unsigned int ) (addr + (i * 4)) = p->insns[i];
	317	wmb();
	318	__asm__ __volatile__("flush %0"
	319	: : "r" (addr + (i * 4)));
	320	}
	321
	322	p++;
	323	}
	324	}
	325
951bc82c DM	326	#ifdef CONFIG_SMP
	327	void __init boot_cpu_id_too_large(int cpu)
	328	{
	329	prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
	330	cpu, NR_CPUS);
	331	prom_halt();
	332	}
	333	#endif
	334
ac85fe8b DM	335	/* On Ultra, we support all of the v8 capabilities. */
	336	unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \|
	337	HWCAP_SPARC_SWAP \| HWCAP_SPARC_MULDIV \|
	338	HWCAP_SPARC_V9);
	339	EXPORT_SYMBOL(sparc64_elf_hwcap);
	340
	341	static const char *hwcaps[] = {
	342	"flush", "stbar", "swap", "muldiv", "v9",
	343	"ultra3", "blkinit", "n2",
	344
	345	/* These strings are as they appear in the machine description
	346	* 'hwcap-list' property for cpu nodes.
	347	*/
	348	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	349	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
6f859c0e DM	350	"ima", "cspare", "pause", "cbcond",
	351	};
	352
	353	static const char *crypto_hwcaps[] = {
	354	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	355	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
ac85fe8b DM	356	};
	357
	358	void cpucap_info(struct seq_file *m)
	359	{
	360	unsigned long caps = sparc64_elf_hwcap;
	361	int i, printed = 0;
	362
	363	seq_puts(m, "cpucaps\t\t: ");
	364	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	365	unsigned long bit = 1UL << i;
	366	if (caps & bit) {
	367	seq_printf(m, "%s%s",
	368	printed ? "," : "", hwcaps[i]);
	369	printed++;
	370	}
	371	}
6f859c0e DM	372	if (caps & HWCAP_SPARC_CRYPTO) {
	373	unsigned long cfr;
	374
	375	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	376	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	377	unsigned long bit = 1UL << i;
	378	if (cfr & bit) {
	379	seq_printf(m, "%s%s",
	380	printed ? "," : "", crypto_hwcaps[i]);
	381	printed++;
	382	}
	383	}
	384	}
ac85fe8b DM	385	seq_putc(m, '\n');
	386	}
	387
6f859c0e DM	388	static void __init report_one_hwcap(int printed, const char name)
	389	{
	390	if ((*printed) == 0)
	391	printk(KERN_INFO "CPU CAPS: [");
	392	printk(KERN_CONT "%s%s",
	393	(*printed) ? "," : "", name);
	394	if (++(*printed) == 8) {
	395	printk(KERN_CONT "]\n");
	396	*printed = 0;
	397	}
	398	}
	399
	400	static void __init report_crypto_hwcaps(int *printed)
	401	{
	402	unsigned long cfr;
	403	int i;
	404
	405	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	406
	407	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	408	unsigned long bit = 1UL << i;
	409	if (cfr & bit)
	410	report_one_hwcap(printed, crypto_hwcaps[i]);
	411	}
	412	}
	413
ac85fe8b DM	414	static void __init report_hwcaps(unsigned long caps)
	415	{
	416	int i, printed = 0;
	417
ac85fe8b DM	418	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
ac85fe8b DM	419	unsigned long bit = 1UL << i;
6f859c0e DM	420	if (caps & bit)
6f859c0e DM	421	report_one_hwcap(&printed, hwcaps[i]);
ac85fe8b	422	}
6f859c0e DM	423	if (caps & HWCAP_SPARC_CRYPTO)
	424	report_crypto_hwcaps(&printed);
	425	if (printed != 0)
	426	printk(KERN_CONT "]\n");
ac85fe8b DM	427	}
	428
	429	static unsigned long __init mdesc_cpu_hwcap_list(void)
	430	{
	431	struct mdesc_handle *hp;
	432	unsigned long caps = 0;
	433	const char *prop;
	434	int len;
	435	u64 pn;
	436
	437	hp = mdesc_grab();
	438	if (!hp)
	439	return 0;
	440
	441	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	442	if (pn == MDESC_NODE_NULL)
	443	goto out;
	444
	445	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	446	if (!prop)
	447	goto out;
	448
	449	while (len) {
	450	int i, plen;
	451
	452	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	453	unsigned long bit = 1UL << i;
	454
	455	if (!strcmp(prop, hwcaps[i])) {
	456	caps \|= bit;
	457	break;
	458	}
	459	}
6f859c0e DM	460	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	461	if (!strcmp(prop, crypto_hwcaps[i]))
	462	caps \|= HWCAP_SPARC_CRYPTO;
	463	}
ac85fe8b DM	464
	465	plen = strlen(prop) + 1;
	466	prop += plen;
	467	len -= plen;
	468	}
	469
	470	out:
	471	mdesc_release(hp);
	472	return caps;
	473	}
	474
	475	/* This yields a mask that user programs can use to figure out what
	476	* instruction set this cpu supports.
	477	*/
	478	static void __init init_sparc64_elf_hwcap(void)
	479	{
	480	unsigned long cap = sparc64_elf_hwcap;
	481	unsigned long mdesc_caps;
	482
	483	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	484	cap \|= HWCAP_SPARC_ULTRA3;
	485	else if (tlb_type == hypervisor) {
	486	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 \|\|
	487	sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	488	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	489	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	490	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	491	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	492	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	493	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	494	cap \|= HWCAP_SPARC_BLKINIT;
ac85fe8b DM	495	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	496	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	497	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	498	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	499	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	500	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	501	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	502	cap \|= HWCAP_SPARC_N2;
	503	}
	504
	505	cap \|= (AV_SPARC_MUL32 \| AV_SPARC_DIV32 \| AV_SPARC_V8PLUS);
	506
	507	mdesc_caps = mdesc_cpu_hwcap_list();
	508	if (!mdesc_caps) {
	509	if (tlb_type == spitfire)
	510	cap \|= AV_SPARC_VIS;
	511	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	512	cap \|= AV_SPARC_VIS \| AV_SPARC_VIS2;
1a8e0da5 DM	513	if (tlb_type == cheetah_plus) {
	514	unsigned long impl, ver;
	515
	516	__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
	517	impl = ((ver >> 32) & 0xffff);
	518	if (impl == PANTHER_IMPL)
	519	cap \|= AV_SPARC_POPC;
	520	}
ac85fe8b DM	521	if (tlb_type == hypervisor) {
	522	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
	523	cap \|= AV_SPARC_ASI_BLK_INIT;
	524	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	525	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	526	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	527	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	528	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	529	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	530	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	531	cap \|= (AV_SPARC_VIS \| AV_SPARC_VIS2 \|
	532	AV_SPARC_ASI_BLK_INIT \|
	533	AV_SPARC_POPC);
08cefa9f DM	534	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	535	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	536	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	537	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	538	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	539	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	540	cap \|= (AV_SPARC_VIS3 \| AV_SPARC_HPC \|
	541	AV_SPARC_FMAF);
	542	}
	543	}
	544	sparc64_elf_hwcap = cap \| mdesc_caps;
	545
	546	report_hwcaps(sparc64_elf_hwcap);
ef7c4d46 DM	547
	548	if (sparc64_elf_hwcap & AV_SPARC_POPC)
	549	popc_patch();
e9b9eb59 DM	550	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
e9b9eb59 DM	551	pause_patch();
ac85fe8b DM	552	}
ac85fe8b DM	553
1da177e4 LT	554	void __init setup_arch(char **cmdline_p)
1da177e4 LT	555	{
1da177e4 LT	556	/* Initialize PROM console and command line. */
1da177e4 LT	557	*cmdline_p = prom_getbootargs();
117a0c5f	558	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
ce3b1d47	559	parse_early_param();
1da177e4	560
3c62a2d3	561	boot_flags_init(*cmdline_p);
c57ec52f DM	562	#ifdef CONFIG_EARLYFB
	563	if (btext_find_display())
	564	#endif
	565	register_console(&prom_early_console);
3c62a2d3	566
3a8c069d DM	567	if (tlb_type == hypervisor)
	568	printk("ARCH: SUN4V\n");
	569	else
	570	printk("ARCH: SUN4U\n");
1da177e4 LT	571
	572	#ifdef CONFIG_DUMMY_CONSOLE
	573	conswitchp = &dummy_con;
1da177e4 LT	574	#endif
1da177e4 LT	575
1da177e4	576	idprom_init();
1da177e4 LT	577
	578	if (!root_flags)
	579	root_mountflags &= ~MS_RDONLY;
	580	ROOT_DEV = old_decode_dev(root_dev);
467418f3	581	#ifdef CONFIG_BLK_DEV_RAM
1da177e4 LT	582	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	583	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	584	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
	585	#endif
	586
f3169641	587	task_thread_info(&init_task)->kregs = &fake_swapper_regs;
1da177e4 LT	588
	589	#ifdef CONFIG_IP_PNP
	590	if (!ic_set_manually) {
8d125562	591	phandle chosen = prom_finddevice("/chosen");
1da177e4 LT	592	u32 cl, sv, gw;
	593
	594	cl = prom_getintdefault (chosen, "client-ip", 0);
	595	sv = prom_getintdefault (chosen, "server-ip", 0);
	596	gw = prom_getintdefault (chosen, "gateway-ip", 0);
	597	if (cl && sv) {
	598	ic_myaddr = cl;
	599	ic_servaddr = sv;
	600	if (gw)
	601	ic_gateway = gw;
	602	#if defined(CONFIG_IP_PNP_BOOTP) \|\| defined(CONFIG_IP_PNP_RARP)
	603	ic_proto_enabled = 0;
	604	#endif
	605	}
	606	}
	607	#endif
	608
56fb4df6	609	/* Get boot processor trap_block[] setup. */
72aff53f	610	init_cur_cpu_trap(current_thread_info());
52845cdb DM	611
52845cdb DM	612	paging_init();
ac85fe8b	613	init_sparc64_elf_hwcap();
1da177e4 LT	614	}
1da177e4 LT	615
1da177e4 LT	616	extern int stop_a_enabled;
	617
	618	void sun_do_break(void)
	619	{
	620	if (!stop_a_enabled)
	621	return;
	622
	623	prom_printf("\n");
	624	flush_user_windows();
	625
	626	prom_cmdline();
	627	}
917c3660	628	EXPORT_SYMBOL(sun_do_break);
1da177e4	629
1da177e4	630	int stop_a_enabled = 1;
917c3660	631	EXPORT_SYMBOL(stop_a_enabled);