Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* smp.c: Sparc SMP support. |
2 | * | |
3 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
4 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
5 | * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org) | |
6 | */ | |
7 | ||
8 | #include <asm/head.h> | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/threads.h> | |
13 | #include <linux/smp.h> | |
1da177e4 LT |
14 | #include <linux/interrupt.h> |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
d3091298 | 23 | #include <linux/profile.h> |
f9fd3488 | 24 | #include <linux/cpu.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
60063497 | 27 | #include <linux/atomic.h> |
1da177e4 LT |
28 | |
29 | #include <asm/irq.h> | |
30 | #include <asm/page.h> | |
31 | #include <asm/pgalloc.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/oplib.h> | |
34 | #include <asm/cacheflush.h> | |
35 | #include <asm/tlbflush.h> | |
36 | #include <asm/cpudata.h> | |
f9fd3488 | 37 | #include <asm/timer.h> |
8401707f | 38 | #include <asm/leon.h> |
1da177e4 | 39 | |
f9fd3488 | 40 | #include "kernel.h" |
32231a66 AV |
41 | #include "irq.h" |
42 | ||
2066aadd | 43 | volatile unsigned long cpu_callin_map[NR_CPUS] = {0,}; |
1da177e4 | 44 | |
a54123e2 | 45 | cpumask_t smp_commenced_mask = CPU_MASK_NONE; |
1da177e4 | 46 | |
4ba22b16 SR |
47 | const struct sparc32_ipi_ops *sparc32_ipi_ops; |
48 | ||
1da177e4 LT |
49 | /* The only guaranteed locking primitive available on all Sparc |
50 | * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically | |
51 | * places the current byte at the effective address into dest_reg and | |
52 | * places 0xff there afterwards. Pretty lame locking primitive | |
53 | * compared to the Alpha and the Intel no? Most Sparcs have 'swap' | |
54 | * instruction which is much better... | |
55 | */ | |
56 | ||
2066aadd | 57 | void smp_store_cpu_info(int id) |
1da177e4 LT |
58 | { |
59 | int cpu_node; | |
f486b3dc | 60 | int mid; |
1da177e4 LT |
61 | |
62 | cpu_data(id).udelay_val = loops_per_jiffy; | |
63 | ||
64 | cpu_find_by_mid(id, &cpu_node); | |
65 | cpu_data(id).clock_tick = prom_getintdefault(cpu_node, | |
66 | "clock-frequency", 0); | |
67 | cpu_data(id).prom_node = cpu_node; | |
f486b3dc | 68 | mid = cpu_get_hwmid(cpu_node); |
650fb838 | 69 | |
f486b3dc SR |
70 | if (mid < 0) { |
71 | printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08d", id, cpu_node); | |
72 | mid = 0; | |
73 | } | |
74 | cpu_data(id).mid = mid; | |
1da177e4 LT |
75 | } |
76 | ||
77 | void __init smp_cpus_done(unsigned int max_cpus) | |
78 | { | |
a54123e2 | 79 | unsigned long bogosum = 0; |
ec7c14bd | 80 | int cpu, num = 0; |
a54123e2 | 81 | |
ec7c14bd RR |
82 | for_each_online_cpu(cpu) { |
83 | num++; | |
84 | bogosum += cpu_data(cpu).udelay_val; | |
85 | } | |
a54123e2 BB |
86 | |
87 | printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
88 | num, bogosum/(500000/HZ), | |
89 | (bogosum/(5000/HZ))%100); | |
90 | ||
8b3c848c | 91 | switch(sparc_cpu_model) { |
8b3c848c RB |
92 | case sun4m: |
93 | smp4m_smp_done(); | |
94 | break; | |
95 | case sun4d: | |
96 | smp4d_smp_done(); | |
97 | break; | |
8401707f KE |
98 | case sparc_leon: |
99 | leon_smp_done(); | |
100 | break; | |
8b3c848c RB |
101 | case sun4e: |
102 | printk("SUN4E\n"); | |
103 | BUG(); | |
104 | break; | |
105 | case sun4u: | |
106 | printk("SUN4U\n"); | |
107 | BUG(); | |
108 | break; | |
109 | default: | |
110 | printk("UNKNOWN!\n"); | |
111 | BUG(); | |
112 | break; | |
6cb79b3f | 113 | } |
1da177e4 LT |
114 | } |
115 | ||
116 | void cpu_panic(void) | |
117 | { | |
118 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
119 | panic("SMP bolixed\n"); | |
120 | } | |
121 | ||
2066aadd | 122 | struct linux_prom_registers smp_penguin_ctable = { 0 }; |
1da177e4 | 123 | |
1da177e4 LT |
124 | void smp_send_reschedule(int cpu) |
125 | { | |
d6d04819 DH |
126 | /* |
127 | * CPU model dependent way of implementing IPI generation targeting | |
128 | * a single CPU. The trap handler needs only to do trap entry/return | |
129 | * to call schedule. | |
130 | */ | |
4ba22b16 | 131 | sparc32_ipi_ops->resched(cpu); |
1da177e4 LT |
132 | } |
133 | ||
134 | void smp_send_stop(void) | |
135 | { | |
136 | } | |
137 | ||
d6d04819 DH |
138 | void arch_send_call_function_single_ipi(int cpu) |
139 | { | |
140 | /* trigger one IPI single call on one CPU */ | |
4ba22b16 | 141 | sparc32_ipi_ops->single(cpu); |
d6d04819 DH |
142 | } |
143 | ||
144 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
145 | { | |
146 | int cpu; | |
147 | ||
148 | /* trigger IPI mask call on each CPU */ | |
149 | for_each_cpu(cpu, mask) | |
4ba22b16 | 150 | sparc32_ipi_ops->mask_one(cpu); |
d6d04819 DH |
151 | } |
152 | ||
153 | void smp_resched_interrupt(void) | |
154 | { | |
90d3ac15 DM |
155 | irq_enter(); |
156 | scheduler_ipi(); | |
d6d04819 | 157 | local_cpu_data().irq_resched_count++; |
90d3ac15 DM |
158 | irq_exit(); |
159 | /* re-schedule routine called by interrupt return code. */ | |
d6d04819 DH |
160 | } |
161 | ||
162 | void smp_call_function_single_interrupt(void) | |
163 | { | |
164 | irq_enter(); | |
165 | generic_smp_call_function_single_interrupt(); | |
166 | local_cpu_data().irq_call_count++; | |
167 | irq_exit(); | |
168 | } | |
169 | ||
170 | void smp_call_function_interrupt(void) | |
171 | { | |
172 | irq_enter(); | |
173 | generic_smp_call_function_interrupt(); | |
174 | local_cpu_data().irq_call_count++; | |
175 | irq_exit(); | |
176 | } | |
177 | ||
1da177e4 LT |
178 | int setup_profiling_timer(unsigned int multiplier) |
179 | { | |
62f08283 | 180 | return -EINVAL; |
1da177e4 LT |
181 | } |
182 | ||
a54123e2 | 183 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 184 | { |
7202fb49 | 185 | int i, cpuid, extra; |
a54123e2 | 186 | |
a54123e2 BB |
187 | printk("Entering SMP Mode...\n"); |
188 | ||
a54123e2 BB |
189 | extra = 0; |
190 | for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) { | |
7202fb49 | 191 | if (cpuid >= NR_CPUS) |
a54123e2 BB |
192 | extra++; |
193 | } | |
7202fb49 BB |
194 | /* i = number of cpus */ |
195 | if (extra && max_cpus > i - extra) | |
a54123e2 BB |
196 | printk("Warning: NR_CPUS is too low to start all cpus\n"); |
197 | ||
198 | smp_store_cpu_info(boot_cpu_id); | |
199 | ||
8b3c848c | 200 | switch(sparc_cpu_model) { |
8b3c848c RB |
201 | case sun4m: |
202 | smp4m_boot_cpus(); | |
203 | break; | |
204 | case sun4d: | |
205 | smp4d_boot_cpus(); | |
206 | break; | |
8401707f KE |
207 | case sparc_leon: |
208 | leon_boot_cpus(); | |
209 | break; | |
8b3c848c RB |
210 | case sun4e: |
211 | printk("SUN4E\n"); | |
212 | BUG(); | |
213 | break; | |
214 | case sun4u: | |
215 | printk("SUN4U\n"); | |
216 | BUG(); | |
217 | break; | |
218 | default: | |
219 | printk("UNKNOWN!\n"); | |
220 | BUG(); | |
221 | break; | |
6cb79b3f | 222 | } |
1da177e4 LT |
223 | } |
224 | ||
7202fb49 BB |
225 | /* Set this up early so that things like the scheduler can init |
226 | * properly. We use the same cpu mask for both the present and | |
227 | * possible cpu map. | |
228 | */ | |
229 | void __init smp_setup_cpu_possible_map(void) | |
230 | { | |
231 | int instance, mid; | |
232 | ||
233 | instance = 0; | |
234 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
235 | if (mid < NR_CPUS) { | |
fe73971c RR |
236 | set_cpu_possible(mid, true); |
237 | set_cpu_present(mid, true); | |
7202fb49 BB |
238 | } |
239 | instance++; | |
240 | } | |
241 | } | |
242 | ||
92d452f0 | 243 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 244 | { |
a54123e2 BB |
245 | int cpuid = hard_smp_processor_id(); |
246 | ||
247 | if (cpuid >= NR_CPUS) { | |
248 | prom_printf("Serious problem, boot cpu id >= NR_CPUS\n"); | |
249 | prom_halt(); | |
250 | } | |
251 | if (cpuid != 0) | |
252 | printk("boot cpu id != 0, this could work but is untested\n"); | |
253 | ||
254 | current_thread_info()->cpu = cpuid; | |
fe73971c RR |
255 | set_cpu_online(cpuid, true); |
256 | set_cpu_possible(cpuid, true); | |
1da177e4 LT |
257 | } |
258 | ||
2066aadd | 259 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 260 | { |
8b3c848c RB |
261 | int ret=0; |
262 | ||
263 | switch(sparc_cpu_model) { | |
8b3c848c | 264 | case sun4m: |
f0a2bc7e | 265 | ret = smp4m_boot_one_cpu(cpu, tidle); |
8b3c848c RB |
266 | break; |
267 | case sun4d: | |
f0a2bc7e | 268 | ret = smp4d_boot_one_cpu(cpu, tidle); |
8b3c848c | 269 | break; |
8401707f | 270 | case sparc_leon: |
f0a2bc7e | 271 | ret = leon_boot_one_cpu(cpu, tidle); |
8401707f | 272 | break; |
8b3c848c RB |
273 | case sun4e: |
274 | printk("SUN4E\n"); | |
275 | BUG(); | |
276 | break; | |
277 | case sun4u: | |
278 | printk("SUN4U\n"); | |
279 | BUG(); | |
280 | break; | |
281 | default: | |
282 | printk("UNKNOWN!\n"); | |
283 | BUG(); | |
284 | break; | |
6cb79b3f | 285 | } |
a54123e2 BB |
286 | |
287 | if (!ret) { | |
fb1fece5 | 288 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
a54123e2 BB |
289 | while (!cpu_online(cpu)) |
290 | mb(); | |
291 | } | |
292 | return ret; | |
1da177e4 LT |
293 | } |
294 | ||
c0b0ba84 | 295 | static void arch_cpu_pre_starting(void *arg) |
f9fd3488 SR |
296 | { |
297 | local_ops->cache_all(); | |
298 | local_ops->tlb_all(); | |
299 | ||
300 | switch(sparc_cpu_model) { | |
301 | case sun4m: | |
302 | sun4m_cpu_pre_starting(arg); | |
303 | break; | |
304 | case sun4d: | |
305 | sun4d_cpu_pre_starting(arg); | |
306 | break; | |
307 | case sparc_leon: | |
308 | leon_cpu_pre_starting(arg); | |
309 | break; | |
310 | default: | |
311 | BUG(); | |
312 | } | |
313 | } | |
314 | ||
c0b0ba84 | 315 | static void arch_cpu_pre_online(void *arg) |
f9fd3488 SR |
316 | { |
317 | unsigned int cpuid = hard_smp_processor_id(); | |
318 | ||
319 | register_percpu_ce(cpuid); | |
320 | ||
321 | calibrate_delay(); | |
322 | smp_store_cpu_info(cpuid); | |
323 | ||
324 | local_ops->cache_all(); | |
325 | local_ops->tlb_all(); | |
326 | ||
327 | switch(sparc_cpu_model) { | |
328 | case sun4m: | |
329 | sun4m_cpu_pre_online(arg); | |
330 | break; | |
331 | case sun4d: | |
332 | sun4d_cpu_pre_online(arg); | |
333 | break; | |
334 | case sparc_leon: | |
335 | leon_cpu_pre_online(arg); | |
336 | break; | |
337 | default: | |
338 | BUG(); | |
339 | } | |
340 | } | |
341 | ||
c0b0ba84 | 342 | static void sparc_start_secondary(void *arg) |
f9fd3488 SR |
343 | { |
344 | unsigned int cpu; | |
345 | ||
346 | /* | |
347 | * SMP booting is extremely fragile in some architectures. So run | |
348 | * the cpu initialization code first before anything else. | |
349 | */ | |
350 | arch_cpu_pre_starting(arg); | |
351 | ||
352 | preempt_disable(); | |
353 | cpu = smp_processor_id(); | |
354 | ||
355 | /* Invoke the CPU_STARTING notifier callbacks */ | |
356 | notify_cpu_starting(cpu); | |
357 | ||
358 | arch_cpu_pre_online(arg); | |
359 | ||
360 | /* Set the CPU in the cpu_online_mask */ | |
361 | set_cpu_online(cpu, true); | |
362 | ||
363 | /* Enable local interrupts now */ | |
364 | local_irq_enable(); | |
365 | ||
366 | wmb(); | |
87fa05ae | 367 | cpu_startup_entry(CPUHP_ONLINE); |
f9fd3488 SR |
368 | |
369 | /* We should never reach here! */ | |
370 | BUG(); | |
371 | } | |
372 | ||
2066aadd | 373 | void smp_callin(void) |
f9fd3488 SR |
374 | { |
375 | sparc_start_secondary(NULL); | |
376 | } | |
377 | ||
1da177e4 LT |
378 | void smp_bogo(struct seq_file *m) |
379 | { | |
380 | int i; | |
381 | ||
394e3902 AM |
382 | for_each_online_cpu(i) { |
383 | seq_printf(m, | |
384 | "Cpu%dBogo\t: %lu.%02lu\n", | |
385 | i, | |
386 | cpu_data(i).udelay_val/(500000/HZ), | |
387 | (cpu_data(i).udelay_val/(5000/HZ))%100); | |
1da177e4 LT |
388 | } |
389 | } | |
390 | ||
391 | void smp_info(struct seq_file *m) | |
392 | { | |
393 | int i; | |
394 | ||
395 | seq_printf(m, "State:\n"); | |
394e3902 AM |
396 | for_each_online_cpu(i) |
397 | seq_printf(m, "CPU%d\t\t: online\n", i); | |
1da177e4 | 398 | } |