Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
cf3d7c1e | 3 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
066bcaca | 6 | #include <linux/export.h> |
1da177e4 LT |
7 | #include <linux/kernel.h> |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/seq_file.h> | |
20 | #include <linux/cache.h> | |
21 | #include <linux/jiffies.h> | |
22 | #include <linux/profile.h> | |
73fffc03 | 23 | #include <linux/bootmem.h> |
4fd78a5f | 24 | #include <linux/vmalloc.h> |
9960e9e8 | 25 | #include <linux/ftrace.h> |
82960b85 | 26 | #include <linux/cpu.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
1da177e4 LT |
28 | |
29 | #include <asm/head.h> | |
30 | #include <asm/ptrace.h> | |
60063497 | 31 | #include <linux/atomic.h> |
1da177e4 LT |
32 | #include <asm/tlbflush.h> |
33 | #include <asm/mmu_context.h> | |
34 | #include <asm/cpudata.h> | |
27a2ef38 DM |
35 | #include <asm/hvtramp.h> |
36 | #include <asm/io.h> | |
cf3d7c1e | 37 | #include <asm/timer.h> |
1da177e4 LT |
38 | |
39 | #include <asm/irq.h> | |
6d24c8dc | 40 | #include <asm/irq_regs.h> |
1da177e4 LT |
41 | #include <asm/page.h> |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/oplib.h> | |
44 | #include <asm/uaccess.h> | |
1da177e4 LT |
45 | #include <asm/starfire.h> |
46 | #include <asm/tlb.h> | |
56fb4df6 | 47 | #include <asm/sections.h> |
07f8e5f3 | 48 | #include <asm/prom.h> |
5cbc3073 | 49 | #include <asm/mdesc.h> |
4f0234f4 | 50 | #include <asm/ldc.h> |
e0204409 | 51 | #include <asm/hypervisor.h> |
b62818e5 | 52 | #include <asm/pcr.h> |
1da177e4 | 53 | |
280ff974 HP |
54 | #include "cpumap.h" |
55 | ||
a2f9f6bb DM |
56 | int sparc64_multi_core __read_mostly; |
57 | ||
d5a7430d | 58 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE; |
f78eae2e DM |
59 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly = |
60 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
4f0234f4 | 61 | |
d5a7430d | 62 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
4f0234f4 DM |
63 | EXPORT_SYMBOL(cpu_core_map); |
64 | ||
1da177e4 | 65 | static cpumask_t smp_commenced_mask; |
1da177e4 LT |
66 | |
67 | void smp_info(struct seq_file *m) | |
68 | { | |
69 | int i; | |
70 | ||
71 | seq_printf(m, "State:\n"); | |
394e3902 AM |
72 | for_each_online_cpu(i) |
73 | seq_printf(m, "CPU%d:\t\tonline\n", i); | |
1da177e4 LT |
74 | } |
75 | ||
76 | void smp_bogo(struct seq_file *m) | |
77 | { | |
78 | int i; | |
79 | ||
394e3902 AM |
80 | for_each_online_cpu(i) |
81 | seq_printf(m, | |
394e3902 | 82 | "Cpu%dClkTck\t: %016lx\n", |
394e3902 | 83 | i, cpu_data(i).clock_tick); |
1da177e4 LT |
84 | } |
85 | ||
112f4871 | 86 | extern void setup_sparc64_timer(void); |
1da177e4 LT |
87 | |
88 | static volatile unsigned long callin_flag = 0; | |
89 | ||
0f7f22d9 | 90 | void __cpuinit smp_callin(void) |
1da177e4 LT |
91 | { |
92 | int cpuid = hard_smp_processor_id(); | |
93 | ||
56fb4df6 | 94 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 95 | |
4a07e646 | 96 | if (tlb_type == hypervisor) |
490384e7 | 97 | sun4v_ktsb_register(); |
481295f9 | 98 | |
56fb4df6 | 99 | __flush_tlb_all(); |
1da177e4 | 100 | |
112f4871 | 101 | setup_sparc64_timer(); |
1da177e4 | 102 | |
816242da DM |
103 | if (cheetah_pcache_forced_on) |
104 | cheetah_enable_pcache(); | |
105 | ||
1da177e4 LT |
106 | local_irq_enable(); |
107 | ||
1da177e4 LT |
108 | callin_flag = 1; |
109 | __asm__ __volatile__("membar #Sync\n\t" | |
110 | "flush %%g6" : : : "memory"); | |
111 | ||
112 | /* Clear this or we will die instantly when we | |
113 | * schedule back to this idler... | |
114 | */ | |
db7d9a4e | 115 | current_thread_info()->new_child = 0; |
1da177e4 LT |
116 | |
117 | /* Attach to the address space of init_task. */ | |
118 | atomic_inc(&init_mm.mm_count); | |
119 | current->active_mm = &init_mm; | |
120 | ||
82960b85 DM |
121 | /* inform the notifiers about the new cpu */ |
122 | notify_cpu_starting(cpuid); | |
123 | ||
fb1fece5 | 124 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
4f07118f | 125 | rmb(); |
1da177e4 | 126 | |
8e255baa | 127 | ipi_call_lock_irq(); |
fb1fece5 | 128 | set_cpu_online(cpuid, true); |
8e255baa | 129 | ipi_call_unlock_irq(); |
5bfb5d69 NP |
130 | |
131 | /* idle thread is expected to have preempt disabled */ | |
132 | preempt_disable(); | |
1da177e4 LT |
133 | } |
134 | ||
135 | void cpu_panic(void) | |
136 | { | |
137 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
138 | panic("SMP bolixed\n"); | |
139 | } | |
140 | ||
1da177e4 LT |
141 | /* This tick register synchronization scheme is taken entirely from |
142 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
143 | * | |
144 | * The only change I've made is to rework it so that the master | |
145 | * initiates the synchonization instead of the slave. -DaveM | |
146 | */ | |
147 | ||
148 | #define MASTER 0 | |
149 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
150 | ||
151 | #define NUM_ROUNDS 64 /* magic value */ | |
152 | #define NUM_ITERS 5 /* likewise */ | |
153 | ||
154 | static DEFINE_SPINLOCK(itc_sync_lock); | |
155 | static unsigned long go[SLAVE + 1]; | |
156 | ||
157 | #define DEBUG_TICK_SYNC 0 | |
158 | ||
159 | static inline long get_delta (long *rt, long *master) | |
160 | { | |
161 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
162 | unsigned long tcenter, t0, t1, tm; | |
163 | unsigned long i; | |
164 | ||
165 | for (i = 0; i < NUM_ITERS; i++) { | |
166 | t0 = tick_ops->get_tick(); | |
167 | go[MASTER] = 1; | |
293666b7 | 168 | membar_safe("#StoreLoad"); |
1da177e4 | 169 | while (!(tm = go[SLAVE])) |
4f07118f | 170 | rmb(); |
1da177e4 | 171 | go[SLAVE] = 0; |
4f07118f | 172 | wmb(); |
1da177e4 LT |
173 | t1 = tick_ops->get_tick(); |
174 | ||
175 | if (t1 - t0 < best_t1 - best_t0) | |
176 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
177 | } | |
178 | ||
179 | *rt = best_t1 - best_t0; | |
180 | *master = best_tm - best_t0; | |
181 | ||
182 | /* average best_t0 and best_t1 without overflow: */ | |
183 | tcenter = (best_t0/2 + best_t1/2); | |
184 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
185 | tcenter++; | |
186 | return tcenter - best_tm; | |
187 | } | |
188 | ||
189 | void smp_synchronize_tick_client(void) | |
190 | { | |
191 | long i, delta, adj, adjust_latency = 0, done = 0; | |
c6fee081 | 192 | unsigned long flags, rt, master_time_stamp; |
1da177e4 LT |
193 | #if DEBUG_TICK_SYNC |
194 | struct { | |
195 | long rt; /* roundtrip time */ | |
196 | long master; /* master's timestamp */ | |
197 | long diff; /* difference between midpoint and master's timestamp */ | |
198 | long lat; /* estimate of itc adjustment latency */ | |
199 | } t[NUM_ROUNDS]; | |
200 | #endif | |
201 | ||
202 | go[MASTER] = 1; | |
203 | ||
204 | while (go[MASTER]) | |
4f07118f | 205 | rmb(); |
1da177e4 LT |
206 | |
207 | local_irq_save(flags); | |
208 | { | |
209 | for (i = 0; i < NUM_ROUNDS; i++) { | |
210 | delta = get_delta(&rt, &master_time_stamp); | |
c6fee081 | 211 | if (delta == 0) |
1da177e4 | 212 | done = 1; /* let's lock on to this... */ |
1da177e4 LT |
213 | |
214 | if (!done) { | |
215 | if (i > 0) { | |
216 | adjust_latency += -delta; | |
217 | adj = -delta + adjust_latency/4; | |
218 | } else | |
219 | adj = -delta; | |
220 | ||
112f4871 | 221 | tick_ops->add_tick(adj); |
1da177e4 LT |
222 | } |
223 | #if DEBUG_TICK_SYNC | |
224 | t[i].rt = rt; | |
225 | t[i].master = master_time_stamp; | |
226 | t[i].diff = delta; | |
227 | t[i].lat = adjust_latency/4; | |
228 | #endif | |
229 | } | |
230 | } | |
231 | local_irq_restore(flags); | |
232 | ||
233 | #if DEBUG_TICK_SYNC | |
234 | for (i = 0; i < NUM_ROUNDS; i++) | |
235 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
236 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
237 | #endif | |
238 | ||
519c4d2d JP |
239 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU " |
240 | "(last diff %ld cycles, maxerr %lu cycles)\n", | |
241 | smp_processor_id(), delta, rt); | |
1da177e4 LT |
242 | } |
243 | ||
244 | static void smp_start_sync_tick_client(int cpu); | |
245 | ||
246 | static void smp_synchronize_one_tick(int cpu) | |
247 | { | |
248 | unsigned long flags, i; | |
249 | ||
250 | go[MASTER] = 0; | |
251 | ||
252 | smp_start_sync_tick_client(cpu); | |
253 | ||
254 | /* wait for client to be ready */ | |
255 | while (!go[MASTER]) | |
4f07118f | 256 | rmb(); |
1da177e4 LT |
257 | |
258 | /* now let the client proceed into his loop */ | |
259 | go[MASTER] = 0; | |
293666b7 | 260 | membar_safe("#StoreLoad"); |
1da177e4 LT |
261 | |
262 | spin_lock_irqsave(&itc_sync_lock, flags); | |
263 | { | |
264 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
265 | while (!go[MASTER]) | |
4f07118f | 266 | rmb(); |
1da177e4 | 267 | go[MASTER] = 0; |
4f07118f | 268 | wmb(); |
1da177e4 | 269 | go[SLAVE] = tick_ops->get_tick(); |
293666b7 | 270 | membar_safe("#StoreLoad"); |
1da177e4 LT |
271 | } |
272 | } | |
273 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
274 | } | |
275 | ||
b14f5c10 | 276 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
27a2ef38 DM |
277 | /* XXX Put this in some common place. XXX */ |
278 | static unsigned long kimage_addr_to_ra(void *p) | |
279 | { | |
280 | unsigned long val = (unsigned long) p; | |
281 | ||
282 | return kern_base + (val - KERNBASE); | |
283 | } | |
284 | ||
557fe0e8 | 285 | static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, void **descrp) |
b14f5c10 DM |
286 | { |
287 | extern unsigned long sparc64_ttable_tl0; | |
288 | extern unsigned long kern_locked_tte_data; | |
b14f5c10 DM |
289 | struct hvtramp_descr *hdesc; |
290 | unsigned long trampoline_ra; | |
291 | struct trap_per_cpu *tb; | |
292 | u64 tte_vaddr, tte_data; | |
293 | unsigned long hv_err; | |
64658743 | 294 | int i; |
b14f5c10 | 295 | |
64658743 DM |
296 | hdesc = kzalloc(sizeof(*hdesc) + |
297 | (sizeof(struct hvtramp_mapping) * | |
298 | num_kernel_image_mappings - 1), | |
299 | GFP_KERNEL); | |
b14f5c10 | 300 | if (!hdesc) { |
27a2ef38 | 301 | printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate " |
b14f5c10 DM |
302 | "hvtramp_descr.\n"); |
303 | return; | |
304 | } | |
557fe0e8 | 305 | *descrp = hdesc; |
b14f5c10 DM |
306 | |
307 | hdesc->cpu = cpu; | |
64658743 | 308 | hdesc->num_mappings = num_kernel_image_mappings; |
b14f5c10 DM |
309 | |
310 | tb = &trap_block[cpu]; | |
b14f5c10 DM |
311 | |
312 | hdesc->fault_info_va = (unsigned long) &tb->fault_info; | |
313 | hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info); | |
314 | ||
315 | hdesc->thread_reg = thread_reg; | |
316 | ||
317 | tte_vaddr = (unsigned long) KERNBASE; | |
318 | tte_data = kern_locked_tte_data; | |
319 | ||
64658743 DM |
320 | for (i = 0; i < hdesc->num_mappings; i++) { |
321 | hdesc->maps[i].vaddr = tte_vaddr; | |
322 | hdesc->maps[i].tte = tte_data; | |
b14f5c10 DM |
323 | tte_vaddr += 0x400000; |
324 | tte_data += 0x400000; | |
b14f5c10 DM |
325 | } |
326 | ||
327 | trampoline_ra = kimage_addr_to_ra(hv_cpu_startup); | |
328 | ||
329 | hv_err = sun4v_cpu_start(cpu, trampoline_ra, | |
330 | kimage_addr_to_ra(&sparc64_ttable_tl0), | |
331 | __pa(hdesc)); | |
e0204409 DM |
332 | if (hv_err) |
333 | printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() " | |
334 | "gives error %lu\n", hv_err); | |
b14f5c10 DM |
335 | } |
336 | #endif | |
337 | ||
1da177e4 LT |
338 | extern unsigned long sparc64_cpu_startup; |
339 | ||
340 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
341 | * 32-bits (I think) so to be safe we have it read the pointer | |
342 | * contained here so we work on >4GB machines. -DaveM | |
343 | */ | |
344 | static struct thread_info *cpu_new_thread = NULL; | |
345 | ||
f0a2bc7e | 346 | static int __cpuinit smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle) |
1da177e4 LT |
347 | { |
348 | unsigned long entry = | |
349 | (unsigned long)(&sparc64_cpu_startup); | |
350 | unsigned long cookie = | |
351 | (unsigned long)(&cpu_new_thread); | |
557fe0e8 | 352 | void *descr = NULL; |
7890f794 | 353 | int timeout, ret; |
1da177e4 | 354 | |
1da177e4 | 355 | callin_flag = 0; |
f0a2bc7e | 356 | cpu_new_thread = task_thread_info(idle); |
1da177e4 | 357 | |
7890f794 | 358 | if (tlb_type == hypervisor) { |
b14f5c10 | 359 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
4f0234f4 DM |
360 | if (ldom_domaining_enabled) |
361 | ldom_startcpu_cpuid(cpu, | |
557fe0e8 DM |
362 | (unsigned long) cpu_new_thread, |
363 | &descr); | |
4f0234f4 DM |
364 | else |
365 | #endif | |
366 | prom_startcpu_cpuid(cpu, entry, cookie); | |
7890f794 | 367 | } else { |
5cbc3073 | 368 | struct device_node *dp = of_find_node_by_cpuid(cpu); |
7890f794 | 369 | |
6016a363 | 370 | prom_startcpu(dp->phandle, entry, cookie); |
7890f794 | 371 | } |
1da177e4 | 372 | |
4f0234f4 | 373 | for (timeout = 0; timeout < 50000; timeout++) { |
1da177e4 LT |
374 | if (callin_flag) |
375 | break; | |
376 | udelay(100); | |
377 | } | |
72aff53f | 378 | |
1da177e4 LT |
379 | if (callin_flag) { |
380 | ret = 0; | |
381 | } else { | |
382 | printk("Processor %d is stuck.\n", cpu); | |
1da177e4 LT |
383 | ret = -ENODEV; |
384 | } | |
385 | cpu_new_thread = NULL; | |
386 | ||
557fe0e8 | 387 | kfree(descr); |
b37d40d1 | 388 | |
1da177e4 LT |
389 | return ret; |
390 | } | |
391 | ||
392 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
393 | { | |
394 | u64 result, target; | |
395 | int stuck, tmp; | |
396 | ||
397 | if (this_is_starfire) { | |
398 | /* map to real upaid */ | |
399 | cpu = (((cpu & 0x3c) << 1) | | |
400 | ((cpu & 0x40) >> 4) | | |
401 | (cpu & 0x3)); | |
402 | } | |
403 | ||
404 | target = (cpu << 14) | 0x70; | |
405 | again: | |
406 | /* Ok, this is the real Spitfire Errata #54. | |
407 | * One must read back from a UDB internal register | |
408 | * after writes to the UDB interrupt dispatch, but | |
409 | * before the membar Sync for that write. | |
410 | * So we use the high UDB control register (ASI 0x7f, | |
411 | * ADDR 0x20) for the dummy read. -DaveM | |
412 | */ | |
413 | tmp = 0x40; | |
414 | __asm__ __volatile__( | |
415 | "wrpr %1, %2, %%pstate\n\t" | |
416 | "stxa %4, [%0] %3\n\t" | |
417 | "stxa %5, [%0+%8] %3\n\t" | |
418 | "add %0, %8, %0\n\t" | |
419 | "stxa %6, [%0+%8] %3\n\t" | |
420 | "membar #Sync\n\t" | |
421 | "stxa %%g0, [%7] %3\n\t" | |
422 | "membar #Sync\n\t" | |
423 | "mov 0x20, %%g1\n\t" | |
424 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
425 | "membar #Sync" | |
426 | : "=r" (tmp) | |
427 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
428 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
429 | "r" (0x10), "0" (tmp) | |
430 | : "g1"); | |
431 | ||
432 | /* NOTE: PSTATE_IE is still clear. */ | |
433 | stuck = 100000; | |
434 | do { | |
435 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
436 | : "=r" (result) | |
437 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
438 | if (result == 0) { | |
439 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
440 | : : "r" (pstate)); | |
441 | return; | |
442 | } | |
443 | stuck -= 1; | |
444 | if (stuck == 0) | |
445 | break; | |
446 | } while (result & 0x1); | |
447 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
448 | : : "r" (pstate)); | |
449 | if (stuck == 0) { | |
90181136 | 450 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
451 | smp_processor_id(), result); |
452 | } else { | |
453 | udelay(2); | |
454 | goto again; | |
455 | } | |
456 | } | |
457 | ||
90f7ae8a | 458 | static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 459 | { |
90f7ae8a DM |
460 | u64 *mondo, data0, data1, data2; |
461 | u16 *cpu_list; | |
1da177e4 LT |
462 | u64 pstate; |
463 | int i; | |
464 | ||
465 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
90f7ae8a DM |
466 | cpu_list = __va(tb->cpu_list_pa); |
467 | mondo = __va(tb->cpu_mondo_block_pa); | |
468 | data0 = mondo[0]; | |
469 | data1 = mondo[1]; | |
470 | data2 = mondo[2]; | |
471 | for (i = 0; i < cnt; i++) | |
472 | spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]); | |
1da177e4 LT |
473 | } |
474 | ||
475 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
476 | * packet, but we have no use for that. However we do take advantage of | |
477 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
478 | */ | |
90f7ae8a | 479 | static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 480 | { |
22adb358 | 481 | int nack_busy_id, is_jbus, need_more; |
90f7ae8a DM |
482 | u64 *mondo, pstate, ver, busy_mask; |
483 | u16 *cpu_list; | |
1da177e4 | 484 | |
90f7ae8a DM |
485 | cpu_list = __va(tb->cpu_list_pa); |
486 | mondo = __va(tb->cpu_mondo_block_pa); | |
cd5bc89d | 487 | |
1da177e4 LT |
488 | /* Unfortunately, someone at Sun had the brilliant idea to make the |
489 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
490 | * derivative processor. | |
491 | */ | |
492 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
493 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
494 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
495 | |
496 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
497 | ||
498 | retry: | |
22adb358 | 499 | need_more = 0; |
1da177e4 LT |
500 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" |
501 | : : "r" (pstate), "i" (PSTATE_IE)); | |
502 | ||
503 | /* Setup the dispatch data registers. */ | |
504 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
505 | "stxa %1, [%4] %6\n\t" | |
506 | "stxa %2, [%5] %6\n\t" | |
507 | "membar #Sync\n\t" | |
508 | : /* no outputs */ | |
90f7ae8a | 509 | : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]), |
1da177e4 LT |
510 | "r" (0x40), "r" (0x50), "r" (0x60), |
511 | "i" (ASI_INTR_W)); | |
512 | ||
513 | nack_busy_id = 0; | |
0de56d1a | 514 | busy_mask = 0; |
1da177e4 LT |
515 | { |
516 | int i; | |
517 | ||
90f7ae8a DM |
518 | for (i = 0; i < cnt; i++) { |
519 | u64 target, nr; | |
520 | ||
521 | nr = cpu_list[i]; | |
522 | if (nr == 0xffff) | |
523 | continue; | |
1da177e4 | 524 | |
90f7ae8a | 525 | target = (nr << 14) | 0x70; |
0de56d1a | 526 | if (is_jbus) { |
90f7ae8a | 527 | busy_mask |= (0x1UL << (nr * 2)); |
0de56d1a | 528 | } else { |
1da177e4 | 529 | target |= (nack_busy_id << 24); |
0de56d1a DM |
530 | busy_mask |= (0x1UL << |
531 | (nack_busy_id * 2)); | |
532 | } | |
1da177e4 LT |
533 | __asm__ __volatile__( |
534 | "stxa %%g0, [%0] %1\n\t" | |
535 | "membar #Sync\n\t" | |
536 | : /* no outputs */ | |
537 | : "r" (target), "i" (ASI_INTR_W)); | |
538 | nack_busy_id++; | |
22adb358 DM |
539 | if (nack_busy_id == 32) { |
540 | need_more = 1; | |
541 | break; | |
542 | } | |
1da177e4 LT |
543 | } |
544 | } | |
545 | ||
546 | /* Now, poll for completion. */ | |
547 | { | |
0de56d1a | 548 | u64 dispatch_stat, nack_mask; |
1da177e4 LT |
549 | long stuck; |
550 | ||
551 | stuck = 100000 * nack_busy_id; | |
0de56d1a | 552 | nack_mask = busy_mask << 1; |
1da177e4 LT |
553 | do { |
554 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
555 | : "=r" (dispatch_stat) | |
556 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
0de56d1a | 557 | if (!(dispatch_stat & (busy_mask | nack_mask))) { |
1da177e4 LT |
558 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" |
559 | : : "r" (pstate)); | |
22adb358 | 560 | if (unlikely(need_more)) { |
90f7ae8a DM |
561 | int i, this_cnt = 0; |
562 | for (i = 0; i < cnt; i++) { | |
563 | if (cpu_list[i] == 0xffff) | |
564 | continue; | |
565 | cpu_list[i] = 0xffff; | |
566 | this_cnt++; | |
567 | if (this_cnt == 32) | |
22adb358 DM |
568 | break; |
569 | } | |
570 | goto retry; | |
571 | } | |
1da177e4 LT |
572 | return; |
573 | } | |
574 | if (!--stuck) | |
575 | break; | |
0de56d1a | 576 | } while (dispatch_stat & busy_mask); |
1da177e4 LT |
577 | |
578 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
579 | : : "r" (pstate)); | |
580 | ||
0de56d1a | 581 | if (dispatch_stat & busy_mask) { |
1da177e4 LT |
582 | /* Busy bits will not clear, continue instead |
583 | * of freezing up on this cpu. | |
584 | */ | |
90181136 | 585 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
586 | smp_processor_id(), dispatch_stat); |
587 | } else { | |
588 | int i, this_busy_nack = 0; | |
589 | ||
590 | /* Delay some random time with interrupts enabled | |
591 | * to prevent deadlock. | |
592 | */ | |
593 | udelay(2 * nack_busy_id); | |
594 | ||
595 | /* Clear out the mask bits for cpus which did not | |
596 | * NACK us. | |
597 | */ | |
90f7ae8a DM |
598 | for (i = 0; i < cnt; i++) { |
599 | u64 check_mask, nr; | |
600 | ||
601 | nr = cpu_list[i]; | |
602 | if (nr == 0xffff) | |
603 | continue; | |
1da177e4 | 604 | |
92704a1c | 605 | if (is_jbus) |
90f7ae8a | 606 | check_mask = (0x2UL << (2*nr)); |
1da177e4 LT |
607 | else |
608 | check_mask = (0x2UL << | |
609 | this_busy_nack); | |
610 | if ((dispatch_stat & check_mask) == 0) | |
90f7ae8a | 611 | cpu_list[i] = 0xffff; |
1da177e4 | 612 | this_busy_nack += 2; |
22adb358 DM |
613 | if (this_busy_nack == 64) |
614 | break; | |
1da177e4 LT |
615 | } |
616 | ||
617 | goto retry; | |
618 | } | |
619 | } | |
620 | } | |
621 | ||
1d2f1f90 | 622 | /* Multi-cpu list version. */ |
90f7ae8a | 623 | static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
a43fe0e7 | 624 | { |
ed4d9c66 | 625 | int retries, this_cpu, prev_sent, i, saw_cpu_error; |
c02a5119 | 626 | unsigned long status; |
b830ab66 | 627 | u16 *cpu_list; |
17f34f0e | 628 | |
b830ab66 | 629 | this_cpu = smp_processor_id(); |
1d2f1f90 | 630 | |
b830ab66 DM |
631 | cpu_list = __va(tb->cpu_list_pa); |
632 | ||
ed4d9c66 | 633 | saw_cpu_error = 0; |
1d2f1f90 | 634 | retries = 0; |
3cab0c3e | 635 | prev_sent = 0; |
1d2f1f90 | 636 | do { |
3cab0c3e | 637 | int forward_progress, n_sent; |
1d2f1f90 | 638 | |
b830ab66 DM |
639 | status = sun4v_cpu_mondo_send(cnt, |
640 | tb->cpu_list_pa, | |
641 | tb->cpu_mondo_block_pa); | |
642 | ||
643 | /* HV_EOK means all cpus received the xcall, we're done. */ | |
644 | if (likely(status == HV_EOK)) | |
1d2f1f90 | 645 | break; |
b830ab66 | 646 | |
3cab0c3e DM |
647 | /* First, see if we made any forward progress. |
648 | * | |
649 | * The hypervisor indicates successful sends by setting | |
650 | * cpu list entries to the value 0xffff. | |
b830ab66 | 651 | */ |
3cab0c3e | 652 | n_sent = 0; |
b830ab66 | 653 | for (i = 0; i < cnt; i++) { |
3cab0c3e DM |
654 | if (likely(cpu_list[i] == 0xffff)) |
655 | n_sent++; | |
1d2f1f90 DM |
656 | } |
657 | ||
3cab0c3e DM |
658 | forward_progress = 0; |
659 | if (n_sent > prev_sent) | |
660 | forward_progress = 1; | |
661 | ||
662 | prev_sent = n_sent; | |
663 | ||
b830ab66 DM |
664 | /* If we get a HV_ECPUERROR, then one or more of the cpus |
665 | * in the list are in error state. Use the cpu_state() | |
666 | * hypervisor call to find out which cpus are in error state. | |
667 | */ | |
668 | if (unlikely(status == HV_ECPUERROR)) { | |
669 | for (i = 0; i < cnt; i++) { | |
670 | long err; | |
671 | u16 cpu; | |
672 | ||
673 | cpu = cpu_list[i]; | |
674 | if (cpu == 0xffff) | |
675 | continue; | |
676 | ||
677 | err = sun4v_cpu_state(cpu); | |
ed4d9c66 DM |
678 | if (err == HV_CPU_STATE_ERROR) { |
679 | saw_cpu_error = (cpu + 1); | |
3cab0c3e | 680 | cpu_list[i] = 0xffff; |
b830ab66 DM |
681 | } |
682 | } | |
683 | } else if (unlikely(status != HV_EWOULDBLOCK)) | |
684 | goto fatal_mondo_error; | |
685 | ||
3cab0c3e DM |
686 | /* Don't bother rewriting the CPU list, just leave the |
687 | * 0xffff and non-0xffff entries in there and the | |
688 | * hypervisor will do the right thing. | |
689 | * | |
690 | * Only advance timeout state if we didn't make any | |
691 | * forward progress. | |
692 | */ | |
b830ab66 DM |
693 | if (unlikely(!forward_progress)) { |
694 | if (unlikely(++retries > 10000)) | |
695 | goto fatal_mondo_timeout; | |
696 | ||
697 | /* Delay a little bit to let other cpus catch up | |
698 | * on their cpu mondo queue work. | |
699 | */ | |
700 | udelay(2 * cnt); | |
701 | } | |
1d2f1f90 DM |
702 | } while (1); |
703 | ||
ed4d9c66 | 704 | if (unlikely(saw_cpu_error)) |
b830ab66 DM |
705 | goto fatal_mondo_cpu_error; |
706 | ||
707 | return; | |
708 | ||
709 | fatal_mondo_cpu_error: | |
710 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus " | |
ed4d9c66 DM |
711 | "(including %d) were in error state\n", |
712 | this_cpu, saw_cpu_error - 1); | |
b830ab66 DM |
713 | return; |
714 | ||
715 | fatal_mondo_timeout: | |
b830ab66 DM |
716 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward " |
717 | " progress after %d retries.\n", | |
718 | this_cpu, retries); | |
719 | goto dump_cpu_list_and_out; | |
720 | ||
721 | fatal_mondo_error: | |
b830ab66 DM |
722 | printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n", |
723 | this_cpu, status); | |
724 | printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) " | |
725 | "mondo_block_pa(%lx)\n", | |
726 | this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa); | |
727 | ||
728 | dump_cpu_list_and_out: | |
729 | printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu); | |
730 | for (i = 0; i < cnt; i++) | |
731 | printk("%u ", cpu_list[i]); | |
732 | printk("]\n"); | |
1d2f1f90 | 733 | } |
a43fe0e7 | 734 | |
90f7ae8a | 735 | static void (*xcall_deliver_impl)(struct trap_per_cpu *, int); |
deb16999 DM |
736 | |
737 | static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask) | |
738 | { | |
90f7ae8a DM |
739 | struct trap_per_cpu *tb; |
740 | int this_cpu, i, cnt; | |
c02a5119 | 741 | unsigned long flags; |
90f7ae8a DM |
742 | u16 *cpu_list; |
743 | u64 *mondo; | |
c02a5119 DM |
744 | |
745 | /* We have to do this whole thing with interrupts fully disabled. | |
746 | * Otherwise if we send an xcall from interrupt context it will | |
747 | * corrupt both our mondo block and cpu list state. | |
748 | * | |
749 | * One consequence of this is that we cannot use timeout mechanisms | |
750 | * that depend upon interrupts being delivered locally. So, for | |
751 | * example, we cannot sample jiffies and expect it to advance. | |
752 | * | |
753 | * Fortunately, udelay() uses %stick/%tick so we can use that. | |
754 | */ | |
755 | local_irq_save(flags); | |
90f7ae8a DM |
756 | |
757 | this_cpu = smp_processor_id(); | |
758 | tb = &trap_block[this_cpu]; | |
759 | ||
760 | mondo = __va(tb->cpu_mondo_block_pa); | |
761 | mondo[0] = data0; | |
762 | mondo[1] = data1; | |
763 | mondo[2] = data2; | |
764 | wmb(); | |
765 | ||
766 | cpu_list = __va(tb->cpu_list_pa); | |
767 | ||
768 | /* Setup the initial cpu list. */ | |
769 | cnt = 0; | |
8e757281 | 770 | for_each_cpu(i, mask) { |
90f7ae8a DM |
771 | if (i == this_cpu || !cpu_online(i)) |
772 | continue; | |
773 | cpu_list[cnt++] = i; | |
774 | } | |
775 | ||
776 | if (cnt) | |
777 | xcall_deliver_impl(tb, cnt); | |
778 | ||
c02a5119 | 779 | local_irq_restore(flags); |
deb16999 | 780 | } |
5e0797e5 | 781 | |
91a4231c DM |
782 | /* Send cross call to all processors mentioned in MASK_P |
783 | * except self. Really, there are only two cases currently, | |
fb1fece5 | 784 | * "cpu_online_mask" and "mm_cpumask(mm)". |
1da177e4 | 785 | */ |
ae583885 | 786 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask) |
1da177e4 LT |
787 | { |
788 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
1da177e4 | 789 | |
ae583885 DM |
790 | xcall_deliver(data0, data1, data2, mask); |
791 | } | |
1da177e4 | 792 | |
ae583885 DM |
793 | /* Send cross call to all processors except self. */ |
794 | static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2) | |
795 | { | |
fb1fece5 | 796 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask); |
1da177e4 LT |
797 | } |
798 | ||
799 | extern unsigned long xcall_sync_tick; | |
800 | ||
801 | static void smp_start_sync_tick_client(int cpu) | |
802 | { | |
24445a4a | 803 | xcall_deliver((u64) &xcall_sync_tick, 0, 0, |
fb1fece5 | 804 | cpumask_of(cpu)); |
1da177e4 LT |
805 | } |
806 | ||
1da177e4 LT |
807 | extern unsigned long xcall_call_function; |
808 | ||
f46df02a | 809 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 810 | { |
f46df02a | 811 | xcall_deliver((u64) &xcall_call_function, 0, 0, mask); |
d172ad18 | 812 | } |
1da177e4 | 813 | |
d172ad18 | 814 | extern unsigned long xcall_call_function_single; |
1da177e4 | 815 | |
d172ad18 DM |
816 | void arch_send_call_function_single_ipi(int cpu) |
817 | { | |
19926630 | 818 | xcall_deliver((u64) &xcall_call_function_single, 0, 0, |
fb1fece5 | 819 | cpumask_of(cpu)); |
1da177e4 LT |
820 | } |
821 | ||
9960e9e8 | 822 | void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs) |
1da177e4 | 823 | { |
d172ad18 DM |
824 | clear_softint(1 << irq); |
825 | generic_smp_call_function_interrupt(); | |
826 | } | |
1da177e4 | 827 | |
9960e9e8 | 828 | void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs) |
d172ad18 | 829 | { |
1da177e4 | 830 | clear_softint(1 << irq); |
d172ad18 | 831 | generic_smp_call_function_single_interrupt(); |
1da177e4 LT |
832 | } |
833 | ||
bd40791e DM |
834 | static void tsb_sync(void *info) |
835 | { | |
6f25f398 | 836 | struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()]; |
bd40791e DM |
837 | struct mm_struct *mm = info; |
838 | ||
42b2aa86 | 839 | /* It is not valid to test "current->active_mm == mm" here. |
6f25f398 DM |
840 | * |
841 | * The value of "current" is not changed atomically with | |
842 | * switch_mm(). But that's OK, we just need to check the | |
843 | * current cpu's trap block PGD physical address. | |
844 | */ | |
845 | if (tp->pgd_paddr == __pa(mm->pgd)) | |
bd40791e DM |
846 | tsb_context_switch(mm); |
847 | } | |
848 | ||
849 | void smp_tsb_sync(struct mm_struct *mm) | |
850 | { | |
81f1adf0 | 851 | smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1); |
bd40791e DM |
852 | } |
853 | ||
1da177e4 LT |
854 | extern unsigned long xcall_flush_tlb_mm; |
855 | extern unsigned long xcall_flush_tlb_pending; | |
856 | extern unsigned long xcall_flush_tlb_kernel_range; | |
93dae5b7 | 857 | extern unsigned long xcall_fetch_glob_regs; |
1da177e4 | 858 | extern unsigned long xcall_receive_signal; |
ee29074d | 859 | extern unsigned long xcall_new_mmu_context_version; |
e2fdd7fd DM |
860 | #ifdef CONFIG_KGDB |
861 | extern unsigned long xcall_kgdb_capture; | |
862 | #endif | |
1da177e4 LT |
863 | |
864 | #ifdef DCACHE_ALIASING_POSSIBLE | |
865 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
866 | #endif | |
867 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
868 | ||
869 | #ifdef CONFIG_DEBUG_DCFLUSH | |
870 | extern atomic_t dcpage_flushes; | |
871 | extern atomic_t dcpage_flushes_xcall; | |
872 | #endif | |
873 | ||
d979f179 | 874 | static inline void __local_flush_dcache_page(struct page *page) |
1da177e4 LT |
875 | { |
876 | #ifdef DCACHE_ALIASING_POSSIBLE | |
877 | __flush_dcache_page(page_address(page), | |
878 | ((tlb_type == spitfire) && | |
879 | page_mapping(page) != NULL)); | |
880 | #else | |
881 | if (page_mapping(page) != NULL && | |
882 | tlb_type == spitfire) | |
883 | __flush_icache_page(__pa(page_address(page))); | |
884 | #endif | |
885 | } | |
886 | ||
887 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
888 | { | |
a43fe0e7 DM |
889 | int this_cpu; |
890 | ||
891 | if (tlb_type == hypervisor) | |
892 | return; | |
1da177e4 LT |
893 | |
894 | #ifdef CONFIG_DEBUG_DCFLUSH | |
895 | atomic_inc(&dcpage_flushes); | |
896 | #endif | |
a43fe0e7 DM |
897 | |
898 | this_cpu = get_cpu(); | |
899 | ||
1da177e4 LT |
900 | if (cpu == this_cpu) { |
901 | __local_flush_dcache_page(page); | |
902 | } else if (cpu_online(cpu)) { | |
903 | void *pg_addr = page_address(page); | |
622824db | 904 | u64 data0 = 0; |
1da177e4 LT |
905 | |
906 | if (tlb_type == spitfire) { | |
622824db | 907 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); |
1da177e4 LT |
908 | if (page_mapping(page) != NULL) |
909 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 910 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 | 911 | #ifdef DCACHE_ALIASING_POSSIBLE |
622824db | 912 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); |
1da177e4 LT |
913 | #endif |
914 | } | |
622824db DM |
915 | if (data0) { |
916 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 917 | (u64) pg_addr, cpumask_of(cpu)); |
1da177e4 | 918 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 919 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 920 | #endif |
622824db | 921 | } |
1da177e4 LT |
922 | } |
923 | ||
924 | put_cpu(); | |
925 | } | |
926 | ||
927 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
928 | { | |
622824db | 929 | void *pg_addr; |
622824db | 930 | u64 data0; |
a43fe0e7 DM |
931 | |
932 | if (tlb_type == hypervisor) | |
933 | return; | |
934 | ||
c6fee081 | 935 | preempt_disable(); |
1da177e4 | 936 | |
1da177e4 LT |
937 | #ifdef CONFIG_DEBUG_DCFLUSH |
938 | atomic_inc(&dcpage_flushes); | |
939 | #endif | |
622824db DM |
940 | data0 = 0; |
941 | pg_addr = page_address(page); | |
1da177e4 LT |
942 | if (tlb_type == spitfire) { |
943 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
944 | if (page_mapping(page) != NULL) | |
945 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 946 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
947 | #ifdef DCACHE_ALIASING_POSSIBLE |
948 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
1da177e4 LT |
949 | #endif |
950 | } | |
622824db DM |
951 | if (data0) { |
952 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 953 | (u64) pg_addr, cpu_online_mask); |
1da177e4 | 954 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 955 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 956 | #endif |
622824db | 957 | } |
1da177e4 LT |
958 | __local_flush_dcache_page(page); |
959 | ||
c6fee081 | 960 | preempt_enable(); |
1da177e4 LT |
961 | } |
962 | ||
9960e9e8 | 963 | void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs) |
1da177e4 | 964 | { |
a0663a79 | 965 | struct mm_struct *mm; |
ee29074d | 966 | unsigned long flags; |
a0663a79 | 967 | |
1da177e4 | 968 | clear_softint(1 << irq); |
a0663a79 DM |
969 | |
970 | /* See if we need to allocate a new TLB context because | |
971 | * the version of the one we are using is now out of date. | |
972 | */ | |
973 | mm = current->active_mm; | |
ee29074d DM |
974 | if (unlikely(!mm || (mm == &init_mm))) |
975 | return; | |
a0663a79 | 976 | |
ee29074d | 977 | spin_lock_irqsave(&mm->context.lock, flags); |
aac0aadf | 978 | |
ee29074d DM |
979 | if (unlikely(!CTX_VALID(mm->context))) |
980 | get_new_mmu_context(mm); | |
aac0aadf | 981 | |
ee29074d | 982 | spin_unlock_irqrestore(&mm->context.lock, flags); |
aac0aadf | 983 | |
ee29074d DM |
984 | load_secondary_context(mm); |
985 | __flush_tlb_mm(CTX_HWBITS(mm->context), | |
986 | SECONDARY_CONTEXT); | |
a0663a79 DM |
987 | } |
988 | ||
989 | void smp_new_mmu_context_version(void) | |
990 | { | |
ee29074d | 991 | smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0); |
1da177e4 LT |
992 | } |
993 | ||
e2fdd7fd DM |
994 | #ifdef CONFIG_KGDB |
995 | void kgdb_roundup_cpus(unsigned long flags) | |
996 | { | |
997 | smp_cross_call(&xcall_kgdb_capture, 0, 0, 0); | |
998 | } | |
999 | #endif | |
1000 | ||
93dae5b7 DM |
1001 | void smp_fetch_global_regs(void) |
1002 | { | |
1003 | smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0); | |
1004 | } | |
93dae5b7 | 1005 | |
1da177e4 LT |
1006 | /* We know that the window frames of the user have been flushed |
1007 | * to the stack before we get here because all callers of us | |
1008 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
1009 | * which performs the flushw. | |
1010 | * | |
1011 | * The SMP TLB coherency scheme we use works as follows: | |
1012 | * | |
1013 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
1014 | * space has (potentially) executed on, this is the heuristic | |
1015 | * we use to avoid doing cross calls. | |
1016 | * | |
1017 | * Also, for flushing from kswapd and also for clones, we | |
1018 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
1019 | * | |
1020 | * 2) TLB context numbers are shared globally across all processors | |
1021 | * in the system, this allows us to play several games to avoid | |
1022 | * cross calls. | |
1023 | * | |
1024 | * One invariant is that when a cpu switches to a process, and | |
1025 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
1026 | * current cpu's bit set, that tlb context is flushed locally. | |
1027 | * | |
1028 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
1029 | * cross calls when we want to flush the currently running process's | |
1030 | * tlb state. This is done by clearing all cpu bits except the current | |
f9384d41 | 1031 | * processor's in current->mm->cpu_vm_mask and performing the |
1da177e4 LT |
1032 | * flush locally only. This will force any subsequent cpus which run |
1033 | * this task to flush the context from the local tlb if the process | |
1034 | * migrates to another cpu (again). | |
1035 | * | |
1036 | * 3) For shared address spaces (threads) and swapping we bite the | |
1037 | * bullet for most cases and perform the cross call (but only to | |
1038 | * the cpus listed in cpu_vm_mask). | |
1039 | * | |
1040 | * The performance gain from "optimizing" away the cross call for threads is | |
1041 | * questionable (in theory the big win for threads is the massive sharing of | |
1042 | * address space state across processors). | |
1043 | */ | |
62dbec78 DM |
1044 | |
1045 | /* This currently is only used by the hugetlb arch pre-fault | |
1046 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
1047 | * bits of the context register for an address space. | |
1048 | */ | |
1da177e4 LT |
1049 | void smp_flush_tlb_mm(struct mm_struct *mm) |
1050 | { | |
62dbec78 DM |
1051 | u32 ctx = CTX_HWBITS(mm->context); |
1052 | int cpu = get_cpu(); | |
1da177e4 | 1053 | |
62dbec78 | 1054 | if (atomic_read(&mm->mm_users) == 1) { |
81f1adf0 | 1055 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
62dbec78 DM |
1056 | goto local_flush_and_out; |
1057 | } | |
1da177e4 | 1058 | |
62dbec78 DM |
1059 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
1060 | ctx, 0, 0, | |
81f1adf0 | 1061 | mm_cpumask(mm)); |
1da177e4 | 1062 | |
62dbec78 DM |
1063 | local_flush_and_out: |
1064 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 1065 | |
62dbec78 | 1066 | put_cpu(); |
1da177e4 LT |
1067 | } |
1068 | ||
1069 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) | |
1070 | { | |
1071 | u32 ctx = CTX_HWBITS(mm->context); | |
1072 | int cpu = get_cpu(); | |
1073 | ||
f9384d41 | 1074 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) |
81f1adf0 | 1075 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
dedeb002 HD |
1076 | else |
1077 | smp_cross_call_masked(&xcall_flush_tlb_pending, | |
1078 | ctx, nr, (unsigned long) vaddrs, | |
81f1adf0 | 1079 | mm_cpumask(mm)); |
1da177e4 | 1080 | |
1da177e4 LT |
1081 | __flush_tlb_pending(ctx, nr, vaddrs); |
1082 | ||
1083 | put_cpu(); | |
1084 | } | |
1085 | ||
1086 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
1087 | { | |
1088 | start &= PAGE_MASK; | |
1089 | end = PAGE_ALIGN(end); | |
1090 | if (start != end) { | |
1091 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1092 | 0, start, end); | |
1093 | ||
1094 | __flush_tlb_kernel_range(start, end); | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | /* CPU capture. */ | |
1099 | /* #define CAPTURE_DEBUG */ | |
1100 | extern unsigned long xcall_capture; | |
1101 | ||
1102 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1103 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1104 | static unsigned long penguins_are_doing_time; | |
1105 | ||
1106 | void smp_capture(void) | |
1107 | { | |
1108 | int result = atomic_add_ret(1, &smp_capture_depth); | |
1109 | ||
1110 | if (result == 1) { | |
1111 | int ncpus = num_online_cpus(); | |
1112 | ||
1113 | #ifdef CAPTURE_DEBUG | |
1114 | printk("CPU[%d]: Sending penguins to jail...", | |
1115 | smp_processor_id()); | |
1116 | #endif | |
1117 | penguins_are_doing_time = 1; | |
1da177e4 LT |
1118 | atomic_inc(&smp_capture_registry); |
1119 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1120 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1121 | rmb(); |
1da177e4 LT |
1122 | #ifdef CAPTURE_DEBUG |
1123 | printk("done\n"); | |
1124 | #endif | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | void smp_release(void) | |
1129 | { | |
1130 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1131 | #ifdef CAPTURE_DEBUG | |
1132 | printk("CPU[%d]: Giving pardon to " | |
1133 | "imprisoned penguins\n", | |
1134 | smp_processor_id()); | |
1135 | #endif | |
1136 | penguins_are_doing_time = 0; | |
293666b7 | 1137 | membar_safe("#StoreLoad"); |
1da177e4 LT |
1138 | atomic_dec(&smp_capture_registry); |
1139 | } | |
1140 | } | |
1141 | ||
b4f4372f DM |
1142 | /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE |
1143 | * set, so they can service tlb flush xcalls... | |
1da177e4 LT |
1144 | */ |
1145 | extern void prom_world(int); | |
96c6e0d8 | 1146 | |
9960e9e8 | 1147 | void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1da177e4 | 1148 | { |
1da177e4 LT |
1149 | clear_softint(1 << irq); |
1150 | ||
1151 | preempt_disable(); | |
1152 | ||
1153 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1154 | prom_world(1); |
1155 | atomic_inc(&smp_capture_registry); | |
293666b7 | 1156 | membar_safe("#StoreLoad"); |
1da177e4 | 1157 | while (penguins_are_doing_time) |
4f07118f | 1158 | rmb(); |
1da177e4 LT |
1159 | atomic_dec(&smp_capture_registry); |
1160 | prom_world(0); | |
1161 | ||
1162 | preempt_enable(); | |
1163 | } | |
1164 | ||
1da177e4 | 1165 | /* /proc/profile writes can call this, don't __init it please. */ |
1da177e4 LT |
1166 | int setup_profiling_timer(unsigned int multiplier) |
1167 | { | |
777a4475 | 1168 | return -EINVAL; |
1da177e4 LT |
1169 | } |
1170 | ||
1171 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1172 | { | |
1da177e4 LT |
1173 | } |
1174 | ||
5cbc3073 | 1175 | void __devinit smp_prepare_boot_cpu(void) |
7abea921 | 1176 | { |
7abea921 DM |
1177 | } |
1178 | ||
5e0797e5 DM |
1179 | void __init smp_setup_processor_id(void) |
1180 | { | |
1181 | if (tlb_type == spitfire) | |
deb16999 | 1182 | xcall_deliver_impl = spitfire_xcall_deliver; |
5e0797e5 | 1183 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
deb16999 | 1184 | xcall_deliver_impl = cheetah_xcall_deliver; |
5e0797e5 | 1185 | else |
deb16999 | 1186 | xcall_deliver_impl = hypervisor_xcall_deliver; |
5e0797e5 DM |
1187 | } |
1188 | ||
5cbc3073 | 1189 | void __devinit smp_fill_in_sib_core_maps(void) |
1da177e4 | 1190 | { |
5cbc3073 DM |
1191 | unsigned int i; |
1192 | ||
e0204409 | 1193 | for_each_present_cpu(i) { |
5cbc3073 DM |
1194 | unsigned int j; |
1195 | ||
fb1fece5 | 1196 | cpumask_clear(&cpu_core_map[i]); |
5cbc3073 | 1197 | if (cpu_data(i).core_id == 0) { |
fb1fece5 | 1198 | cpumask_set_cpu(i, &cpu_core_map[i]); |
5cbc3073 DM |
1199 | continue; |
1200 | } | |
1201 | ||
e0204409 | 1202 | for_each_present_cpu(j) { |
5cbc3073 DM |
1203 | if (cpu_data(i).core_id == |
1204 | cpu_data(j).core_id) | |
fb1fece5 | 1205 | cpumask_set_cpu(j, &cpu_core_map[i]); |
f78eae2e DM |
1206 | } |
1207 | } | |
1208 | ||
e0204409 | 1209 | for_each_present_cpu(i) { |
f78eae2e DM |
1210 | unsigned int j; |
1211 | ||
fb1fece5 | 1212 | cpumask_clear(&per_cpu(cpu_sibling_map, i)); |
f78eae2e | 1213 | if (cpu_data(i).proc_id == -1) { |
fb1fece5 | 1214 | cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i)); |
f78eae2e DM |
1215 | continue; |
1216 | } | |
1217 | ||
e0204409 | 1218 | for_each_present_cpu(j) { |
f78eae2e DM |
1219 | if (cpu_data(i).proc_id == |
1220 | cpu_data(j).proc_id) | |
fb1fece5 | 1221 | cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i)); |
5cbc3073 DM |
1222 | } |
1223 | } | |
1da177e4 LT |
1224 | } |
1225 | ||
8239c25f | 1226 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 1227 | { |
f0a2bc7e | 1228 | int ret = smp_boot_one_cpu(cpu, tidle); |
1da177e4 LT |
1229 | |
1230 | if (!ret) { | |
fb1fece5 KM |
1231 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
1232 | while (!cpu_online(cpu)) | |
1da177e4 | 1233 | mb(); |
fb1fece5 | 1234 | if (!cpu_online(cpu)) { |
1da177e4 LT |
1235 | ret = -ENODEV; |
1236 | } else { | |
02fead75 DM |
1237 | /* On SUN4V, writes to %tick and %stick are |
1238 | * not allowed. | |
1239 | */ | |
1240 | if (tlb_type != hypervisor) | |
1241 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1242 | } |
1243 | } | |
1244 | return ret; | |
1245 | } | |
1246 | ||
4f0234f4 | 1247 | #ifdef CONFIG_HOTPLUG_CPU |
e0204409 DM |
1248 | void cpu_play_dead(void) |
1249 | { | |
1250 | int cpu = smp_processor_id(); | |
1251 | unsigned long pstate; | |
1252 | ||
1253 | idle_task_exit(); | |
1254 | ||
1255 | if (tlb_type == hypervisor) { | |
1256 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1257 | ||
1258 | sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO, | |
1259 | tb->cpu_mondo_pa, 0); | |
1260 | sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO, | |
1261 | tb->dev_mondo_pa, 0); | |
1262 | sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR, | |
1263 | tb->resum_mondo_pa, 0); | |
1264 | sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR, | |
1265 | tb->nonresum_mondo_pa, 0); | |
1266 | } | |
1267 | ||
fb1fece5 | 1268 | cpumask_clear_cpu(cpu, &smp_commenced_mask); |
e0204409 DM |
1269 | membar_safe("#Sync"); |
1270 | ||
1271 | local_irq_disable(); | |
1272 | ||
1273 | __asm__ __volatile__( | |
1274 | "rdpr %%pstate, %0\n\t" | |
1275 | "wrpr %0, %1, %%pstate" | |
1276 | : "=r" (pstate) | |
1277 | : "i" (PSTATE_IE)); | |
1278 | ||
1279 | while (1) | |
1280 | barrier(); | |
1281 | } | |
1282 | ||
4f0234f4 DM |
1283 | int __cpu_disable(void) |
1284 | { | |
e0204409 DM |
1285 | int cpu = smp_processor_id(); |
1286 | cpuinfo_sparc *c; | |
1287 | int i; | |
1288 | ||
fb1fece5 KM |
1289 | for_each_cpu(i, &cpu_core_map[cpu]) |
1290 | cpumask_clear_cpu(cpu, &cpu_core_map[i]); | |
1291 | cpumask_clear(&cpu_core_map[cpu]); | |
e0204409 | 1292 | |
fb1fece5 KM |
1293 | for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu)) |
1294 | cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i)); | |
1295 | cpumask_clear(&per_cpu(cpu_sibling_map, cpu)); | |
e0204409 DM |
1296 | |
1297 | c = &cpu_data(cpu); | |
1298 | ||
1299 | c->core_id = 0; | |
1300 | c->proc_id = -1; | |
1301 | ||
e0204409 DM |
1302 | smp_wmb(); |
1303 | ||
1304 | /* Make sure no interrupts point to this cpu. */ | |
1305 | fixup_irqs(); | |
1306 | ||
1307 | local_irq_enable(); | |
1308 | mdelay(1); | |
1309 | local_irq_disable(); | |
1310 | ||
4d084617 | 1311 | ipi_call_lock(); |
fb1fece5 | 1312 | set_cpu_online(cpu, false); |
4d084617 PM |
1313 | ipi_call_unlock(); |
1314 | ||
280ff974 HP |
1315 | cpu_map_rebuild(); |
1316 | ||
e0204409 | 1317 | return 0; |
4f0234f4 DM |
1318 | } |
1319 | ||
1320 | void __cpu_die(unsigned int cpu) | |
1321 | { | |
e0204409 DM |
1322 | int i; |
1323 | ||
1324 | for (i = 0; i < 100; i++) { | |
1325 | smp_rmb(); | |
fb1fece5 | 1326 | if (!cpumask_test_cpu(cpu, &smp_commenced_mask)) |
e0204409 DM |
1327 | break; |
1328 | msleep(100); | |
1329 | } | |
fb1fece5 | 1330 | if (cpumask_test_cpu(cpu, &smp_commenced_mask)) { |
e0204409 DM |
1331 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1332 | } else { | |
1333 | #if defined(CONFIG_SUN_LDOMS) | |
1334 | unsigned long hv_err; | |
1335 | int limit = 100; | |
1336 | ||
1337 | do { | |
1338 | hv_err = sun4v_cpu_stop(cpu); | |
1339 | if (hv_err == HV_EOK) { | |
fb1fece5 | 1340 | set_cpu_present(cpu, false); |
e0204409 DM |
1341 | break; |
1342 | } | |
1343 | } while (--limit > 0); | |
1344 | if (limit <= 0) { | |
1345 | printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n", | |
1346 | hv_err); | |
1347 | } | |
1348 | #endif | |
1349 | } | |
4f0234f4 DM |
1350 | } |
1351 | #endif | |
1352 | ||
1da177e4 LT |
1353 | void __init smp_cpus_done(unsigned int max_cpus) |
1354 | { | |
b62818e5 | 1355 | pcr_arch_init(); |
1da177e4 LT |
1356 | } |
1357 | ||
1da177e4 LT |
1358 | void smp_send_reschedule(int cpu) |
1359 | { | |
19926630 | 1360 | xcall_deliver((u64) &xcall_receive_signal, 0, 0, |
fb1fece5 | 1361 | cpumask_of(cpu)); |
19926630 DM |
1362 | } |
1363 | ||
9960e9e8 | 1364 | void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs) |
19926630 DM |
1365 | { |
1366 | clear_softint(1 << irq); | |
184748cc | 1367 | scheduler_ipi(); |
1da177e4 LT |
1368 | } |
1369 | ||
1370 | /* This is a nop because we capture all other cpus | |
1371 | * anyways when making the PROM active. | |
1372 | */ | |
1373 | void smp_send_stop(void) | |
1374 | { | |
1375 | } | |
1376 | ||
4fd78a5f DM |
1377 | /** |
1378 | * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu | |
1379 | * @cpu: cpu to allocate for | |
1380 | * @size: size allocation in bytes | |
1381 | * @align: alignment | |
1382 | * | |
1383 | * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper | |
1384 | * does the right thing for NUMA regardless of the current | |
1385 | * configuration. | |
1386 | * | |
1387 | * RETURNS: | |
1388 | * Pointer to the allocated area on success, NULL on failure. | |
1389 | */ | |
bcb2107f TH |
1390 | static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size, |
1391 | size_t align) | |
4fd78a5f DM |
1392 | { |
1393 | const unsigned long goal = __pa(MAX_DMA_ADDRESS); | |
1394 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
1395 | int node = cpu_to_node(cpu); | |
1396 | void *ptr; | |
1397 | ||
1398 | if (!node_online(node) || !NODE_DATA(node)) { | |
1399 | ptr = __alloc_bootmem(size, align, goal); | |
1400 | pr_info("cpu %d has no node %d or node-local memory\n", | |
1401 | cpu, node); | |
1402 | pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n", | |
1403 | cpu, size, __pa(ptr)); | |
1404 | } else { | |
1405 | ptr = __alloc_bootmem_node(NODE_DATA(node), | |
1406 | size, align, goal); | |
1407 | pr_debug("per cpu data for cpu%d %lu bytes on node%d at " | |
1408 | "%016lx\n", cpu, size, node, __pa(ptr)); | |
1409 | } | |
1410 | return ptr; | |
1411 | #else | |
1412 | return __alloc_bootmem(size, align, goal); | |
1413 | #endif | |
1414 | } | |
1415 | ||
bcb2107f | 1416 | static void __init pcpu_free_bootmem(void *ptr, size_t size) |
4fd78a5f | 1417 | { |
bcb2107f TH |
1418 | free_bootmem(__pa(ptr), size); |
1419 | } | |
4fd78a5f | 1420 | |
a70c6913 | 1421 | static int __init pcpu_cpu_distance(unsigned int from, unsigned int to) |
bcb2107f TH |
1422 | { |
1423 | if (cpu_to_node(from) == cpu_to_node(to)) | |
1424 | return LOCAL_DISTANCE; | |
1425 | else | |
1426 | return REMOTE_DISTANCE; | |
4fd78a5f DM |
1427 | } |
1428 | ||
a70c6913 TH |
1429 | static void __init pcpu_populate_pte(unsigned long addr) |
1430 | { | |
1431 | pgd_t *pgd = pgd_offset_k(addr); | |
1432 | pud_t *pud; | |
1433 | pmd_t *pmd; | |
1434 | ||
1435 | pud = pud_offset(pgd, addr); | |
1436 | if (pud_none(*pud)) { | |
1437 | pmd_t *new; | |
1438 | ||
1439 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1440 | pud_populate(&init_mm, pud, new); | |
1441 | } | |
1442 | ||
1443 | pmd = pmd_offset(pud, addr); | |
1444 | if (!pmd_present(*pmd)) { | |
1445 | pte_t *new; | |
1446 | ||
1447 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1448 | pmd_populate_kernel(&init_mm, pmd, new); | |
1449 | } | |
1450 | } | |
1451 | ||
73fffc03 | 1452 | void __init setup_per_cpu_areas(void) |
1da177e4 | 1453 | { |
bcb2107f TH |
1454 | unsigned long delta; |
1455 | unsigned int cpu; | |
a70c6913 TH |
1456 | int rc = -EINVAL; |
1457 | ||
1458 | if (pcpu_chosen_fc != PCPU_FC_PAGE) { | |
1459 | rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE, | |
1460 | PERCPU_DYNAMIC_RESERVE, 4 << 20, | |
1461 | pcpu_cpu_distance, | |
1462 | pcpu_alloc_bootmem, | |
1463 | pcpu_free_bootmem); | |
1464 | if (rc) | |
1465 | pr_warning("PERCPU: %s allocator failed (%d), " | |
1466 | "falling back to page size\n", | |
1467 | pcpu_fc_names[pcpu_chosen_fc], rc); | |
1468 | } | |
1469 | if (rc < 0) | |
1470 | rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE, | |
1471 | pcpu_alloc_bootmem, | |
1472 | pcpu_free_bootmem, | |
1473 | pcpu_populate_pte); | |
1474 | if (rc < 0) | |
1475 | panic("cannot initialize percpu area (err=%d)", rc); | |
5a089006 | 1476 | |
4fd78a5f | 1477 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; |
fb435d52 TH |
1478 | for_each_possible_cpu(cpu) |
1479 | __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu]; | |
951bc82c DM |
1480 | |
1481 | /* Setup %g5 for the boot cpu. */ | |
1482 | __local_per_cpu_offset = __per_cpu_offset(smp_processor_id()); | |
b696fdc2 DM |
1483 | |
1484 | of_fill_in_cpu_data(); | |
1485 | if (tlb_type == hypervisor) | |
6ac5c610 | 1486 | mdesc_fill_in_cpu_data(cpu_all_mask); |
1da177e4 | 1487 | } |