Commit | Line | Data |
---|---|---|
e54f8548 | 1 | /* Sparc SS1000/SC2000 SMP support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
4 | * | |
5 | * Based on sun4m's smp.c, which is: | |
6 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
7 | */ | |
8 | ||
1da177e4 | 9 | #include <linux/interrupt.h> |
1da177e4 | 10 | #include <linux/profile.h> |
6c81c32f | 11 | #include <linux/delay.h> |
4245e59d | 12 | #include <linux/cpu.h> |
1da177e4 | 13 | |
1da177e4 | 14 | #include <asm/sbi.h> |
e54f8548 | 15 | #include <asm/mmu.h> |
1da177e4 | 16 | #include <asm/tlbflush.h> |
bde4d8b2 | 17 | #include <asm/switch_to.h> |
1da177e4 | 18 | #include <asm/cacheflush.h> |
1da177e4 | 19 | |
e54f8548 | 20 | #include "kernel.h" |
32231a66 | 21 | #include "irq.h" |
1da177e4 | 22 | |
e54f8548 | 23 | #define IRQ_CROSS_CALL 15 |
1da177e4 | 24 | |
e54f8548 | 25 | static volatile int smp_processors_ready; |
1da177e4 | 26 | static int smp_highest_cpu; |
1da177e4 | 27 | |
a638f25a | 28 | static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val) |
1da177e4 LT |
29 | { |
30 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
31 | "=&r" (val), "=&r" (ptr) : | |
32 | "0" (val), "1" (ptr)); | |
33 | return val; | |
34 | } | |
35 | ||
55dd23ec | 36 | static void smp4d_ipi_init(void); |
1da177e4 | 37 | static void smp_setup_percpu_timer(void); |
1da177e4 | 38 | |
7b1af32f DM |
39 | static unsigned char cpu_leds[32]; |
40 | ||
41 | static inline void show_leds(int cpuid) | |
42 | { | |
43 | cpuid &= 0x1e; | |
44 | __asm__ __volatile__ ("stba %0, [%1] %2" : : | |
45 | "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]), | |
46 | "r" (ECSR_BASE(cpuid) | BB_LEDS), | |
47 | "i" (ASI_M_CTL)); | |
48 | } | |
49 | ||
409832f5 | 50 | void __cpuinit smp4d_callin(void) |
1da177e4 LT |
51 | { |
52 | int cpuid = hard_smp4d_processor_id(); | |
1da177e4 | 53 | unsigned long flags; |
e54f8548 | 54 | |
1da177e4 LT |
55 | /* Show we are alive */ |
56 | cpu_leds[cpuid] = 0x6; | |
57 | show_leds(cpuid); | |
58 | ||
59 | /* Enable level15 interrupt, disable level14 interrupt for now */ | |
60 | cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000); | |
61 | ||
62 | local_flush_cache_all(); | |
63 | local_flush_tlb_all(); | |
64 | ||
e545a614 | 65 | notify_cpu_starting(cpuid); |
1da177e4 LT |
66 | /* |
67 | * Unblock the master CPU _only_ when the scheduler state | |
68 | * of all secondary CPUs will be up-to-date, so after | |
69 | * the SMP initialization the master will be just allowed | |
70 | * to call the scheduler code. | |
71 | */ | |
72 | /* Get our local ticker going. */ | |
73 | smp_setup_percpu_timer(); | |
74 | ||
75 | calibrate_delay(); | |
76 | smp_store_cpu_info(cpuid); | |
77 | local_flush_cache_all(); | |
78 | local_flush_tlb_all(); | |
79 | ||
80 | /* Allow master to continue. */ | |
a638f25a | 81 | sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1); |
1da177e4 LT |
82 | local_flush_cache_all(); |
83 | local_flush_tlb_all(); | |
e54f8548 | 84 | |
e54f8548 | 85 | while ((unsigned long)current_set[cpuid] < PAGE_OFFSET) |
1da177e4 | 86 | barrier(); |
e54f8548 SR |
87 | |
88 | while (current_set[cpuid]->cpu != cpuid) | |
1da177e4 | 89 | barrier(); |
e54f8548 | 90 | |
1da177e4 LT |
91 | /* Fix idle thread fields. */ |
92 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
93 | : : "r" (¤t_set[cpuid]) | |
94 | : "memory" /* paranoid */); | |
95 | ||
96 | cpu_leds[cpuid] = 0x9; | |
97 | show_leds(cpuid); | |
e54f8548 | 98 | |
1da177e4 LT |
99 | /* Attach to the address space of init_task. */ |
100 | atomic_inc(&init_mm.mm_count); | |
101 | current->active_mm = &init_mm; | |
102 | ||
103 | local_flush_cache_all(); | |
104 | local_flush_tlb_all(); | |
e54f8548 | 105 | |
1da177e4 | 106 | local_irq_enable(); /* We don't allow PIL 14 yet */ |
e54f8548 | 107 | |
fb1fece5 | 108 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
1da177e4 LT |
109 | barrier(); |
110 | ||
111 | spin_lock_irqsave(&sun4d_imsk_lock, flags); | |
112 | cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */ | |
113 | spin_unlock_irqrestore(&sun4d_imsk_lock, flags); | |
fe73971c | 114 | set_cpu_online(cpuid, true); |
8b3c848c | 115 | |
1da177e4 LT |
116 | } |
117 | ||
1da177e4 LT |
118 | /* |
119 | * Cycle through the processors asking the PROM to start each one. | |
120 | */ | |
1da177e4 LT |
121 | void __init smp4d_boot_cpus(void) |
122 | { | |
55dd23ec | 123 | smp4d_ipi_init(); |
1da177e4 LT |
124 | if (boot_cpu_id) |
125 | current_set[0] = NULL; | |
1da177e4 LT |
126 | smp_setup_percpu_timer(); |
127 | local_flush_cache_all(); | |
8b3c848c RB |
128 | } |
129 | ||
b4cff846 | 130 | int __cpuinit smp4d_boot_one_cpu(int i) |
8b3c848c | 131 | { |
e54f8548 SR |
132 | unsigned long *entry = &sun4d_cpu_startup; |
133 | struct task_struct *p; | |
134 | int timeout; | |
135 | int cpu_node; | |
1da177e4 | 136 | |
e54f8548 SR |
137 | cpu_find_by_instance(i, &cpu_node, NULL); |
138 | /* Cook up an idler for this guy. */ | |
139 | p = fork_idle(i); | |
140 | current_set[i] = task_thread_info(p); | |
141 | ||
142 | /* | |
143 | * Initialize the contexts table | |
144 | * Since the call to prom_startcpu() trashes the structure, | |
145 | * we need to re-initialize it for each cpu | |
146 | */ | |
147 | smp_penguin_ctable.which_io = 0; | |
148 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
149 | smp_penguin_ctable.reg_size = 0; | |
150 | ||
151 | /* whirrr, whirrr, whirrrrrrrrr... */ | |
152 | printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); | |
153 | local_flush_cache_all(); | |
154 | prom_startcpu(cpu_node, | |
155 | &smp_penguin_ctable, 0, (char *)entry); | |
156 | ||
157 | printk(KERN_INFO "prom_startcpu returned :)\n"); | |
158 | ||
159 | /* wheee... it's going... */ | |
160 | for (timeout = 0; timeout < 10000; timeout++) { | |
161 | if (cpu_callin_map[i]) | |
162 | break; | |
163 | udelay(200); | |
164 | } | |
1da177e4 | 165 | |
8b3c848c | 166 | if (!(cpu_callin_map[i])) { |
e54f8548 | 167 | printk(KERN_ERR "Processor %d is stuck.\n", i); |
8b3c848c RB |
168 | return -ENODEV; |
169 | ||
1da177e4 LT |
170 | } |
171 | local_flush_cache_all(); | |
8b3c848c RB |
172 | return 0; |
173 | } | |
174 | ||
175 | void __init smp4d_smp_done(void) | |
176 | { | |
177 | int i, first; | |
178 | int *prev; | |
179 | ||
180 | /* setup cpu list for irq rotation */ | |
181 | first = 0; | |
182 | prev = &first; | |
ec7c14bd RR |
183 | for_each_online_cpu(i) { |
184 | *prev = i; | |
185 | prev = &cpu_data(i).next; | |
186 | } | |
8b3c848c RB |
187 | *prev = first; |
188 | local_flush_cache_all(); | |
1da177e4 | 189 | |
1da177e4 LT |
190 | /* Ok, they are spinning and ready to go. */ |
191 | smp_processors_ready = 1; | |
192 | sun4d_distribute_irqs(); | |
193 | } | |
194 | ||
55dd23ec DH |
195 | /* Memory structure giving interrupt handler information about IPI generated */ |
196 | struct sun4d_ipi_work { | |
197 | int single; | |
198 | int msk; | |
199 | int resched; | |
200 | }; | |
201 | ||
202 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work); | |
203 | ||
204 | /* Initialize IPIs on the SUN4D SMP machine */ | |
205 | static void __init smp4d_ipi_init(void) | |
206 | { | |
207 | int cpu; | |
208 | struct sun4d_ipi_work *work; | |
209 | ||
210 | printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ); | |
211 | ||
212 | for_each_possible_cpu(cpu) { | |
213 | work = &per_cpu(sun4d_ipi_work, cpu); | |
214 | work->single = work->msk = work->resched = 0; | |
215 | } | |
216 | } | |
217 | ||
218 | void sun4d_ipi_interrupt(void) | |
219 | { | |
220 | struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work); | |
221 | ||
222 | if (work->single) { | |
223 | work->single = 0; | |
224 | smp_call_function_single_interrupt(); | |
225 | } | |
226 | if (work->msk) { | |
227 | work->msk = 0; | |
228 | smp_call_function_interrupt(); | |
229 | } | |
230 | if (work->resched) { | |
231 | work->resched = 0; | |
232 | smp_resched_interrupt(); | |
233 | } | |
234 | } | |
235 | ||
236 | static void smp4d_ipi_single(int cpu) | |
237 | { | |
238 | struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu); | |
239 | ||
240 | /* Mark work */ | |
241 | work->single = 1; | |
242 | ||
243 | /* Generate IRQ on the CPU */ | |
244 | sun4d_send_ipi(cpu, SUN4D_IPI_IRQ); | |
245 | } | |
246 | ||
247 | static void smp4d_ipi_mask_one(int cpu) | |
248 | { | |
249 | struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu); | |
250 | ||
251 | /* Mark work */ | |
252 | work->msk = 1; | |
253 | ||
254 | /* Generate IRQ on the CPU */ | |
255 | sun4d_send_ipi(cpu, SUN4D_IPI_IRQ); | |
256 | } | |
257 | ||
258 | static void smp4d_ipi_resched(int cpu) | |
259 | { | |
260 | struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu); | |
261 | ||
262 | /* Mark work */ | |
263 | work->resched = 1; | |
264 | ||
265 | /* Generate IRQ on the CPU (any IRQ will cause resched) */ | |
266 | sun4d_send_ipi(cpu, SUN4D_IPI_IRQ); | |
267 | } | |
268 | ||
1da177e4 LT |
269 | static struct smp_funcall { |
270 | smpfunc_t func; | |
271 | unsigned long arg1; | |
272 | unsigned long arg2; | |
273 | unsigned long arg3; | |
274 | unsigned long arg4; | |
275 | unsigned long arg5; | |
276 | unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */ | |
277 | unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */ | |
278 | } ccall_info __attribute__((aligned(8))); | |
279 | ||
280 | static DEFINE_SPINLOCK(cross_call_lock); | |
281 | ||
282 | /* Cross calls must be serialized, at least currently. */ | |
66e4f8c0 DM |
283 | static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
284 | unsigned long arg2, unsigned long arg3, | |
285 | unsigned long arg4) | |
1da177e4 | 286 | { |
e54f8548 | 287 | if (smp_processors_ready) { |
1da177e4 LT |
288 | register int high = smp_highest_cpu; |
289 | unsigned long flags; | |
290 | ||
291 | spin_lock_irqsave(&cross_call_lock, flags); | |
292 | ||
293 | { | |
e54f8548 SR |
294 | /* |
295 | * If you make changes here, make sure | |
296 | * gcc generates proper code... | |
297 | */ | |
1da177e4 LT |
298 | register smpfunc_t f asm("i0") = func; |
299 | register unsigned long a1 asm("i1") = arg1; | |
300 | register unsigned long a2 asm("i2") = arg2; | |
301 | register unsigned long a3 asm("i3") = arg3; | |
302 | register unsigned long a4 asm("i4") = arg4; | |
66e4f8c0 | 303 | register unsigned long a5 asm("i5") = 0; |
1da177e4 LT |
304 | |
305 | __asm__ __volatile__( | |
306 | "std %0, [%6]\n\t" | |
307 | "std %2, [%6 + 8]\n\t" | |
308 | "std %4, [%6 + 16]\n\t" : : | |
309 | "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5), | |
310 | "r" (&ccall_info.func)); | |
311 | } | |
312 | ||
313 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
314 | { | |
1da177e4 LT |
315 | register int i; |
316 | ||
fb1fece5 KM |
317 | cpumask_clear_cpu(smp_processor_id(), &mask); |
318 | cpumask_and(&mask, cpu_online_mask, &mask); | |
e54f8548 | 319 | for (i = 0; i <= high; i++) { |
fb1fece5 | 320 | if (cpumask_test_cpu(i, &mask)) { |
1da177e4 LT |
321 | ccall_info.processors_in[i] = 0; |
322 | ccall_info.processors_out[i] = 0; | |
323 | sun4d_send_ipi(i, IRQ_CROSS_CALL); | |
324 | } | |
325 | } | |
326 | } | |
327 | ||
328 | { | |
329 | register int i; | |
330 | ||
331 | i = 0; | |
332 | do { | |
fb1fece5 | 333 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 334 | continue; |
e54f8548 | 335 | while (!ccall_info.processors_in[i]) |
1da177e4 | 336 | barrier(); |
e54f8548 | 337 | } while (++i <= high); |
1da177e4 LT |
338 | |
339 | i = 0; | |
340 | do { | |
fb1fece5 | 341 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 342 | continue; |
e54f8548 | 343 | while (!ccall_info.processors_out[i]) |
1da177e4 | 344 | barrier(); |
e54f8548 | 345 | } while (++i <= high); |
1da177e4 LT |
346 | } |
347 | ||
348 | spin_unlock_irqrestore(&cross_call_lock, flags); | |
349 | } | |
350 | } | |
351 | ||
352 | /* Running cross calls. */ | |
353 | void smp4d_cross_call_irq(void) | |
354 | { | |
355 | int i = hard_smp4d_processor_id(); | |
356 | ||
357 | ccall_info.processors_in[i] = 1; | |
358 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
359 | ccall_info.arg4, ccall_info.arg5); | |
360 | ccall_info.processors_out[i] = 1; | |
361 | } | |
362 | ||
1da177e4 LT |
363 | void smp4d_percpu_timer_interrupt(struct pt_regs *regs) |
364 | { | |
0d84438d | 365 | struct pt_regs *old_regs; |
1da177e4 LT |
366 | int cpu = hard_smp4d_processor_id(); |
367 | static int cpu_tick[NR_CPUS]; | |
368 | static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd }; | |
369 | ||
0d84438d | 370 | old_regs = set_irq_regs(regs); |
e54f8548 | 371 | bw_get_prof_limit(cpu); |
1da177e4 LT |
372 | bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */ |
373 | ||
374 | cpu_tick[cpu]++; | |
375 | if (!(cpu_tick[cpu] & 15)) { | |
376 | if (cpu_tick[cpu] == 0x60) | |
377 | cpu_tick[cpu] = 0; | |
378 | cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4]; | |
379 | show_leds(cpu); | |
380 | } | |
381 | ||
0d84438d | 382 | profile_tick(CPU_PROFILING); |
1da177e4 | 383 | |
e54f8548 | 384 | if (!--prof_counter(cpu)) { |
1da177e4 LT |
385 | int user = user_mode(regs); |
386 | ||
387 | irq_enter(); | |
388 | update_process_times(user); | |
389 | irq_exit(); | |
390 | ||
391 | prof_counter(cpu) = prof_multiplier(cpu); | |
392 | } | |
0d84438d | 393 | set_irq_regs(old_regs); |
1da177e4 LT |
394 | } |
395 | ||
409832f5 | 396 | static void __cpuinit smp_setup_percpu_timer(void) |
1da177e4 LT |
397 | { |
398 | int cpu = hard_smp4d_processor_id(); | |
399 | ||
400 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
401 | load_profile_irq(cpu, lvl14_resolution); | |
402 | } | |
403 | ||
404 | void __init smp4d_blackbox_id(unsigned *addr) | |
405 | { | |
406 | int rd = *addr & 0x3e000000; | |
e54f8548 | 407 | |
1da177e4 | 408 | addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ |
e54f8548 SR |
409 | addr[1] = 0x01000000; /* nop */ |
410 | addr[2] = 0x01000000; /* nop */ | |
1da177e4 LT |
411 | } |
412 | ||
413 | void __init smp4d_blackbox_current(unsigned *addr) | |
414 | { | |
415 | int rd = *addr & 0x3e000000; | |
e54f8548 | 416 | |
1da177e4 LT |
417 | addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ |
418 | addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */ | |
419 | addr[4] = 0x01000000; /* nop */ | |
420 | } | |
421 | ||
422 | void __init sun4d_init_smp(void) | |
423 | { | |
424 | int i; | |
1da177e4 LT |
425 | |
426 | /* Patch ipi15 trap table */ | |
427 | t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m); | |
e54f8548 | 428 | |
1da177e4 LT |
429 | /* And set btfixup... */ |
430 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id); | |
431 | BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current); | |
432 | BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM); | |
1da177e4 | 433 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM); |
55dd23ec DH |
434 | BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM); |
435 | BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM); | |
436 | BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM); | |
e54f8548 | 437 | |
1da177e4 LT |
438 | for (i = 0; i < NR_CPUS; i++) { |
439 | ccall_info.processors_in[i] = 1; | |
440 | ccall_info.processors_out[i] = 1; | |
441 | } | |
442 | } |