[deliverable/linux.git] / arch / sparc / kernel / sun4d_smp.c

/* Sparc SS1000/SC2000 SMP support.
 *
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 *
 * Based on sun4m's smp.c, which is:
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/delay.h>
#include <linux/cpu.h>

#include <asm/sbi.h>
#include <asm/mmu.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>

#include "kernel.h"
#include "irq.h"

#define IRQ_CROSS_CALL		15

static volatile int smp_processors_ready;
static int smp_highest_cpu;

static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp4d_ipi_init(void);
static void smp_setup_percpu_timer(void);

static unsigned char cpu_leds[32];

static inline void show_leds(int cpuid)
{
	cpuid &= 0x1e;
	__asm__ __volatile__ ("stba %0, [%1] %2" : :
			      "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
			      "r" (ECSR_BASE(cpuid) | BB_LEDS),
			      "i" (ASI_M_CTL));
}

void __cpuinit smp4d_callin(void)
{
	int cpuid = hard_smp4d_processor_id();
	unsigned long flags;

	/* Show we are alive */
	cpu_leds[cpuid] = 0x6;
	show_leds(cpuid);

	/* Enable level15 interrupt, disable level14 interrupt for now */
	cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);

	local_flush_cache_all();
	local_flush_tlb_all();

	notify_cpu_starting(cpuid);
	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);
	local_flush_cache_all();
	local_flush_tlb_all();

	/* Allow master to continue. */
	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
	local_flush_cache_all();
	local_flush_tlb_all();

	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
		barrier();

	while (current_set[cpuid]->cpu != cpuid)
		barrier();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	cpu_leds[cpuid] = 0x9;
	show_leds(cpuid);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	local_flush_cache_all();
	local_flush_tlb_all();

	local_irq_enable();	/* We don't allow PIL 14 yet */

	while (!cpu_isset(cpuid, smp_commenced_mask))
		barrier();

	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
	set_cpu_online(cpuid, true);

}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
void __init smp4d_boot_cpus(void)
{
	smp4d_ipi_init();
	if (boot_cpu_id)
		current_set[0] = NULL;
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int __cpuinit smp4d_boot_one_cpu(int i)
{
	unsigned long *entry = &sun4d_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_instance(i, &cpu_node, NULL);
	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	printk(KERN_INFO "prom_startcpu returned :)\n");

	/* wheee... it's going... */
	for (timeout = 0; timeout < 10000; timeout++) {
		if (cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk(KERN_ERR "Processor %d is stuck.\n", i);
		return -ENODEV;

	}
	local_flush_cache_all();
	return 0;
}

void __init smp4d_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for_each_online_cpu(i) {
		*prev = i;
		prev = &cpu_data(i).next;
	}
	*prev = first;
	local_flush_cache_all();

	/* Ok, they are spinning and ready to go. */
	smp_processors_ready = 1;
	sun4d_distribute_irqs();
}

/* Memory structure giving interrupt handler information about IPI generated */
struct sun4d_ipi_work {
	int single;
	int msk;
	int resched;
};

static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);

/* Initialize IPIs on the SUN4D SMP machine */
static void __init smp4d_ipi_init(void)
{
	int cpu;
	struct sun4d_ipi_work *work;

	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);

	for_each_possible_cpu(cpu) {
		work = &per_cpu(sun4d_ipi_work, cpu);
		work->single = work->msk = work->resched = 0;
	}
}

void sun4d_ipi_interrupt(void)
{
	struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);

	if (work->single) {
		work->single = 0;
		smp_call_function_single_interrupt();
	}
	if (work->msk) {
		work->msk = 0;
		smp_call_function_interrupt();
	}
	if (work->resched) {
		work->resched = 0;
		smp_resched_interrupt();
	}
}

static void smp4d_ipi_single(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->single = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void smp4d_ipi_mask_one(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->msk = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void smp4d_ipi_resched(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->resched = 1;

	/* Generate IRQ on the CPU (any IRQ will cause resched) */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned char processors_in[NR_CPUS];  /* Set when ipi entered. */
	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
} ccall_info __attribute__((aligned(8)));

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
	if (smp_processors_ready) {
		register int high = smp_highest_cpu;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		{
			/*
			 * If you make changes here, make sure
			 * gcc generates proper code...
			 */
			register smpfunc_t f asm("i0") = func;
			register unsigned long a1 asm("i1") = arg1;
			register unsigned long a2 asm("i2") = arg2;
			register unsigned long a3 asm("i3") = arg3;
			register unsigned long a4 asm("i4") = arg4;
			register unsigned long a5 asm("i5") = 0;

			__asm__ __volatile__(
				"std %0, [%6]\n\t"
				"std %2, [%6 + 8]\n\t"
				"std %4, [%6 + 16]\n\t" : :
				"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
				"r" (&ccall_info.func));
		}

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpu_clear(smp_processor_id(), mask);
			cpus_and(mask, cpu_online_map, mask);
			for (i = 0; i <= high; i++) {
				if (cpu_isset(i, mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					sun4d_send_ipi(i, IRQ_CROSS_CALL);
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while (!ccall_info.processors_in[i])
					barrier();
			} while (++i <= high);

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while (!ccall_info.processors_out[i])
					barrier();
			} while (++i <= high);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
	}
}

/* Running cross calls. */
void smp4d_cross_call_irq(void)
{
	int i = hard_smp4d_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = hard_smp4d_processor_id();
	static int cpu_tick[NR_CPUS];
	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };

	old_regs = set_irq_regs(regs);
	bw_get_prof_limit(cpu);
	bw_clear_intr_mask(0, 1);	/* INTR_TABLE[0] & 1 is Profile IRQ */

	cpu_tick[cpu]++;
	if (!(cpu_tick[cpu] & 15)) {
		if (cpu_tick[cpu] == 0x60)
			cpu_tick[cpu] = 0;
		cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
		show_leds(cpu);
	}

	profile_tick(CPU_PROFILING);

	if (!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
	set_irq_regs(old_regs);
}

static void __cpuinit smp_setup_percpu_timer(void)
{
	int cpu = hard_smp4d_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);
}

void __init smp4d_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[1] = 0x01000000;			/* nop */
	addr[2] = 0x01000000;			/* nop */
}

void __init smp4d_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[2] = 0x81282002 | rd | (rd >> 11);	/* sll reg, 2, reg */
	addr[4] = 0x01000000;			/* nop */
}

void __init sun4d_init_smp(void)
{
	int i;

	/* Patch ipi15 trap table */
	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);

	/* And set btfixup... */
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);

	for (i = 0; i < NR_CPUS; i++) {
		ccall_info.processors_in[i] = 1;
		ccall_info.processors_out[i] = 1;
	}
}
Commit	Line	Data
e54f8548	1	/* Sparc SS1000/SC2000 SMP support.
1da177e4 LT	2	*
	3	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	4	*
	5	* Based on sun4m's smp.c, which is:
	6	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	7	*/
	8
1da177e4	9	#include <linux/interrupt.h>
1da177e4	10	#include <linux/profile.h>
6c81c32f	11	#include <linux/delay.h>
4245e59d	12	#include <linux/cpu.h>
1da177e4	13
1da177e4	14	#include <asm/sbi.h>
e54f8548	15	#include <asm/mmu.h>
1da177e4 LT	16	#include <asm/tlbflush.h>
1da177e4 LT	17	#include <asm/cacheflush.h>
1da177e4	18
e54f8548	19	#include "kernel.h"
32231a66	20	#include "irq.h"
1da177e4	21
e54f8548	22	#define IRQ_CROSS_CALL 15
1da177e4	23
e54f8548	24	static volatile int smp_processors_ready;
1da177e4	25	static int smp_highest_cpu;
1da177e4	26
a638f25a	27	static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
1da177e4 LT	28	{
	29	__asm__ __volatile__("swap [%1], %0\n\t" :
	30	"=&r" (val), "=&r" (ptr) :
	31	"0" (val), "1" (ptr));
	32	return val;
	33	}
	34
55dd23ec	35	static void smp4d_ipi_init(void);
1da177e4	36	static void smp_setup_percpu_timer(void);
1da177e4	37
7b1af32f DM	38	static unsigned char cpu_leds[32];
	39
	40	static inline void show_leds(int cpuid)
	41	{
	42	cpuid &= 0x1e;
	43	__asm__ __volatile__ ("stba %0, [%1] %2" : :
	44	"r" ((cpu_leds[cpuid] << 4) \| cpu_leds[cpuid+1]),
	45	"r" (ECSR_BASE(cpuid) \| BB_LEDS),
	46	"i" (ASI_M_CTL));
	47	}
	48
409832f5	49	void __cpuinit smp4d_callin(void)
1da177e4 LT	50	{
1da177e4 LT	51	int cpuid = hard_smp4d_processor_id();
1da177e4	52	unsigned long flags;
e54f8548	53
1da177e4 LT	54	/* Show we are alive */
	55	cpu_leds[cpuid] = 0x6;
	56	show_leds(cpuid);
	57
	58	/* Enable level15 interrupt, disable level14 interrupt for now */
	59	cc_set_imsk((cc_get_imsk() & ~0x8000) \| 0x4000);
	60
	61	local_flush_cache_all();
	62	local_flush_tlb_all();
	63
e545a614	64	notify_cpu_starting(cpuid);
1da177e4 LT	65	/*
	66	* Unblock the master CPU _only_ when the scheduler state
	67	* of all secondary CPUs will be up-to-date, so after
	68	* the SMP initialization the master will be just allowed
	69	* to call the scheduler code.
	70	*/
	71	/* Get our local ticker going. */
	72	smp_setup_percpu_timer();
	73
	74	calibrate_delay();
	75	smp_store_cpu_info(cpuid);
	76	local_flush_cache_all();
	77	local_flush_tlb_all();
	78
	79	/* Allow master to continue. */
a638f25a	80	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
1da177e4 LT	81	local_flush_cache_all();
1da177e4 LT	82	local_flush_tlb_all();
e54f8548	83
e54f8548	84	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
1da177e4	85	barrier();
e54f8548 SR	86
e54f8548 SR	87	while (current_set[cpuid]->cpu != cpuid)
1da177e4	88	barrier();
e54f8548	89
1da177e4 LT	90	/* Fix idle thread fields. */
	91	__asm__ __volatile__("ld [%0], %%g6\n\t"
	92	: : "r" (&current_set[cpuid])
	93	: "memory" /* paranoid */);
	94
	95	cpu_leds[cpuid] = 0x9;
	96	show_leds(cpuid);
e54f8548	97
1da177e4 LT	98	/* Attach to the address space of init_task. */
	99	atomic_inc(&init_mm.mm_count);
	100	current->active_mm = &init_mm;
	101
	102	local_flush_cache_all();
	103	local_flush_tlb_all();
e54f8548	104
1da177e4	105	local_irq_enable(); /* We don't allow PIL 14 yet */
e54f8548	106
a54123e2	107	while (!cpu_isset(cpuid, smp_commenced_mask))
1da177e4 LT	108	barrier();
	109
	110	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	111	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	112	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
fe73971c	113	set_cpu_online(cpuid, true);
8b3c848c	114
1da177e4 LT	115	}
1da177e4 LT	116
1da177e4 LT	117	/*
	118	* Cycle through the processors asking the PROM to start each one.
	119	*/
1da177e4 LT	120	void __init smp4d_boot_cpus(void)
1da177e4 LT	121	{
55dd23ec	122	smp4d_ipi_init();
1da177e4 LT	123	if (boot_cpu_id)
1da177e4 LT	124	current_set[0] = NULL;
1da177e4 LT	125	smp_setup_percpu_timer();
1da177e4 LT	126	local_flush_cache_all();
8b3c848c RB	127	}
8b3c848c RB	128
b4cff846	129	int __cpuinit smp4d_boot_one_cpu(int i)
8b3c848c	130	{
e54f8548 SR	131	unsigned long *entry = &sun4d_cpu_startup;
	132	struct task_struct *p;
	133	int timeout;
	134	int cpu_node;
1da177e4	135
e54f8548 SR	136	cpu_find_by_instance(i, &cpu_node, NULL);
	137	/* Cook up an idler for this guy. */
	138	p = fork_idle(i);
	139	current_set[i] = task_thread_info(p);
	140
	141	/*
	142	* Initialize the contexts table
	143	* Since the call to prom_startcpu() trashes the structure,
	144	* we need to re-initialize it for each cpu
	145	*/
	146	smp_penguin_ctable.which_io = 0;
	147	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	148	smp_penguin_ctable.reg_size = 0;
	149
	150	/* whirrr, whirrr, whirrrrrrrrr... */
	151	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	152	local_flush_cache_all();
	153	prom_startcpu(cpu_node,
	154	&smp_penguin_ctable, 0, (char *)entry);
	155
	156	printk(KERN_INFO "prom_startcpu returned :)\n");
	157
	158	/* wheee... it's going... */
	159	for (timeout = 0; timeout < 10000; timeout++) {
	160	if (cpu_callin_map[i])
	161	break;
	162	udelay(200);
	163	}
1da177e4	164
8b3c848c	165	if (!(cpu_callin_map[i])) {
e54f8548	166	printk(KERN_ERR "Processor %d is stuck.\n", i);
8b3c848c RB	167	return -ENODEV;
8b3c848c RB	168
1da177e4 LT	169	}
1da177e4 LT	170	local_flush_cache_all();
8b3c848c RB	171	return 0;
	172	}
	173
	174	void __init smp4d_smp_done(void)
	175	{
	176	int i, first;
	177	int *prev;
	178
	179	/* setup cpu list for irq rotation */
	180	first = 0;
	181	prev = &first;
ec7c14bd RR	182	for_each_online_cpu(i) {
	183	*prev = i;
	184	prev = &cpu_data(i).next;
	185	}
8b3c848c RB	186	*prev = first;
8b3c848c RB	187	local_flush_cache_all();
1da177e4	188
1da177e4 LT	189	/* Ok, they are spinning and ready to go. */
	190	smp_processors_ready = 1;
	191	sun4d_distribute_irqs();
	192	}
	193
55dd23ec DH	194	/* Memory structure giving interrupt handler information about IPI generated */
	195	struct sun4d_ipi_work {
	196	int single;
	197	int msk;
	198	int resched;
	199	};
	200
	201	static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
	202
	203	/* Initialize IPIs on the SUN4D SMP machine */
	204	static void __init smp4d_ipi_init(void)
	205	{
	206	int cpu;
	207	struct sun4d_ipi_work *work;
	208
	209	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
	210
	211	for_each_possible_cpu(cpu) {
	212	work = &per_cpu(sun4d_ipi_work, cpu);
	213	work->single = work->msk = work->resched = 0;
	214	}
	215	}
	216
	217	void sun4d_ipi_interrupt(void)
	218	{
	219	struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
	220
	221	if (work->single) {
	222	work->single = 0;
	223	smp_call_function_single_interrupt();
	224	}
	225	if (work->msk) {
	226	work->msk = 0;
	227	smp_call_function_interrupt();
	228	}
	229	if (work->resched) {
	230	work->resched = 0;
	231	smp_resched_interrupt();
	232	}
	233	}
	234
	235	static void smp4d_ipi_single(int cpu)
	236	{
	237	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	238
	239	/* Mark work */
	240	work->single = 1;
	241
	242	/* Generate IRQ on the CPU */
	243	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	244	}
	245
	246	static void smp4d_ipi_mask_one(int cpu)
	247	{
	248	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	249
	250	/* Mark work */
	251	work->msk = 1;
	252
	253	/* Generate IRQ on the CPU */
	254	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	255	}
	256
	257	static void smp4d_ipi_resched(int cpu)
258	{
259	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
260
261	/* Mark work */
262	work->resched = 1;
263
264	/* Generate IRQ on the CPU (any IRQ will cause resched) */
265	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
266	}
267
1da177e4 LT	268	static struct smp_funcall {
	269	smpfunc_t func;
	270	unsigned long arg1;
	271	unsigned long arg2;
	272	unsigned long arg3;
	273	unsigned long arg4;
	274	unsigned long arg5;
	275	unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
	276	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
	277	} ccall_info __attribute__((aligned(8)));
	278
	279	static DEFINE_SPINLOCK(cross_call_lock);
	280
	281	/* Cross calls must be serialized, at least currently. */
66e4f8c0 DM	282	static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
	283	unsigned long arg2, unsigned long arg3,
	284	unsigned long arg4)
1da177e4	285	{
e54f8548	286	if (smp_processors_ready) {
1da177e4 LT	287	register int high = smp_highest_cpu;
	288	unsigned long flags;
	289
	290	spin_lock_irqsave(&cross_call_lock, flags);
	291
	292	{
e54f8548 SR	293	/*
	294	* If you make changes here, make sure
	295	* gcc generates proper code...
	296	*/
1da177e4 LT	297	register smpfunc_t f asm("i0") = func;
	298	register unsigned long a1 asm("i1") = arg1;
	299	register unsigned long a2 asm("i2") = arg2;
	300	register unsigned long a3 asm("i3") = arg3;
	301	register unsigned long a4 asm("i4") = arg4;
66e4f8c0	302	register unsigned long a5 asm("i5") = 0;
1da177e4 LT	303
	304	__asm__ __volatile__(
	305	"std %0, [%6]\n\t"
	306	"std %2, [%6 + 8]\n\t"
	307	"std %4, [%6 + 16]\n\t" : :
	308	"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
	309	"r" (&ccall_info.func));
	310	}
	311
	312	/* Init receive/complete mapping, plus fire the IPI's off. */
	313	{
1da177e4 LT	314	register int i;
1da177e4 LT	315
66e4f8c0 DM	316	cpu_clear(smp_processor_id(), mask);
66e4f8c0 DM	317	cpus_and(mask, cpu_online_map, mask);
e54f8548	318	for (i = 0; i <= high; i++) {
1da177e4 LT	319	if (cpu_isset(i, mask)) {
	320	ccall_info.processors_in[i] = 0;
	321	ccall_info.processors_out[i] = 0;
	322	sun4d_send_ipi(i, IRQ_CROSS_CALL);
	323	}
	324	}
	325	}
	326
	327	{
	328	register int i;
	329
	330	i = 0;
	331	do {
66e4f8c0 DM	332	if (!cpu_isset(i, mask))
66e4f8c0 DM	333	continue;
e54f8548	334	while (!ccall_info.processors_in[i])
1da177e4	335	barrier();
e54f8548	336	} while (++i <= high);
1da177e4 LT	337
	338	i = 0;
	339	do {
66e4f8c0 DM	340	if (!cpu_isset(i, mask))
66e4f8c0 DM	341	continue;
e54f8548	342	while (!ccall_info.processors_out[i])
1da177e4	343	barrier();
e54f8548	344	} while (++i <= high);
1da177e4 LT	345	}
	346
	347	spin_unlock_irqrestore(&cross_call_lock, flags);
	348	}
	349	}
	350
	351	/* Running cross calls. */
	352	void smp4d_cross_call_irq(void)
	353	{
	354	int i = hard_smp4d_processor_id();
	355
	356	ccall_info.processors_in[i] = 1;
	357	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	358	ccall_info.arg4, ccall_info.arg5);
	359	ccall_info.processors_out[i] = 1;
	360	}
	361
1da177e4 LT	362	void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
1da177e4 LT	363	{
0d84438d	364	struct pt_regs *old_regs;
1da177e4 LT	365	int cpu = hard_smp4d_processor_id();
	366	static int cpu_tick[NR_CPUS];
	367	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
	368
0d84438d	369	old_regs = set_irq_regs(regs);
e54f8548	370	bw_get_prof_limit(cpu);
1da177e4 LT	371	bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
	372
	373	cpu_tick[cpu]++;
	374	if (!(cpu_tick[cpu] & 15)) {
	375	if (cpu_tick[cpu] == 0x60)
	376	cpu_tick[cpu] = 0;
	377	cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
	378	show_leds(cpu);
	379	}
	380
0d84438d	381	profile_tick(CPU_PROFILING);
1da177e4	382
e54f8548	383	if (!--prof_counter(cpu)) {
1da177e4 LT	384	int user = user_mode(regs);
	385
	386	irq_enter();
	387	update_process_times(user);
	388	irq_exit();
	389
	390	prof_counter(cpu) = prof_multiplier(cpu);
	391	}
0d84438d	392	set_irq_regs(old_regs);
1da177e4 LT	393	}
1da177e4 LT	394
409832f5	395	static void __cpuinit smp_setup_percpu_timer(void)
1da177e4 LT	396	{
	397	int cpu = hard_smp4d_processor_id();
	398
	399	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	400	load_profile_irq(cpu, lvl14_resolution);
	401	}
	402
	403	void __init smp4d_blackbox_id(unsigned *addr)
	404	{
	405	int rd = *addr & 0x3e000000;
e54f8548	406
1da177e4	407	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
e54f8548 SR	408	addr[1] = 0x01000000; /* nop */
e54f8548 SR	409	addr[2] = 0x01000000; /* nop */
1da177e4 LT	410	}
	411
	412	void __init smp4d_blackbox_current(unsigned *addr)
	413	{
	414	int rd = *addr & 0x3e000000;
e54f8548	415
1da177e4 LT	416	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
	417	addr[2] = 0x81282002 \| rd \| (rd >> 11); /* sll reg, 2, reg */
	418	addr[4] = 0x01000000; /* nop */
	419	}
	420
	421	void __init sun4d_init_smp(void)
	422	{
	423	int i;
1da177e4 LT	424
	425	/* Patch ipi15 trap table */
	426	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
e54f8548	427
1da177e4 LT	428	/* And set btfixup... */
	429	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	430	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	431	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
1da177e4	432	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
55dd23ec DH	433	BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
	434	BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
	435	BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
e54f8548	436
1da177e4 LT	437	for (i = 0; i < NR_CPUS; i++) {
	438	ccall_info.processors_in[i] = 1;
	439	ccall_info.processors_out[i] = 1;
	440	}
	441	}