[deliverable/linux.git] / arch / sparc / kernel / sun4d_smp.c

/* Sparc SS1000/SC2000 SMP support.
 *
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 *
 * Based on sun4m's smp.c, which is:
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/delay.h>
#include <linux/cpu.h>

#include <asm/cacheflush.h>
#include <asm/switch_to.h>
#include <asm/tlbflush.h>
#include <asm/timer.h>
#include <asm/sbi.h>
#include <asm/mmu.h>

#include "kernel.h"
#include "irq.h"

#define IRQ_CROSS_CALL		15

static volatile int smp_processors_ready;
static int smp_highest_cpu;

static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp4d_ipi_init(void);

static unsigned char cpu_leds[32];

static inline void show_leds(int cpuid)
{
	cpuid &= 0x1e;
	__asm__ __volatile__ ("stba %0, [%1] %2" : :
			      "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
			      "r" (ECSR_BASE(cpuid) | BB_LEDS),
			      "i" (ASI_M_CTL));
}

void __cpuinit smp4d_callin(void)
{
	int cpuid = hard_smp4d_processor_id();
	unsigned long flags;

	/* Show we are alive */
	cpu_leds[cpuid] = 0x6;
	show_leds(cpuid);

	/* Enable level15 interrupt, disable level14 interrupt for now */
	cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);

	local_flush_cache_all();
	local_flush_tlb_all();

	notify_cpu_starting(cpuid);
	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Get our local ticker going. */
	register_percpu_ce(cpuid);

	calibrate_delay();
	smp_store_cpu_info(cpuid);
	local_flush_cache_all();
	local_flush_tlb_all();

	/* Allow master to continue. */
	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
	local_flush_cache_all();
	local_flush_tlb_all();

	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
		barrier();

	while (current_set[cpuid]->cpu != cpuid)
		barrier();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	cpu_leds[cpuid] = 0x9;
	show_leds(cpuid);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	local_flush_cache_all();
	local_flush_tlb_all();

	local_irq_enable();	/* We don't allow PIL 14 yet */

	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
		barrier();

	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
	set_cpu_online(cpuid, true);

}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
void __init smp4d_boot_cpus(void)
{
	smp4d_ipi_init();
	if (boot_cpu_id)
		current_set[0] = NULL;
	local_flush_cache_all();
}

int __cpuinit smp4d_boot_one_cpu(int i)
{
	unsigned long *entry = &sun4d_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_instance(i, &cpu_node, NULL);
	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	printk(KERN_INFO "prom_startcpu returned :)\n");

	/* wheee... it's going... */
	for (timeout = 0; timeout < 10000; timeout++) {
		if (cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk(KERN_ERR "Processor %d is stuck.\n", i);
		return -ENODEV;

	}
	local_flush_cache_all();
	return 0;
}

void __init smp4d_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for_each_online_cpu(i) {
		*prev = i;
		prev = &cpu_data(i).next;
	}
	*prev = first;
	local_flush_cache_all();

	/* Ok, they are spinning and ready to go. */
	smp_processors_ready = 1;
	sun4d_distribute_irqs();
}

/* Memory structure giving interrupt handler information about IPI generated */
struct sun4d_ipi_work {
	int single;
	int msk;
	int resched;
};

static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);

/* Initialize IPIs on the SUN4D SMP machine */
static void __init smp4d_ipi_init(void)
{
	int cpu;
	struct sun4d_ipi_work *work;

	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);

	for_each_possible_cpu(cpu) {
		work = &per_cpu(sun4d_ipi_work, cpu);
		work->single = work->msk = work->resched = 0;
	}
}

void sun4d_ipi_interrupt(void)
{
	struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);

	if (work->single) {
		work->single = 0;
		smp_call_function_single_interrupt();
	}
	if (work->msk) {
		work->msk = 0;
		smp_call_function_interrupt();
	}
	if (work->resched) {
		work->resched = 0;
		smp_resched_interrupt();
	}
}

static void smp4d_ipi_single(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->single = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void smp4d_ipi_mask_one(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->msk = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void smp4d_ipi_resched(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->resched = 1;

	/* Generate IRQ on the CPU (any IRQ will cause resched) */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned char processors_in[NR_CPUS];  /* Set when ipi entered. */
	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
} ccall_info __attribute__((aligned(8)));

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
	if (smp_processors_ready) {
		register int high = smp_highest_cpu;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		{
			/*
			 * If you make changes here, make sure
			 * gcc generates proper code...
			 */
			register smpfunc_t f asm("i0") = func;
			register unsigned long a1 asm("i1") = arg1;
			register unsigned long a2 asm("i2") = arg2;
			register unsigned long a3 asm("i3") = arg3;
			register unsigned long a4 asm("i4") = arg4;
			register unsigned long a5 asm("i5") = 0;

			__asm__ __volatile__(
				"std %0, [%6]\n\t"
				"std %2, [%6 + 8]\n\t"
				"std %4, [%6 + 16]\n\t" : :
				"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
				"r" (&ccall_info.func));
		}

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpumask_clear_cpu(smp_processor_id(), &mask);
			cpumask_and(&mask, cpu_online_mask, &mask);
			for (i = 0; i <= high; i++) {
				if (cpumask_test_cpu(i, &mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					sun4d_send_ipi(i, IRQ_CROSS_CALL);
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpumask_test_cpu(i, &mask))
					continue;
				while (!ccall_info.processors_in[i])
					barrier();
			} while (++i <= high);

			i = 0;
			do {
				if (!cpumask_test_cpu(i, &mask))
					continue;
				while (!ccall_info.processors_out[i])
					barrier();
			} while (++i <= high);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
	}
}

/* Running cross calls. */
void smp4d_cross_call_irq(void)
{
	int i = hard_smp4d_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = hard_smp4d_processor_id();
	struct clock_event_device *ce;
	static int cpu_tick[NR_CPUS];
	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };

	old_regs = set_irq_regs(regs);
	bw_get_prof_limit(cpu);
	bw_clear_intr_mask(0, 1);	/* INTR_TABLE[0] & 1 is Profile IRQ */

	cpu_tick[cpu]++;
	if (!(cpu_tick[cpu] & 15)) {
		if (cpu_tick[cpu] == 0x60)
			cpu_tick[cpu] = 0;
		cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
		show_leds(cpu);
	}

	ce = &per_cpu(sparc32_clockevent, cpu);

	irq_enter();
	ce->event_handler(ce);
	irq_exit();

	set_irq_regs(old_regs);
}

void __init smp4d_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[1] = 0x01000000;			/* nop */
	addr[2] = 0x01000000;			/* nop */
}

void __init smp4d_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[2] = 0x81282002 | rd | (rd >> 11);	/* sll reg, 2, reg */
	addr[4] = 0x01000000;			/* nop */
}

void __init sun4d_init_smp(void)
{
	int i;

	/* Patch ipi15 trap table */
	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);

	/* And set btfixup... */
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);

	for (i = 0; i < NR_CPUS; i++) {
		ccall_info.processors_in[i] = 1;
		ccall_info.processors_out[i] = 1;
	}
}
Commit	Line	Data
e54f8548	1	/* Sparc SS1000/SC2000 SMP support.
1da177e4 LT	2	*
	3	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	4	*
	5	* Based on sun4m's smp.c, which is:
	6	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	7	*/
	8
62f08283	9	#include <linux/clockchips.h>
1da177e4	10	#include <linux/interrupt.h>
1da177e4	11	#include <linux/profile.h>
6c81c32f	12	#include <linux/delay.h>
4245e59d	13	#include <linux/cpu.h>
1da177e4	14
62f08283 TK	15	#include <asm/cacheflush.h>
	16	#include <asm/switch_to.h>
	17	#include <asm/tlbflush.h>
	18	#include <asm/timer.h>
1da177e4	19	#include <asm/sbi.h>
e54f8548	20	#include <asm/mmu.h>
1da177e4	21
e54f8548	22	#include "kernel.h"
32231a66	23	#include "irq.h"
1da177e4	24
e54f8548	25	#define IRQ_CROSS_CALL 15
1da177e4	26
e54f8548	27	static volatile int smp_processors_ready;
1da177e4	28	static int smp_highest_cpu;
1da177e4	29
a638f25a	30	static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
1da177e4 LT	31	{
	32	__asm__ __volatile__("swap [%1], %0\n\t" :
	33	"=&r" (val), "=&r" (ptr) :
	34	"0" (val), "1" (ptr));
	35	return val;
	36	}
	37
55dd23ec	38	static void smp4d_ipi_init(void);
1da177e4	39
7b1af32f DM	40	static unsigned char cpu_leds[32];
	41
	42	static inline void show_leds(int cpuid)
	43	{
	44	cpuid &= 0x1e;
	45	__asm__ __volatile__ ("stba %0, [%1] %2" : :
	46	"r" ((cpu_leds[cpuid] << 4) \| cpu_leds[cpuid+1]),
	47	"r" (ECSR_BASE(cpuid) \| BB_LEDS),
	48	"i" (ASI_M_CTL));
	49	}
	50
409832f5	51	void __cpuinit smp4d_callin(void)
1da177e4 LT	52	{
1da177e4 LT	53	int cpuid = hard_smp4d_processor_id();
1da177e4	54	unsigned long flags;
e54f8548	55
1da177e4 LT	56	/* Show we are alive */
	57	cpu_leds[cpuid] = 0x6;
	58	show_leds(cpuid);
	59
	60	/* Enable level15 interrupt, disable level14 interrupt for now */
	61	cc_set_imsk((cc_get_imsk() & ~0x8000) \| 0x4000);
	62
	63	local_flush_cache_all();
	64	local_flush_tlb_all();
	65
e545a614	66	notify_cpu_starting(cpuid);
1da177e4 LT	67	/*
	68	* Unblock the master CPU _only_ when the scheduler state
	69	* of all secondary CPUs will be up-to-date, so after
	70	* the SMP initialization the master will be just allowed
	71	* to call the scheduler code.
	72	*/
	73	/* Get our local ticker going. */
62f08283	74	register_percpu_ce(cpuid);
1da177e4 LT	75
	76	calibrate_delay();
	77	smp_store_cpu_info(cpuid);
	78	local_flush_cache_all();
	79	local_flush_tlb_all();
	80
	81	/* Allow master to continue. */
a638f25a	82	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
1da177e4 LT	83	local_flush_cache_all();
1da177e4 LT	84	local_flush_tlb_all();
e54f8548	85
e54f8548	86	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
1da177e4	87	barrier();
e54f8548 SR	88
e54f8548 SR	89	while (current_set[cpuid]->cpu != cpuid)
1da177e4	90	barrier();
e54f8548	91
1da177e4 LT	92	/* Fix idle thread fields. */
	93	__asm__ __volatile__("ld [%0], %%g6\n\t"
	94	: : "r" (&current_set[cpuid])
	95	: "memory" /* paranoid */);
	96
	97	cpu_leds[cpuid] = 0x9;
	98	show_leds(cpuid);
e54f8548	99
1da177e4 LT	100	/* Attach to the address space of init_task. */
	101	atomic_inc(&init_mm.mm_count);
	102	current->active_mm = &init_mm;
	103
	104	local_flush_cache_all();
	105	local_flush_tlb_all();
e54f8548	106
1da177e4	107	local_irq_enable(); /* We don't allow PIL 14 yet */
e54f8548	108
fb1fece5	109	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
1da177e4 LT	110	barrier();
	111
	112	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	113	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	114	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
fe73971c	115	set_cpu_online(cpuid, true);
8b3c848c	116
1da177e4 LT	117	}
1da177e4 LT	118
1da177e4 LT	119	/*
	120	* Cycle through the processors asking the PROM to start each one.
	121	*/
1da177e4 LT	122	void __init smp4d_boot_cpus(void)
1da177e4 LT	123	{
55dd23ec	124	smp4d_ipi_init();
1da177e4 LT	125	if (boot_cpu_id)
1da177e4 LT	126	current_set[0] = NULL;
1da177e4	127	local_flush_cache_all();
8b3c848c RB	128	}
8b3c848c RB	129
b4cff846	130	int __cpuinit smp4d_boot_one_cpu(int i)
8b3c848c	131	{
e54f8548 SR	132	unsigned long *entry = &sun4d_cpu_startup;
	133	struct task_struct *p;
	134	int timeout;
	135	int cpu_node;
1da177e4	136
e54f8548 SR	137	cpu_find_by_instance(i, &cpu_node, NULL);
	138	/* Cook up an idler for this guy. */
	139	p = fork_idle(i);
	140	current_set[i] = task_thread_info(p);
	141
	142	/*
	143	* Initialize the contexts table
	144	* Since the call to prom_startcpu() trashes the structure,
	145	* we need to re-initialize it for each cpu
	146	*/
	147	smp_penguin_ctable.which_io = 0;
	148	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	149	smp_penguin_ctable.reg_size = 0;
	150
	151	/* whirrr, whirrr, whirrrrrrrrr... */
	152	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	153	local_flush_cache_all();
	154	prom_startcpu(cpu_node,
	155	&smp_penguin_ctable, 0, (char *)entry);
	156
	157	printk(KERN_INFO "prom_startcpu returned :)\n");
	158
	159	/* wheee... it's going... */
	160	for (timeout = 0; timeout < 10000; timeout++) {
	161	if (cpu_callin_map[i])
	162	break;
	163	udelay(200);
	164	}
1da177e4	165
8b3c848c	166	if (!(cpu_callin_map[i])) {
e54f8548	167	printk(KERN_ERR "Processor %d is stuck.\n", i);
8b3c848c RB	168	return -ENODEV;
8b3c848c RB	169
1da177e4 LT	170	}
1da177e4 LT	171	local_flush_cache_all();
8b3c848c RB	172	return 0;
	173	}
	174
	175	void __init smp4d_smp_done(void)
	176	{
	177	int i, first;
	178	int *prev;
	179
	180	/* setup cpu list for irq rotation */
	181	first = 0;
	182	prev = &first;
ec7c14bd RR	183	for_each_online_cpu(i) {
	184	*prev = i;
	185	prev = &cpu_data(i).next;
	186	}
8b3c848c RB	187	*prev = first;
8b3c848c RB	188	local_flush_cache_all();
1da177e4	189
1da177e4 LT	190	/* Ok, they are spinning and ready to go. */
	191	smp_processors_ready = 1;
	192	sun4d_distribute_irqs();
	193	}
	194
55dd23ec DH	195	/* Memory structure giving interrupt handler information about IPI generated */
	196	struct sun4d_ipi_work {
	197	int single;
	198	int msk;
	199	int resched;
	200	};
	201
	202	static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
	203
	204	/* Initialize IPIs on the SUN4D SMP machine */
	205	static void __init smp4d_ipi_init(void)
	206	{
	207	int cpu;
	208	struct sun4d_ipi_work *work;
	209
	210	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
	211
	212	for_each_possible_cpu(cpu) {
	213	work = &per_cpu(sun4d_ipi_work, cpu);
	214	work->single = work->msk = work->resched = 0;
	215	}
	216	}
	217
	218	void sun4d_ipi_interrupt(void)
	219	{
	220	struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
	221
	222	if (work->single) {
	223	work->single = 0;
	224	smp_call_function_single_interrupt();
	225	}
	226	if (work->msk) {
	227	work->msk = 0;
	228	smp_call_function_interrupt();
	229	}
	230	if (work->resched) {
	231	work->resched = 0;
	232	smp_resched_interrupt();
	233	}
	234	}
	235
	236	static void smp4d_ipi_single(int cpu)
	237	{
	238	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	239
	240	/* Mark work */
	241	work->single = 1;
	242
	243	/* Generate IRQ on the CPU */
	244	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	245	}
	246
	247	static void smp4d_ipi_mask_one(int cpu)
	248	{
	249	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	250
	251	/* Mark work */
	252	work->msk = 1;
	253
	254	/* Generate IRQ on the CPU */
	255	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	256	}
	257
	258	static void smp4d_ipi_resched(int cpu)
259	{
260	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
261
262	/* Mark work */
263	work->resched = 1;
264
265	/* Generate IRQ on the CPU (any IRQ will cause resched) */
266	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
267	}
268
1da177e4 LT	269	static struct smp_funcall {
	270	smpfunc_t func;
	271	unsigned long arg1;
	272	unsigned long arg2;
	273	unsigned long arg3;
	274	unsigned long arg4;
	275	unsigned long arg5;
	276	unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
	277	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
	278	} ccall_info __attribute__((aligned(8)));
	279
	280	static DEFINE_SPINLOCK(cross_call_lock);
	281
	282	/* Cross calls must be serialized, at least currently. */
66e4f8c0 DM	283	static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
	284	unsigned long arg2, unsigned long arg3,
	285	unsigned long arg4)
1da177e4	286	{
e54f8548	287	if (smp_processors_ready) {
1da177e4 LT	288	register int high = smp_highest_cpu;
	289	unsigned long flags;
	290
	291	spin_lock_irqsave(&cross_call_lock, flags);
	292
	293	{
e54f8548 SR	294	/*
	295	* If you make changes here, make sure
	296	* gcc generates proper code...
	297	*/
1da177e4 LT	298	register smpfunc_t f asm("i0") = func;
	299	register unsigned long a1 asm("i1") = arg1;
	300	register unsigned long a2 asm("i2") = arg2;
	301	register unsigned long a3 asm("i3") = arg3;
	302	register unsigned long a4 asm("i4") = arg4;
66e4f8c0	303	register unsigned long a5 asm("i5") = 0;
1da177e4 LT	304
	305	__asm__ __volatile__(
	306	"std %0, [%6]\n\t"
	307	"std %2, [%6 + 8]\n\t"
	308	"std %4, [%6 + 16]\n\t" : :
	309	"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
	310	"r" (&ccall_info.func));
	311	}
	312
	313	/* Init receive/complete mapping, plus fire the IPI's off. */
	314	{
1da177e4 LT	315	register int i;
1da177e4 LT	316
fb1fece5 KM	317	cpumask_clear_cpu(smp_processor_id(), &mask);
fb1fece5 KM	318	cpumask_and(&mask, cpu_online_mask, &mask);
e54f8548	319	for (i = 0; i <= high; i++) {
fb1fece5	320	if (cpumask_test_cpu(i, &mask)) {
1da177e4 LT	321	ccall_info.processors_in[i] = 0;
	322	ccall_info.processors_out[i] = 0;
	323	sun4d_send_ipi(i, IRQ_CROSS_CALL);
	324	}
	325	}
	326	}
	327
	328	{
	329	register int i;
	330
	331	i = 0;
	332	do {
fb1fece5	333	if (!cpumask_test_cpu(i, &mask))
66e4f8c0	334	continue;
e54f8548	335	while (!ccall_info.processors_in[i])
1da177e4	336	barrier();
e54f8548	337	} while (++i <= high);
1da177e4 LT	338
	339	i = 0;
	340	do {
fb1fece5	341	if (!cpumask_test_cpu(i, &mask))
66e4f8c0	342	continue;
e54f8548	343	while (!ccall_info.processors_out[i])
1da177e4	344	barrier();
e54f8548	345	} while (++i <= high);
1da177e4 LT	346	}
	347
	348	spin_unlock_irqrestore(&cross_call_lock, flags);
	349	}
	350	}
	351
	352	/* Running cross calls. */
	353	void smp4d_cross_call_irq(void)
	354	{
	355	int i = hard_smp4d_processor_id();
	356
	357	ccall_info.processors_in[i] = 1;
	358	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	359	ccall_info.arg4, ccall_info.arg5);
	360	ccall_info.processors_out[i] = 1;
	361	}
	362
1da177e4 LT	363	void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
1da177e4 LT	364	{
0d84438d	365	struct pt_regs *old_regs;
1da177e4	366	int cpu = hard_smp4d_processor_id();
62f08283	367	struct clock_event_device *ce;
1da177e4 LT	368	static int cpu_tick[NR_CPUS];
	369	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
	370
0d84438d	371	old_regs = set_irq_regs(regs);
e54f8548	372	bw_get_prof_limit(cpu);
1da177e4 LT	373	bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
	374
	375	cpu_tick[cpu]++;
	376	if (!(cpu_tick[cpu] & 15)) {
	377	if (cpu_tick[cpu] == 0x60)
	378	cpu_tick[cpu] = 0;
	379	cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
	380	show_leds(cpu);
	381	}
	382
62f08283	383	ce = &per_cpu(sparc32_clockevent, cpu);
1da177e4	384
62f08283 TK	385	irq_enter();
	386	ce->event_handler(ce);
	387	irq_exit();
1da177e4	388
0d84438d	389	set_irq_regs(old_regs);
1da177e4 LT	390	}
1da177e4 LT	391
1da177e4 LT	392	void __init smp4d_blackbox_id(unsigned *addr)
	393	{
	394	int rd = *addr & 0x3e000000;
e54f8548	395
1da177e4	396	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
e54f8548 SR	397	addr[1] = 0x01000000; /* nop */
e54f8548 SR	398	addr[2] = 0x01000000; /* nop */
1da177e4 LT	399	}
	400
	401	void __init smp4d_blackbox_current(unsigned *addr)
	402	{
	403	int rd = *addr & 0x3e000000;
e54f8548	404
1da177e4 LT	405	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
	406	addr[2] = 0x81282002 \| rd \| (rd >> 11); /* sll reg, 2, reg */
	407	addr[4] = 0x01000000; /* nop */
	408	}
	409
	410	void __init sun4d_init_smp(void)
	411	{
	412	int i;
1da177e4 LT	413
	414	/* Patch ipi15 trap table */
	415	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
e54f8548	416
1da177e4 LT	417	/* And set btfixup... */
	418	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	419	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	420	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
1da177e4	421	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
55dd23ec DH	422	BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
	423	BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
	424	BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
e54f8548	425
1da177e4 LT	426	for (i = 0; i < NR_CPUS; i++) {
	427	ccall_info.processors_in[i] = 1;
	428	ccall_info.processors_out[i] = 1;
	429	}
	430	}