[deliverable/linux.git] / arch / sparc / kernel / sun4d_smp.c

/* Sparc SS1000/SC2000 SMP support.
 *
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 *
 * Based on sun4m's smp.c, which is:
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/delay.h>
#include <linux/cpu.h>

#include <asm/sbi.h>
#include <asm/mmu.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>

#include "kernel.h"
#include "irq.h"

#define IRQ_CROSS_CALL		15

static volatile int smp_processors_ready;
static int smp_highest_cpu;

static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp_setup_percpu_timer(void);

static unsigned char cpu_leds[32];

static inline void show_leds(int cpuid)
{
	cpuid &= 0x1e;
	__asm__ __volatile__ ("stba %0, [%1] %2" : :
			      "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
			      "r" (ECSR_BASE(cpuid) | BB_LEDS),
			      "i" (ASI_M_CTL));
}

void __cpuinit smp4d_callin(void)
{
	int cpuid = hard_smp4d_processor_id();
	unsigned long flags;

	/* Show we are alive */
	cpu_leds[cpuid] = 0x6;
	show_leds(cpuid);

	/* Enable level15 interrupt, disable level14 interrupt for now */
	cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);

	local_flush_cache_all();
	local_flush_tlb_all();

	notify_cpu_starting(cpuid);
	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);
	local_flush_cache_all();
	local_flush_tlb_all();

	/* Allow master to continue. */
	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
	local_flush_cache_all();
	local_flush_tlb_all();

	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
		barrier();

	while (current_set[cpuid]->cpu != cpuid)
		barrier();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	cpu_leds[cpuid] = 0x9;
	show_leds(cpuid);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	local_flush_cache_all();
	local_flush_tlb_all();

	local_irq_enable();	/* We don't allow PIL 14 yet */

	while (!cpu_isset(cpuid, smp_commenced_mask))
		barrier();

	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
	set_cpu_online(cpuid, true);

}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
void __init smp4d_boot_cpus(void)
{
	if (boot_cpu_id)
		current_set[0] = NULL;
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int __cpuinit smp4d_boot_one_cpu(int i)
{
	unsigned long *entry = &sun4d_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_instance(i, &cpu_node, NULL);
	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	printk(KERN_INFO "prom_startcpu returned :)\n");

	/* wheee... it's going... */
	for (timeout = 0; timeout < 10000; timeout++) {
		if (cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk(KERN_ERR "Processor %d is stuck.\n", i);
		return -ENODEV;

	}
	local_flush_cache_all();
	return 0;
}

void __init smp4d_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for_each_online_cpu(i) {
		*prev = i;
		prev = &cpu_data(i).next;
	}
	*prev = first;
	local_flush_cache_all();

	/* Ok, they are spinning and ready to go. */
	smp_processors_ready = 1;
	sun4d_distribute_irqs();
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned char processors_in[NR_CPUS];  /* Set when ipi entered. */
	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
} ccall_info __attribute__((aligned(8)));

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
	if (smp_processors_ready) {
		register int high = smp_highest_cpu;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		{
			/*
			 * If you make changes here, make sure
			 * gcc generates proper code...
			 */
			register smpfunc_t f asm("i0") = func;
			register unsigned long a1 asm("i1") = arg1;
			register unsigned long a2 asm("i2") = arg2;
			register unsigned long a3 asm("i3") = arg3;
			register unsigned long a4 asm("i4") = arg4;
			register unsigned long a5 asm("i5") = 0;

			__asm__ __volatile__(
				"std %0, [%6]\n\t"
				"std %2, [%6 + 8]\n\t"
				"std %4, [%6 + 16]\n\t" : :
				"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
				"r" (&ccall_info.func));
		}

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpu_clear(smp_processor_id(), mask);
			cpus_and(mask, cpu_online_map, mask);
			for (i = 0; i <= high; i++) {
				if (cpu_isset(i, mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					sun4d_send_ipi(i, IRQ_CROSS_CALL);
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while (!ccall_info.processors_in[i])
					barrier();
			} while (++i <= high);

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while (!ccall_info.processors_out[i])
					barrier();
			} while (++i <= high);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
	}
}

/* Running cross calls. */
void smp4d_cross_call_irq(void)
{
	int i = hard_smp4d_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = hard_smp4d_processor_id();
	static int cpu_tick[NR_CPUS];
	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };

	old_regs = set_irq_regs(regs);
	bw_get_prof_limit(cpu);
	bw_clear_intr_mask(0, 1);	/* INTR_TABLE[0] & 1 is Profile IRQ */

	cpu_tick[cpu]++;
	if (!(cpu_tick[cpu] & 15)) {
		if (cpu_tick[cpu] == 0x60)
			cpu_tick[cpu] = 0;
		cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
		show_leds(cpu);
	}

	profile_tick(CPU_PROFILING);

	if (!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
	set_irq_regs(old_regs);
}

static void __cpuinit smp_setup_percpu_timer(void)
{
	int cpu = hard_smp4d_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);
}

void __init smp4d_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[1] = 0x01000000;			/* nop */
	addr[2] = 0x01000000;			/* nop */
}

void __init smp4d_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[2] = 0x81282002 | rd | (rd >> 11);	/* sll reg, 2, reg */
	addr[4] = 0x01000000;			/* nop */
}

void __init sun4d_init_smp(void)
{
	int i;

	/* Patch ipi15 trap table */
	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);

	/* And set btfixup... */
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);

	for (i = 0; i < NR_CPUS; i++) {
		ccall_info.processors_in[i] = 1;
		ccall_info.processors_out[i] = 1;
	}
}
Commit	Line	Data
e54f8548	1	/* Sparc SS1000/SC2000 SMP support.
1da177e4 LT	2	*
	3	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	4	*
	5	* Based on sun4m's smp.c, which is:
	6	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	7	*/
	8
1da177e4	9	#include <linux/interrupt.h>
1da177e4	10	#include <linux/profile.h>
6c81c32f	11	#include <linux/delay.h>
4245e59d	12	#include <linux/cpu.h>
1da177e4	13
1da177e4	14	#include <asm/sbi.h>
e54f8548	15	#include <asm/mmu.h>
1da177e4 LT	16	#include <asm/tlbflush.h>
1da177e4 LT	17	#include <asm/cacheflush.h>
1da177e4	18
e54f8548	19	#include "kernel.h"
32231a66	20	#include "irq.h"
1da177e4	21
e54f8548	22	#define IRQ_CROSS_CALL 15
1da177e4	23
e54f8548	24	static volatile int smp_processors_ready;
1da177e4	25	static int smp_highest_cpu;
1da177e4	26
a638f25a	27	static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
1da177e4 LT	28	{
	29	__asm__ __volatile__("swap [%1], %0\n\t" :
	30	"=&r" (val), "=&r" (ptr) :
	31	"0" (val), "1" (ptr));
	32	return val;
	33	}
	34
	35	static void smp_setup_percpu_timer(void);
1da177e4	36
7b1af32f DM	37	static unsigned char cpu_leds[32];
	38
	39	static inline void show_leds(int cpuid)
	40	{
	41	cpuid &= 0x1e;
	42	__asm__ __volatile__ ("stba %0, [%1] %2" : :
	43	"r" ((cpu_leds[cpuid] << 4) \| cpu_leds[cpuid+1]),
	44	"r" (ECSR_BASE(cpuid) \| BB_LEDS),
	45	"i" (ASI_M_CTL));
	46	}
	47
409832f5	48	void __cpuinit smp4d_callin(void)
1da177e4 LT	49	{
1da177e4 LT	50	int cpuid = hard_smp4d_processor_id();
1da177e4	51	unsigned long flags;
e54f8548	52
1da177e4 LT	53	/* Show we are alive */
	54	cpu_leds[cpuid] = 0x6;
	55	show_leds(cpuid);
	56
	57	/* Enable level15 interrupt, disable level14 interrupt for now */
	58	cc_set_imsk((cc_get_imsk() & ~0x8000) \| 0x4000);
	59
	60	local_flush_cache_all();
	61	local_flush_tlb_all();
	62
e545a614	63	notify_cpu_starting(cpuid);
1da177e4 LT	64	/*
	65	* Unblock the master CPU _only_ when the scheduler state
	66	* of all secondary CPUs will be up-to-date, so after
	67	* the SMP initialization the master will be just allowed
	68	* to call the scheduler code.
	69	*/
	70	/* Get our local ticker going. */
	71	smp_setup_percpu_timer();
	72
	73	calibrate_delay();
	74	smp_store_cpu_info(cpuid);
	75	local_flush_cache_all();
	76	local_flush_tlb_all();
	77
	78	/* Allow master to continue. */
a638f25a	79	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
1da177e4 LT	80	local_flush_cache_all();
1da177e4 LT	81	local_flush_tlb_all();
e54f8548	82
e54f8548	83	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
1da177e4	84	barrier();
e54f8548 SR	85
e54f8548 SR	86	while (current_set[cpuid]->cpu != cpuid)
1da177e4	87	barrier();
e54f8548	88
1da177e4 LT	89	/* Fix idle thread fields. */
	90	__asm__ __volatile__("ld [%0], %%g6\n\t"
	91	: : "r" (&current_set[cpuid])
	92	: "memory" /* paranoid */);
	93
	94	cpu_leds[cpuid] = 0x9;
	95	show_leds(cpuid);
e54f8548	96
1da177e4 LT	97	/* Attach to the address space of init_task. */
	98	atomic_inc(&init_mm.mm_count);
	99	current->active_mm = &init_mm;
	100
	101	local_flush_cache_all();
	102	local_flush_tlb_all();
e54f8548	103
1da177e4	104	local_irq_enable(); /* We don't allow PIL 14 yet */
e54f8548	105
a54123e2	106	while (!cpu_isset(cpuid, smp_commenced_mask))
1da177e4 LT	107	barrier();
	108
	109	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	110	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	111	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
fe73971c	112	set_cpu_online(cpuid, true);
8b3c848c	113
1da177e4 LT	114	}
1da177e4 LT	115
1da177e4 LT	116	/*
	117	* Cycle through the processors asking the PROM to start each one.
	118	*/
1da177e4 LT	119	void __init smp4d_boot_cpus(void)
1da177e4 LT	120	{
1da177e4 LT	121	if (boot_cpu_id)
1da177e4 LT	122	current_set[0] = NULL;
1da177e4 LT	123	smp_setup_percpu_timer();
1da177e4 LT	124	local_flush_cache_all();
8b3c848c RB	125	}
8b3c848c RB	126
b4cff846	127	int __cpuinit smp4d_boot_one_cpu(int i)
8b3c848c	128	{
e54f8548 SR	129	unsigned long *entry = &sun4d_cpu_startup;
	130	struct task_struct *p;
	131	int timeout;
	132	int cpu_node;
1da177e4	133
e54f8548 SR	134	cpu_find_by_instance(i, &cpu_node, NULL);
	135	/* Cook up an idler for this guy. */
	136	p = fork_idle(i);
	137	current_set[i] = task_thread_info(p);
	138
	139	/*
	140	* Initialize the contexts table
	141	* Since the call to prom_startcpu() trashes the structure,
	142	* we need to re-initialize it for each cpu
	143	*/
	144	smp_penguin_ctable.which_io = 0;
	145	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	146	smp_penguin_ctable.reg_size = 0;
	147
	148	/* whirrr, whirrr, whirrrrrrrrr... */
	149	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	150	local_flush_cache_all();
	151	prom_startcpu(cpu_node,
	152	&smp_penguin_ctable, 0, (char *)entry);
	153
	154	printk(KERN_INFO "prom_startcpu returned :)\n");
	155
	156	/* wheee... it's going... */
	157	for (timeout = 0; timeout < 10000; timeout++) {
	158	if (cpu_callin_map[i])
	159	break;
	160	udelay(200);
	161	}
1da177e4	162
8b3c848c	163	if (!(cpu_callin_map[i])) {
e54f8548	164	printk(KERN_ERR "Processor %d is stuck.\n", i);
8b3c848c RB	165	return -ENODEV;
8b3c848c RB	166
1da177e4 LT	167	}
1da177e4 LT	168	local_flush_cache_all();
8b3c848c RB	169	return 0;
	170	}
	171
	172	void __init smp4d_smp_done(void)
	173	{
	174	int i, first;
	175	int *prev;
	176
	177	/* setup cpu list for irq rotation */
	178	first = 0;
	179	prev = &first;
ec7c14bd RR	180	for_each_online_cpu(i) {
	181	*prev = i;
	182	prev = &cpu_data(i).next;
	183	}
8b3c848c RB	184	*prev = first;
8b3c848c RB	185	local_flush_cache_all();
1da177e4	186
1da177e4 LT	187	/* Ok, they are spinning and ready to go. */
	188	smp_processors_ready = 1;
	189	sun4d_distribute_irqs();
	190	}
	191
	192	static struct smp_funcall {
	193	smpfunc_t func;
	194	unsigned long arg1;
	195	unsigned long arg2;
	196	unsigned long arg3;
	197	unsigned long arg4;
	198	unsigned long arg5;
	199	unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
	200	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
	201	} ccall_info __attribute__((aligned(8)));
	202
	203	static DEFINE_SPINLOCK(cross_call_lock);
	204
	205	/* Cross calls must be serialized, at least currently. */
66e4f8c0 DM	206	static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
	207	unsigned long arg2, unsigned long arg3,
	208	unsigned long arg4)
1da177e4	209	{
e54f8548	210	if (smp_processors_ready) {
1da177e4 LT	211	register int high = smp_highest_cpu;
	212	unsigned long flags;
	213
	214	spin_lock_irqsave(&cross_call_lock, flags);
	215
	216	{
e54f8548 SR	217	/*
	218	* If you make changes here, make sure
	219	* gcc generates proper code...
	220	*/
1da177e4 LT	221	register smpfunc_t f asm("i0") = func;
	222	register unsigned long a1 asm("i1") = arg1;
	223	register unsigned long a2 asm("i2") = arg2;
	224	register unsigned long a3 asm("i3") = arg3;
	225	register unsigned long a4 asm("i4") = arg4;
66e4f8c0	226	register unsigned long a5 asm("i5") = 0;
1da177e4 LT	227
	228	__asm__ __volatile__(
	229	"std %0, [%6]\n\t"
	230	"std %2, [%6 + 8]\n\t"
	231	"std %4, [%6 + 16]\n\t" : :
	232	"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
	233	"r" (&ccall_info.func));
	234	}
	235
	236	/* Init receive/complete mapping, plus fire the IPI's off. */
	237	{
1da177e4 LT	238	register int i;
1da177e4 LT	239
66e4f8c0 DM	240	cpu_clear(smp_processor_id(), mask);
66e4f8c0 DM	241	cpus_and(mask, cpu_online_map, mask);
e54f8548	242	for (i = 0; i <= high; i++) {
1da177e4 LT	243	if (cpu_isset(i, mask)) {
	244	ccall_info.processors_in[i] = 0;
	245	ccall_info.processors_out[i] = 0;
	246	sun4d_send_ipi(i, IRQ_CROSS_CALL);
	247	}
	248	}
	249	}
	250
	251	{
	252	register int i;
	253
	254	i = 0;
	255	do {
66e4f8c0 DM	256	if (!cpu_isset(i, mask))
66e4f8c0 DM	257	continue;
e54f8548	258	while (!ccall_info.processors_in[i])
1da177e4	259	barrier();
e54f8548	260	} while (++i <= high);
1da177e4 LT	261
	262	i = 0;
	263	do {
66e4f8c0 DM	264	if (!cpu_isset(i, mask))
66e4f8c0 DM	265	continue;
e54f8548	266	while (!ccall_info.processors_out[i])
1da177e4	267	barrier();
e54f8548	268	} while (++i <= high);
1da177e4 LT	269	}
	270
	271	spin_unlock_irqrestore(&cross_call_lock, flags);
	272	}
	273	}
	274
	275	/* Running cross calls. */
	276	void smp4d_cross_call_irq(void)
	277	{
	278	int i = hard_smp4d_processor_id();
	279
	280	ccall_info.processors_in[i] = 1;
	281	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	282	ccall_info.arg4, ccall_info.arg5);
	283	ccall_info.processors_out[i] = 1;
	284	}
	285
1da177e4 LT	286	void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
1da177e4 LT	287	{
0d84438d	288	struct pt_regs *old_regs;
1da177e4 LT	289	int cpu = hard_smp4d_processor_id();
	290	static int cpu_tick[NR_CPUS];
	291	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
	292
0d84438d	293	old_regs = set_irq_regs(regs);
e54f8548	294	bw_get_prof_limit(cpu);
1da177e4 LT	295	bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
	296
	297	cpu_tick[cpu]++;
	298	if (!(cpu_tick[cpu] & 15)) {
	299	if (cpu_tick[cpu] == 0x60)
	300	cpu_tick[cpu] = 0;
	301	cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
	302	show_leds(cpu);
	303	}
	304
0d84438d	305	profile_tick(CPU_PROFILING);
1da177e4	306
e54f8548	307	if (!--prof_counter(cpu)) {
1da177e4 LT	308	int user = user_mode(regs);
	309
	310	irq_enter();
	311	update_process_times(user);
	312	irq_exit();
	313
	314	prof_counter(cpu) = prof_multiplier(cpu);
	315	}
0d84438d	316	set_irq_regs(old_regs);
1da177e4 LT	317	}
1da177e4 LT	318
409832f5	319	static void __cpuinit smp_setup_percpu_timer(void)
1da177e4 LT	320	{
	321	int cpu = hard_smp4d_processor_id();
	322
	323	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	324	load_profile_irq(cpu, lvl14_resolution);
	325	}
	326
	327	void __init smp4d_blackbox_id(unsigned *addr)
	328	{
	329	int rd = *addr & 0x3e000000;
e54f8548	330
1da177e4	331	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
e54f8548 SR	332	addr[1] = 0x01000000; /* nop */
e54f8548 SR	333	addr[2] = 0x01000000; /* nop */
1da177e4 LT	334	}
	335
	336	void __init smp4d_blackbox_current(unsigned *addr)
	337	{
	338	int rd = *addr & 0x3e000000;
e54f8548	339
1da177e4 LT	340	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
	341	addr[2] = 0x81282002 \| rd \| (rd >> 11); /* sll reg, 2, reg */
	342	addr[4] = 0x01000000; /* nop */
	343	}
	344
	345	void __init sun4d_init_smp(void)
	346	{
	347	int i;
1da177e4 LT	348
	349	/* Patch ipi15 trap table */
	350	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
e54f8548	351
1da177e4 LT	352	/* And set btfixup... */
	353	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	354	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	355	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
1da177e4	356	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
e54f8548	357
1da177e4 LT	358	for (i = 0; i < NR_CPUS; i++) {
	359	ccall_info.processors_in[i] = 1;
	360	ccall_info.processors_out[i] = 1;
	361	}
	362	}