[deliverable/linux.git] / arch / sparc / kernel / sun4d_smp.c

/* Sparc SS1000/SC2000 SMP support.
 *
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 *
 * Based on sun4m's smp.c, which is:
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/delay.h>
#include <linux/cpu.h>

#include <asm/sbi.h>
#include <asm/mmu.h>
#include <asm/tlbflush.h>
#include <asm/switch_to.h>
#include <asm/cacheflush.h>

#include "kernel.h"
#include "irq.h"

#define IRQ_CROSS_CALL		15

static volatile int smp_processors_ready;
static int smp_highest_cpu;

static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp4d_ipi_init(void);
static void smp_setup_percpu_timer(void);

static unsigned char cpu_leds[32];

static inline void show_leds(int cpuid)
{
	cpuid &= 0x1e;
	__asm__ __volatile__ ("stba %0, [%1] %2" : :
			      "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
			      "r" (ECSR_BASE(cpuid) | BB_LEDS),
			      "i" (ASI_M_CTL));
}

void __cpuinit smp4d_callin(void)
{
	int cpuid = hard_smp4d_processor_id();
	unsigned long flags;

	/* Show we are alive */
	cpu_leds[cpuid] = 0x6;
	show_leds(cpuid);

	/* Enable level15 interrupt, disable level14 interrupt for now */
	cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);

	local_flush_cache_all();
	local_flush_tlb_all();

	notify_cpu_starting(cpuid);
	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);
	local_flush_cache_all();
	local_flush_tlb_all();

	/* Allow master to continue. */
	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
	local_flush_cache_all();
	local_flush_tlb_all();

	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
		barrier();

	while (current_set[cpuid]->cpu != cpuid)
		barrier();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	cpu_leds[cpuid] = 0x9;
	show_leds(cpuid);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	local_flush_cache_all();
	local_flush_tlb_all();

	local_irq_enable();	/* We don't allow PIL 14 yet */

	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
		barrier();

	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
	set_cpu_online(cpuid, true);

}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
void __init smp4d_boot_cpus(void)
{
	smp4d_ipi_init();
	if (boot_cpu_id)
		current_set[0] = NULL;
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int __cpuinit smp4d_boot_one_cpu(int i, struct task_struct *idle)
{
	unsigned long *entry = &sun4d_cpu_startup;
	int timeout;
	int cpu_node;

	cpu_find_by_instance(i, &cpu_node, NULL);
	current_set[i] = task_thread_info(idle);
	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	printk(KERN_INFO "prom_startcpu returned :)\n");

	/* wheee... it's going... */
	for (timeout = 0; timeout < 10000; timeout++) {
		if (cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk(KERN_ERR "Processor %d is stuck.\n", i);
		return -ENODEV;

	}
	local_flush_cache_all();
	return 0;
}

void __init smp4d_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for_each_online_cpu(i) {
		*prev = i;
		prev = &cpu_data(i).next;
	}
	*prev = first;
	local_flush_cache_all();

	/* Ok, they are spinning and ready to go. */
	smp_processors_ready = 1;
	sun4d_distribute_irqs();
}

/* Memory structure giving interrupt handler information about IPI generated */
struct sun4d_ipi_work {
	int single;
	int msk;
	int resched;
};

static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);

/* Initialize IPIs on the SUN4D SMP machine */
static void __init smp4d_ipi_init(void)
{
	int cpu;
	struct sun4d_ipi_work *work;

	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);

	for_each_possible_cpu(cpu) {
		work = &per_cpu(sun4d_ipi_work, cpu);
		work->single = work->msk = work->resched = 0;
	}
}

void sun4d_ipi_interrupt(void)
{
	struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);

	if (work->single) {
		work->single = 0;
		smp_call_function_single_interrupt();
	}
	if (work->msk) {
		work->msk = 0;
		smp_call_function_interrupt();
	}
	if (work->resched) {
		work->resched = 0;
		smp_resched_interrupt();
	}
}

static void smp4d_ipi_single(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->single = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void smp4d_ipi_mask_one(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->msk = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void smp4d_ipi_resched(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->resched = 1;

	/* Generate IRQ on the CPU (any IRQ will cause resched) */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned char processors_in[NR_CPUS];  /* Set when ipi entered. */
	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
} ccall_info __attribute__((aligned(8)));

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
	if (smp_processors_ready) {
		register int high = smp_highest_cpu;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		{
			/*
			 * If you make changes here, make sure
			 * gcc generates proper code...
			 */
			register smpfunc_t f asm("i0") = func;
			register unsigned long a1 asm("i1") = arg1;
			register unsigned long a2 asm("i2") = arg2;
			register unsigned long a3 asm("i3") = arg3;
			register unsigned long a4 asm("i4") = arg4;
			register unsigned long a5 asm("i5") = 0;

			__asm__ __volatile__(
				"std %0, [%6]\n\t"
				"std %2, [%6 + 8]\n\t"
				"std %4, [%6 + 16]\n\t" : :
				"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
				"r" (&ccall_info.func));
		}

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpumask_clear_cpu(smp_processor_id(), &mask);
			cpumask_and(&mask, cpu_online_mask, &mask);
			for (i = 0; i <= high; i++) {
				if (cpumask_test_cpu(i, &mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					sun4d_send_ipi(i, IRQ_CROSS_CALL);
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpumask_test_cpu(i, &mask))
					continue;
				while (!ccall_info.processors_in[i])
					barrier();
			} while (++i <= high);

			i = 0;
			do {
				if (!cpumask_test_cpu(i, &mask))
					continue;
				while (!ccall_info.processors_out[i])
					barrier();
			} while (++i <= high);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
	}
}

/* Running cross calls. */
void smp4d_cross_call_irq(void)
{
	int i = hard_smp4d_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = hard_smp4d_processor_id();
	static int cpu_tick[NR_CPUS];
	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };

	old_regs = set_irq_regs(regs);
	bw_get_prof_limit(cpu);
	bw_clear_intr_mask(0, 1);	/* INTR_TABLE[0] & 1 is Profile IRQ */

	cpu_tick[cpu]++;
	if (!(cpu_tick[cpu] & 15)) {
		if (cpu_tick[cpu] == 0x60)
			cpu_tick[cpu] = 0;
		cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
		show_leds(cpu);
	}

	profile_tick(CPU_PROFILING);

	if (!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
	set_irq_regs(old_regs);
}

static void __cpuinit smp_setup_percpu_timer(void)
{
	int cpu = hard_smp4d_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);
}

void __init smp4d_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[1] = 0x01000000;			/* nop */
	addr[2] = 0x01000000;			/* nop */
}

void __init smp4d_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;

	addr[0] = 0xc0800800 | rd;		/* lda [%g0] ASI_M_VIKING_TMP1, reg */
	addr[2] = 0x81282002 | rd | (rd >> 11);	/* sll reg, 2, reg */
	addr[4] = 0x01000000;			/* nop */
}

void __init sun4d_init_smp(void)
{
	int i;

	/* Patch ipi15 trap table */
	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);

	/* And set btfixup... */
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);

	for (i = 0; i < NR_CPUS; i++) {
		ccall_info.processors_in[i] = 1;
		ccall_info.processors_out[i] = 1;
	}
}
Commit	Line	Data
e54f8548	1	/* Sparc SS1000/SC2000 SMP support.
1da177e4 LT	2	*
	3	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	4	*
	5	* Based on sun4m's smp.c, which is:
	6	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	7	*/
	8
1da177e4	9	#include <linux/interrupt.h>
1da177e4	10	#include <linux/profile.h>
6c81c32f	11	#include <linux/delay.h>
4245e59d	12	#include <linux/cpu.h>
1da177e4	13
1da177e4	14	#include <asm/sbi.h>
e54f8548	15	#include <asm/mmu.h>
1da177e4	16	#include <asm/tlbflush.h>
bde4d8b2	17	#include <asm/switch_to.h>
1da177e4	18	#include <asm/cacheflush.h>
1da177e4	19
e54f8548	20	#include "kernel.h"
32231a66	21	#include "irq.h"
1da177e4	22
e54f8548	23	#define IRQ_CROSS_CALL 15
1da177e4	24
e54f8548	25	static volatile int smp_processors_ready;
1da177e4	26	static int smp_highest_cpu;
1da177e4	27
a638f25a	28	static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
1da177e4 LT	29	{
	30	__asm__ __volatile__("swap [%1], %0\n\t" :
	31	"=&r" (val), "=&r" (ptr) :
	32	"0" (val), "1" (ptr));
	33	return val;
	34	}
	35
55dd23ec	36	static void smp4d_ipi_init(void);
1da177e4	37	static void smp_setup_percpu_timer(void);
1da177e4	38
7b1af32f DM	39	static unsigned char cpu_leds[32];
	40
	41	static inline void show_leds(int cpuid)
	42	{
	43	cpuid &= 0x1e;
	44	__asm__ __volatile__ ("stba %0, [%1] %2" : :
	45	"r" ((cpu_leds[cpuid] << 4) \| cpu_leds[cpuid+1]),
	46	"r" (ECSR_BASE(cpuid) \| BB_LEDS),
	47	"i" (ASI_M_CTL));
	48	}
	49
409832f5	50	void __cpuinit smp4d_callin(void)
1da177e4 LT	51	{
1da177e4 LT	52	int cpuid = hard_smp4d_processor_id();
1da177e4	53	unsigned long flags;
e54f8548	54
1da177e4 LT	55	/* Show we are alive */
	56	cpu_leds[cpuid] = 0x6;
	57	show_leds(cpuid);
	58
	59	/* Enable level15 interrupt, disable level14 interrupt for now */
	60	cc_set_imsk((cc_get_imsk() & ~0x8000) \| 0x4000);
	61
	62	local_flush_cache_all();
	63	local_flush_tlb_all();
	64
e545a614	65	notify_cpu_starting(cpuid);
1da177e4 LT	66	/*
	67	* Unblock the master CPU _only_ when the scheduler state
	68	* of all secondary CPUs will be up-to-date, so after
	69	* the SMP initialization the master will be just allowed
	70	* to call the scheduler code.
	71	*/
	72	/* Get our local ticker going. */
	73	smp_setup_percpu_timer();
	74
	75	calibrate_delay();
	76	smp_store_cpu_info(cpuid);
	77	local_flush_cache_all();
	78	local_flush_tlb_all();
	79
	80	/* Allow master to continue. */
a638f25a	81	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
1da177e4 LT	82	local_flush_cache_all();
1da177e4 LT	83	local_flush_tlb_all();
e54f8548	84
e54f8548	85	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
1da177e4	86	barrier();
e54f8548 SR	87
e54f8548 SR	88	while (current_set[cpuid]->cpu != cpuid)
1da177e4	89	barrier();
e54f8548	90
1da177e4 LT	91	/* Fix idle thread fields. */
	92	__asm__ __volatile__("ld [%0], %%g6\n\t"
	93	: : "r" (&current_set[cpuid])
	94	: "memory" /* paranoid */);
	95
	96	cpu_leds[cpuid] = 0x9;
	97	show_leds(cpuid);
e54f8548	98
1da177e4 LT	99	/* Attach to the address space of init_task. */
	100	atomic_inc(&init_mm.mm_count);
	101	current->active_mm = &init_mm;
	102
	103	local_flush_cache_all();
	104	local_flush_tlb_all();
e54f8548	105
1da177e4	106	local_irq_enable(); /* We don't allow PIL 14 yet */
e54f8548	107
fb1fece5	108	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
1da177e4 LT	109	barrier();
	110
	111	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	112	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	113	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
fe73971c	114	set_cpu_online(cpuid, true);
8b3c848c	115
1da177e4 LT	116	}
1da177e4 LT	117
1da177e4 LT	118	/*
	119	* Cycle through the processors asking the PROM to start each one.
	120	*/
1da177e4 LT	121	void __init smp4d_boot_cpus(void)
1da177e4 LT	122	{
55dd23ec	123	smp4d_ipi_init();
1da177e4 LT	124	if (boot_cpu_id)
1da177e4 LT	125	current_set[0] = NULL;
1da177e4 LT	126	smp_setup_percpu_timer();
1da177e4 LT	127	local_flush_cache_all();
8b3c848c RB	128	}
8b3c848c RB	129
f0a2bc7e	130	int __cpuinit smp4d_boot_one_cpu(int i, struct task_struct *idle)
8b3c848c	131	{
e54f8548	132	unsigned long *entry = &sun4d_cpu_startup;
e54f8548 SR	133	int timeout;
e54f8548 SR	134	int cpu_node;
1da177e4	135
e54f8548	136	cpu_find_by_instance(i, &cpu_node, NULL);
f0a2bc7e	137	current_set[i] = task_thread_info(idle);
e54f8548 SR	138	/*
	139	* Initialize the contexts table
	140	* Since the call to prom_startcpu() trashes the structure,
	141	* we need to re-initialize it for each cpu
	142	*/
	143	smp_penguin_ctable.which_io = 0;
	144	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	145	smp_penguin_ctable.reg_size = 0;
	146
	147	/* whirrr, whirrr, whirrrrrrrrr... */
	148	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	149	local_flush_cache_all();
	150	prom_startcpu(cpu_node,
	151	&smp_penguin_ctable, 0, (char *)entry);
	152
	153	printk(KERN_INFO "prom_startcpu returned :)\n");
	154
	155	/* wheee... it's going... */
	156	for (timeout = 0; timeout < 10000; timeout++) {
	157	if (cpu_callin_map[i])
	158	break;
	159	udelay(200);
	160	}
1da177e4	161
8b3c848c	162	if (!(cpu_callin_map[i])) {
e54f8548	163	printk(KERN_ERR "Processor %d is stuck.\n", i);
8b3c848c RB	164	return -ENODEV;
8b3c848c RB	165
1da177e4 LT	166	}
1da177e4 LT	167	local_flush_cache_all();
8b3c848c RB	168	return 0;
	169	}
	170
	171	void __init smp4d_smp_done(void)
	172	{
	173	int i, first;
	174	int *prev;
	175
	176	/* setup cpu list for irq rotation */
	177	first = 0;
	178	prev = &first;
ec7c14bd RR	179	for_each_online_cpu(i) {
	180	*prev = i;
	181	prev = &cpu_data(i).next;
	182	}
8b3c848c RB	183	*prev = first;
8b3c848c RB	184	local_flush_cache_all();
1da177e4	185
1da177e4 LT	186	/* Ok, they are spinning and ready to go. */
	187	smp_processors_ready = 1;
	188	sun4d_distribute_irqs();
	189	}
	190
55dd23ec DH	191	/* Memory structure giving interrupt handler information about IPI generated */
	192	struct sun4d_ipi_work {
	193	int single;
	194	int msk;
	195	int resched;
	196	};
	197
	198	static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
	199
	200	/* Initialize IPIs on the SUN4D SMP machine */
	201	static void __init smp4d_ipi_init(void)
	202	{
	203	int cpu;
	204	struct sun4d_ipi_work *work;
	205
	206	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
	207
	208	for_each_possible_cpu(cpu) {
	209	work = &per_cpu(sun4d_ipi_work, cpu);
	210	work->single = work->msk = work->resched = 0;
	211	}
	212	}
	213
	214	void sun4d_ipi_interrupt(void)
	215	{
	216	struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
	217
	218	if (work->single) {
	219	work->single = 0;
	220	smp_call_function_single_interrupt();
	221	}
	222	if (work->msk) {
	223	work->msk = 0;
	224	smp_call_function_interrupt();
	225	}
	226	if (work->resched) {
	227	work->resched = 0;
	228	smp_resched_interrupt();
	229	}
	230	}
	231
	232	static void smp4d_ipi_single(int cpu)
	233	{
	234	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	235
	236	/* Mark work */
	237	work->single = 1;
	238
	239	/* Generate IRQ on the CPU */
	240	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	241	}
	242
	243	static void smp4d_ipi_mask_one(int cpu)
	244	{
	245	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	246
	247	/* Mark work */
	248	work->msk = 1;
	249
	250	/* Generate IRQ on the CPU */
	251	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	252	}
	253
	254	static void smp4d_ipi_resched(int cpu)
255	{
256	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
257
258	/* Mark work */
259	work->resched = 1;
260
261	/* Generate IRQ on the CPU (any IRQ will cause resched) */
262	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
263	}
264
1da177e4 LT	265	static struct smp_funcall {
	266	smpfunc_t func;
	267	unsigned long arg1;
	268	unsigned long arg2;
	269	unsigned long arg3;
	270	unsigned long arg4;
	271	unsigned long arg5;
	272	unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
	273	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
	274	} ccall_info __attribute__((aligned(8)));
	275
	276	static DEFINE_SPINLOCK(cross_call_lock);
	277
	278	/* Cross calls must be serialized, at least currently. */
66e4f8c0 DM	279	static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
	280	unsigned long arg2, unsigned long arg3,
	281	unsigned long arg4)
1da177e4	282	{
e54f8548	283	if (smp_processors_ready) {
1da177e4 LT	284	register int high = smp_highest_cpu;
	285	unsigned long flags;
	286
	287	spin_lock_irqsave(&cross_call_lock, flags);
	288
	289	{
e54f8548 SR	290	/*
	291	* If you make changes here, make sure
	292	* gcc generates proper code...
	293	*/
1da177e4 LT	294	register smpfunc_t f asm("i0") = func;
	295	register unsigned long a1 asm("i1") = arg1;
	296	register unsigned long a2 asm("i2") = arg2;
	297	register unsigned long a3 asm("i3") = arg3;
	298	register unsigned long a4 asm("i4") = arg4;
66e4f8c0	299	register unsigned long a5 asm("i5") = 0;
1da177e4 LT	300
	301	__asm__ __volatile__(
	302	"std %0, [%6]\n\t"
	303	"std %2, [%6 + 8]\n\t"
	304	"std %4, [%6 + 16]\n\t" : :
	305	"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
	306	"r" (&ccall_info.func));
	307	}
	308
	309	/* Init receive/complete mapping, plus fire the IPI's off. */
	310	{
1da177e4 LT	311	register int i;
1da177e4 LT	312
fb1fece5 KM	313	cpumask_clear_cpu(smp_processor_id(), &mask);
fb1fece5 KM	314	cpumask_and(&mask, cpu_online_mask, &mask);
e54f8548	315	for (i = 0; i <= high; i++) {
fb1fece5	316	if (cpumask_test_cpu(i, &mask)) {
1da177e4 LT	317	ccall_info.processors_in[i] = 0;
	318	ccall_info.processors_out[i] = 0;
	319	sun4d_send_ipi(i, IRQ_CROSS_CALL);
	320	}
	321	}
	322	}
	323
	324	{
	325	register int i;
	326
	327	i = 0;
	328	do {
fb1fece5	329	if (!cpumask_test_cpu(i, &mask))
66e4f8c0	330	continue;
e54f8548	331	while (!ccall_info.processors_in[i])
1da177e4	332	barrier();
e54f8548	333	} while (++i <= high);
1da177e4 LT	334
	335	i = 0;
	336	do {
fb1fece5	337	if (!cpumask_test_cpu(i, &mask))
66e4f8c0	338	continue;
e54f8548	339	while (!ccall_info.processors_out[i])
1da177e4	340	barrier();
e54f8548	341	} while (++i <= high);
1da177e4 LT	342	}
	343
	344	spin_unlock_irqrestore(&cross_call_lock, flags);
	345	}
	346	}
	347
	348	/* Running cross calls. */
	349	void smp4d_cross_call_irq(void)
	350	{
	351	int i = hard_smp4d_processor_id();
	352
	353	ccall_info.processors_in[i] = 1;
	354	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	355	ccall_info.arg4, ccall_info.arg5);
	356	ccall_info.processors_out[i] = 1;
	357	}
	358
1da177e4 LT	359	void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
1da177e4 LT	360	{
0d84438d	361	struct pt_regs *old_regs;
1da177e4 LT	362	int cpu = hard_smp4d_processor_id();
	363	static int cpu_tick[NR_CPUS];
	364	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
	365
0d84438d	366	old_regs = set_irq_regs(regs);
e54f8548	367	bw_get_prof_limit(cpu);
1da177e4 LT	368	bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
	369
	370	cpu_tick[cpu]++;
	371	if (!(cpu_tick[cpu] & 15)) {
	372	if (cpu_tick[cpu] == 0x60)
	373	cpu_tick[cpu] = 0;
	374	cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
	375	show_leds(cpu);
	376	}
	377
0d84438d	378	profile_tick(CPU_PROFILING);
1da177e4	379
e54f8548	380	if (!--prof_counter(cpu)) {
1da177e4 LT	381	int user = user_mode(regs);
	382
	383	irq_enter();
	384	update_process_times(user);
	385	irq_exit();
	386
	387	prof_counter(cpu) = prof_multiplier(cpu);
	388	}
0d84438d	389	set_irq_regs(old_regs);
1da177e4 LT	390	}
1da177e4 LT	391
409832f5	392	static void __cpuinit smp_setup_percpu_timer(void)
1da177e4 LT	393	{
	394	int cpu = hard_smp4d_processor_id();
	395
	396	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	397	load_profile_irq(cpu, lvl14_resolution);
	398	}
	399
	400	void __init smp4d_blackbox_id(unsigned *addr)
	401	{
	402	int rd = *addr & 0x3e000000;
e54f8548	403
1da177e4	404	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
e54f8548 SR	405	addr[1] = 0x01000000; /* nop */
e54f8548 SR	406	addr[2] = 0x01000000; /* nop */
1da177e4 LT	407	}
	408
	409	void __init smp4d_blackbox_current(unsigned *addr)
	410	{
	411	int rd = *addr & 0x3e000000;
e54f8548	412
1da177e4 LT	413	addr[0] = 0xc0800800 \| rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
	414	addr[2] = 0x81282002 \| rd \| (rd >> 11); /* sll reg, 2, reg */
	415	addr[4] = 0x01000000; /* nop */
	416	}
	417
	418	void __init sun4d_init_smp(void)
	419	{
	420	int i;
1da177e4 LT	421
	422	/* Patch ipi15 trap table */
	423	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
e54f8548	424
1da177e4 LT	425	/* And set btfixup... */
	426	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
	427	BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
	428	BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
1da177e4	429	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
55dd23ec DH	430	BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
	431	BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
	432	BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
e54f8548	433
1da177e4 LT	434	for (i = 0; i < NR_CPUS; i++) {
	435	ccall_info.processors_in[i] = 1;
	436	ccall_info.processors_out[i] = 1;
	437	}
	438	}