Commit | Line | Data |
---|---|---|
aba20a82 SR |
1 | /* |
2 | * sun4m irq support | |
1da177e4 LT |
3 | * |
4 | * djhr: Hacked out of irq.c into a CPU dependent version. | |
5 | * | |
6 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
7 | * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
8 | * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com) | |
9 | * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk) | |
10 | */ | |
11 | ||
a755180b SR |
12 | #include <linux/slab.h> |
13 | ||
1da177e4 | 14 | #include <asm/timer.h> |
1da177e4 LT |
15 | #include <asm/traps.h> |
16 | #include <asm/pgalloc.h> | |
17 | #include <asm/pgtable.h> | |
1da177e4 LT |
18 | #include <asm/irq.h> |
19 | #include <asm/io.h> | |
1da177e4 LT |
20 | #include <asm/cacheflush.h> |
21 | ||
32231a66 | 22 | #include "irq.h" |
aba20a82 SR |
23 | #include "kernel.h" |
24 | ||
25 | /* Sample sun4m IRQ layout: | |
26 | * | |
27 | * 0x22 - Power | |
28 | * 0x24 - ESP SCSI | |
29 | * 0x26 - Lance ethernet | |
30 | * 0x2b - Floppy | |
31 | * 0x2c - Zilog uart | |
32 | * 0x32 - SBUS level 0 | |
33 | * 0x33 - Parallel port, SBUS level 1 | |
34 | * 0x35 - SBUS level 2 | |
35 | * 0x37 - SBUS level 3 | |
36 | * 0x39 - Audio, Graphics card, SBUS level 4 | |
37 | * 0x3b - SBUS level 5 | |
38 | * 0x3d - SBUS level 6 | |
39 | * | |
40 | * Each interrupt source has a mask bit in the interrupt registers. | |
41 | * When the mask bit is set, this blocks interrupt deliver. So you | |
42 | * clear the bit to enable the interrupt. | |
43 | * | |
44 | * Interrupts numbered less than 0x10 are software triggered interrupts | |
45 | * and unused by Linux. | |
46 | * | |
47 | * Interrupt level assignment on sun4m: | |
48 | * | |
49 | * level source | |
50 | * ------------------------------------------------------------ | |
51 | * 1 softint-1 | |
52 | * 2 softint-2, VME/SBUS level 1 | |
53 | * 3 softint-3, VME/SBUS level 2 | |
54 | * 4 softint-4, onboard SCSI | |
55 | * 5 softint-5, VME/SBUS level 3 | |
56 | * 6 softint-6, onboard ETHERNET | |
57 | * 7 softint-7, VME/SBUS level 4 | |
58 | * 8 softint-8, onboard VIDEO | |
59 | * 9 softint-9, VME/SBUS level 5, Module Interrupt | |
60 | * 10 softint-10, system counter/timer | |
61 | * 11 softint-11, VME/SBUS level 6, Floppy | |
62 | * 12 softint-12, Keyboard/Mouse, Serial | |
63 | * 13 softint-13, VME/SBUS level 7, ISDN Audio | |
64 | * 14 softint-14, per-processor counter/timer | |
65 | * 15 softint-15, Asynchronous Errors (broadcast) | |
66 | * | |
67 | * Each interrupt source is masked distinctly in the sun4m interrupt | |
68 | * registers. The PIL level alone is therefore ambiguous, since multiple | |
69 | * interrupt sources map to a single PIL. | |
70 | * | |
71 | * This ambiguity is resolved in the 'intr' property for device nodes | |
72 | * in the OF device tree. Each 'intr' property entry is composed of | |
73 | * two 32-bit words. The first word is the IRQ priority value, which | |
74 | * is what we're intersted in. The second word is the IRQ vector, which | |
75 | * is unused. | |
76 | * | |
77 | * The low 4 bits of the IRQ priority indicate the PIL, and the upper | |
78 | * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20 | |
79 | * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled. | |
80 | * | |
81 | * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI | |
82 | * whereas a value of 0x33 is SBUS level 2. Here are some sample | |
83 | * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and | |
84 | * Tadpole S3 GX systems. | |
85 | * | |
86 | * esp: 0x24 onboard ESP SCSI | |
87 | * le: 0x26 onboard Lance ETHERNET | |
88 | * p9100: 0x32 SBUS level 1 P9100 video | |
89 | * bpp: 0x33 SBUS level 2 BPP parallel port device | |
90 | * DBRI: 0x39 SBUS level 5 DBRI ISDN audio | |
91 | * SUNW,leo: 0x39 SBUS level 5 LEO video | |
92 | * pcmcia: 0x3b SBUS level 6 PCMCIA controller | |
93 | * uctrl: 0x3b SBUS level 6 UCTRL device | |
94 | * modem: 0x3d SBUS level 7 MODEM | |
95 | * zs: 0x2c onboard keyboard/mouse/serial | |
96 | * floppy: 0x2b onboard Floppy | |
97 | * power: 0x22 onboard power device (XXX unknown mask bit XXX) | |
98 | */ | |
99 | ||
32231a66 | 100 | |
69c010b2 DM |
101 | /* Code in entry.S needs to get at these register mappings. */ |
102 | struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS]; | |
103 | struct sun4m_irq_global __iomem *sun4m_irq_global; | |
1da177e4 | 104 | |
6baa9b20 SR |
105 | struct sun4m_handler_data { |
106 | bool percpu; | |
107 | long mask; | |
108 | }; | |
109 | ||
32231a66 AV |
110 | /* Dave Redman (djhr@tadpole.co.uk) |
111 | * The sun4m interrupt registers. | |
112 | */ | |
aba20a82 SR |
113 | #define SUN4M_INT_ENABLE 0x80000000 |
114 | #define SUN4M_INT_E14 0x00000080 | |
115 | #define SUN4M_INT_E10 0x00080000 | |
32231a66 | 116 | |
32231a66 AV |
117 | #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */ |
118 | #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */ | |
6cf4a924 RR |
119 | #define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */ |
120 | #define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */ | |
121 | #define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */ | |
32231a66 AV |
122 | #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */ |
123 | #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */ | |
124 | #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */ | |
125 | #define SUN4M_INT_REALTIME 0x00080000 /* system timer */ | |
126 | #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */ | |
127 | #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */ | |
128 | #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */ | |
129 | #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */ | |
130 | #define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */ | |
131 | #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */ | |
6cf4a924 RR |
132 | #define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */ |
133 | ||
134 | #define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \ | |
135 | SUN4M_INT_M2S_WRITE_ERR | \ | |
136 | SUN4M_INT_ECC_ERR | \ | |
137 | SUN4M_INT_VME_ERR) | |
32231a66 AV |
138 | |
139 | #define SUN4M_INT_SBUS(x) (1 << (x+7)) | |
140 | #define SUN4M_INT_VME(x) (1 << (x)) | |
141 | ||
6cf4a924 RR |
142 | /* Interrupt levels used by OBP */ |
143 | #define OBP_INT_LEVEL_SOFT 0x10 | |
144 | #define OBP_INT_LEVEL_ONBOARD 0x20 | |
145 | #define OBP_INT_LEVEL_SBUS 0x30 | |
146 | #define OBP_INT_LEVEL_VME 0x40 | |
147 | ||
0399bb5b | 148 | #define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10) |
6baa9b20 | 149 | #define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14) |
0399bb5b | 150 | |
6baa9b20 | 151 | static unsigned long sun4m_imask[0x50] = { |
0399bb5b | 152 | /* 0x00 - SMP */ |
6cf4a924 RR |
153 | 0, SUN4M_SOFT_INT(1), |
154 | SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3), | |
155 | SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5), | |
156 | SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7), | |
157 | SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9), | |
158 | SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11), | |
159 | SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13), | |
160 | SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15), | |
0399bb5b | 161 | /* 0x10 - soft */ |
6cf4a924 RR |
162 | 0, SUN4M_SOFT_INT(1), |
163 | SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3), | |
164 | SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5), | |
165 | SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7), | |
166 | SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9), | |
167 | SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11), | |
168 | SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13), | |
169 | SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15), | |
0399bb5b | 170 | /* 0x20 - onboard */ |
6cf4a924 RR |
171 | 0, 0, 0, 0, |
172 | SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0, | |
173 | SUN4M_INT_VIDEO, SUN4M_INT_MODULE, | |
174 | SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY, | |
175 | (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), | |
6baa9b20 | 176 | SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR, |
0399bb5b | 177 | /* 0x30 - sbus */ |
6cf4a924 RR |
178 | 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1), |
179 | 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3), | |
180 | 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5), | |
181 | 0, SUN4M_INT_SBUS(6), 0, 0, | |
0399bb5b | 182 | /* 0x40 - vme */ |
6cf4a924 RR |
183 | 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1), |
184 | 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3), | |
185 | 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5), | |
186 | 0, SUN4M_INT_VME(6), 0, 0 | |
1da177e4 LT |
187 | }; |
188 | ||
6baa9b20 | 189 | static void sun4m_mask_irq(struct irq_data *data) |
1da177e4 | 190 | { |
6baa9b20 SR |
191 | struct sun4m_handler_data *handler_data = data->handler_data; |
192 | int cpu = smp_processor_id(); | |
6cf4a924 | 193 | |
6baa9b20 SR |
194 | if (handler_data->mask) { |
195 | unsigned long flags; | |
6cf4a924 | 196 | |
6baa9b20 SR |
197 | local_irq_save(flags); |
198 | if (handler_data->percpu) { | |
199 | sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set); | |
200 | } else { | |
201 | sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set); | |
202 | } | |
203 | local_irq_restore(flags); | |
204 | } | |
1da177e4 LT |
205 | } |
206 | ||
6baa9b20 | 207 | static void sun4m_unmask_irq(struct irq_data *data) |
1da177e4 | 208 | { |
6baa9b20 | 209 | struct sun4m_handler_data *handler_data = data->handler_data; |
1da177e4 LT |
210 | int cpu = smp_processor_id(); |
211 | ||
6baa9b20 SR |
212 | if (handler_data->mask) { |
213 | unsigned long flags; | |
1da177e4 | 214 | |
1da177e4 | 215 | local_irq_save(flags); |
6baa9b20 SR |
216 | if (handler_data->percpu) { |
217 | sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear); | |
218 | } else { | |
219 | sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear); | |
220 | } | |
1da177e4 LT |
221 | local_irq_restore(flags); |
222 | } | |
223 | } | |
224 | ||
6baa9b20 SR |
225 | static unsigned int sun4m_startup_irq(struct irq_data *data) |
226 | { | |
227 | irq_link(data->irq); | |
228 | sun4m_unmask_irq(data); | |
229 | return 0; | |
230 | } | |
1da177e4 | 231 | |
6baa9b20 | 232 | static void sun4m_shutdown_irq(struct irq_data *data) |
1da177e4 | 233 | { |
6baa9b20 SR |
234 | sun4m_mask_irq(data); |
235 | irq_unlink(data->irq); | |
1da177e4 LT |
236 | } |
237 | ||
6baa9b20 SR |
238 | static struct irq_chip sun4m_irq = { |
239 | .name = "sun4m", | |
240 | .irq_startup = sun4m_startup_irq, | |
241 | .irq_shutdown = sun4m_shutdown_irq, | |
242 | .irq_mask = sun4m_mask_irq, | |
243 | .irq_unmask = sun4m_unmask_irq, | |
244 | }; | |
245 | ||
246 | ||
247 | static unsigned int sun4m_build_device_irq(struct platform_device *op, | |
248 | unsigned int real_irq) | |
1da177e4 | 249 | { |
6baa9b20 SR |
250 | struct sun4m_handler_data *handler_data; |
251 | unsigned int irq; | |
252 | unsigned int pil; | |
253 | ||
254 | if (real_irq >= OBP_INT_LEVEL_VME) { | |
255 | prom_printf("Bogus sun4m IRQ %u\n", real_irq); | |
256 | prom_halt(); | |
257 | } | |
258 | pil = (real_irq & 0xf); | |
259 | irq = irq_alloc(real_irq, pil); | |
260 | ||
261 | if (irq == 0) | |
262 | goto out; | |
263 | ||
264 | handler_data = irq_get_handler_data(irq); | |
265 | if (unlikely(handler_data)) | |
266 | goto out; | |
267 | ||
268 | handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC); | |
269 | if (unlikely(!handler_data)) { | |
270 | prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n"); | |
271 | prom_halt(); | |
272 | } | |
273 | ||
274 | handler_data->mask = sun4m_imask[real_irq]; | |
275 | handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD; | |
276 | irq_set_chip_and_handler_name(irq, &sun4m_irq, | |
277 | handle_level_irq, "level"); | |
278 | irq_set_handler_data(irq, handler_data); | |
279 | ||
280 | out: | |
281 | return irq; | |
1da177e4 LT |
282 | } |
283 | ||
9b2e43ae DM |
284 | struct sun4m_timer_percpu { |
285 | u32 l14_limit; | |
286 | u32 l14_count; | |
287 | u32 l14_limit_noclear; | |
288 | u32 user_timer_start_stop; | |
289 | }; | |
290 | ||
291 | static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS]; | |
292 | ||
293 | struct sun4m_timer_global { | |
294 | u32 l10_limit; | |
295 | u32 l10_count; | |
296 | u32 l10_limit_noclear; | |
297 | u32 reserved; | |
298 | u32 timer_config; | |
299 | }; | |
300 | ||
301 | static struct sun4m_timer_global __iomem *timers_global; | |
302 | ||
1da177e4 LT |
303 | static void sun4m_clear_clock_irq(void) |
304 | { | |
9b2e43ae | 305 | sbus_readl(&timers_global->l10_limit); |
1da177e4 LT |
306 | } |
307 | ||
6cf4a924 RR |
308 | void sun4m_nmi(struct pt_regs *regs) |
309 | { | |
310 | unsigned long afsr, afar, si; | |
311 | ||
312 | printk(KERN_ERR "Aieee: sun4m NMI received!\n"); | |
313 | /* XXX HyperSparc hack XXX */ | |
314 | __asm__ __volatile__("mov 0x500, %%g1\n\t" | |
315 | "lda [%%g1] 0x4, %0\n\t" | |
316 | "mov 0x600, %%g1\n\t" | |
317 | "lda [%%g1] 0x4, %1\n\t" : | |
318 | "=r" (afsr), "=r" (afar)); | |
319 | printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar); | |
320 | si = sbus_readl(&sun4m_irq_global->pending); | |
321 | printk(KERN_ERR "si=%08lx\n", si); | |
322 | if (si & SUN4M_INT_MODULE_ERR) | |
323 | printk(KERN_ERR "Module async error\n"); | |
324 | if (si & SUN4M_INT_M2S_WRITE_ERR) | |
325 | printk(KERN_ERR "MBus/SBus async error\n"); | |
326 | if (si & SUN4M_INT_ECC_ERR) | |
327 | printk(KERN_ERR "ECC memory error\n"); | |
328 | if (si & SUN4M_INT_VME_ERR) | |
329 | printk(KERN_ERR "VME async error\n"); | |
330 | printk(KERN_ERR "you lose buddy boy...\n"); | |
331 | show_regs(regs); | |
332 | prom_halt(); | |
333 | } | |
334 | ||
6baa9b20 SR |
335 | void sun4m_unmask_profile_irq(void) |
336 | { | |
337 | unsigned long flags; | |
338 | ||
339 | local_irq_save(flags); | |
340 | sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear); | |
341 | local_irq_restore(flags); | |
342 | } | |
343 | ||
1de937a5 | 344 | void sun4m_clear_profile_irq(int cpu) |
1da177e4 | 345 | { |
9b2e43ae | 346 | sbus_readl(&timers_percpu[cpu]->l14_limit); |
1da177e4 LT |
347 | } |
348 | ||
349 | static void sun4m_load_profile_irq(int cpu, unsigned int limit) | |
350 | { | |
62f08283 TK |
351 | unsigned int value = limit ? timer_value(limit) : 0; |
352 | sbus_writel(value, &timers_percpu[cpu]->l14_limit); | |
1da177e4 LT |
353 | } |
354 | ||
62f08283 | 355 | static void __init sun4m_init_timers(void) |
1da177e4 | 356 | { |
9b2e43ae DM |
357 | struct device_node *dp = of_find_node_by_name(NULL, "counter"); |
358 | int i, err, len, num_cpu_timers; | |
6baa9b20 | 359 | unsigned int irq; |
9b2e43ae DM |
360 | const u32 *addr; |
361 | ||
362 | if (!dp) { | |
363 | printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n"); | |
364 | return; | |
1da177e4 | 365 | } |
9b2e43ae DM |
366 | |
367 | addr = of_get_property(dp, "address", &len); | |
c2e27c35 | 368 | of_node_put(dp); |
9b2e43ae DM |
369 | if (!addr) { |
370 | printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n"); | |
371 | return; | |
1da177e4 LT |
372 | } |
373 | ||
9b2e43ae DM |
374 | num_cpu_timers = (len / sizeof(u32)) - 1; |
375 | for (i = 0; i < num_cpu_timers; i++) { | |
376 | timers_percpu[i] = (void __iomem *) | |
377 | (unsigned long) addr[i]; | |
1da177e4 | 378 | } |
9b2e43ae DM |
379 | timers_global = (void __iomem *) |
380 | (unsigned long) addr[num_cpu_timers]; | |
381 | ||
e51e07e0 TK |
382 | /* Every per-cpu timer works in timer mode */ |
383 | sbus_writel(0x00000000, &timers_global->timer_config); | |
384 | ||
62f08283 TK |
385 | #ifdef CONFIG_SMP |
386 | sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */ | |
387 | sparc_config.features |= FEAT_L14_ONESHOT; | |
388 | #else | |
389 | sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */ | |
390 | sparc_config.features |= FEAT_L10_CLOCKEVENT; | |
391 | #endif | |
392 | sparc_config.features |= FEAT_L10_CLOCKSOURCE; | |
393 | sbus_writel(timer_value(sparc_config.cs_period), | |
394 | &timers_global->l10_limit); | |
9b2e43ae DM |
395 | |
396 | master_l10_counter = &timers_global->l10_count; | |
9b2e43ae | 397 | |
6baa9b20 SR |
398 | irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ); |
399 | ||
62f08283 | 400 | err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); |
9b2e43ae DM |
401 | if (err) { |
402 | printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n", | |
403 | err); | |
404 | return; | |
1da177e4 | 405 | } |
9b2e43ae DM |
406 | |
407 | for (i = 0; i < num_cpu_timers; i++) | |
408 | sbus_writel(0, &timers_percpu[i]->l14_limit); | |
409 | if (num_cpu_timers == 4) | |
69c010b2 | 410 | sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set); |
9b2e43ae | 411 | |
1da177e4 LT |
412 | #ifdef CONFIG_SMP |
413 | { | |
414 | unsigned long flags; | |
1da177e4 LT |
415 | struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)]; |
416 | ||
417 | /* For SMP we use the level 14 ticker, however the bootup code | |
d1a78c32 | 418 | * has copied the firmware's level 14 vector into the boot cpu's |
1da177e4 LT |
419 | * trap table, we must fix this now or we get squashed. |
420 | */ | |
421 | local_irq_save(flags); | |
422 | trap_table->inst_one = lvl14_save[0]; | |
423 | trap_table->inst_two = lvl14_save[1]; | |
424 | trap_table->inst_three = lvl14_save[2]; | |
425 | trap_table->inst_four = lvl14_save[3]; | |
5d83d666 | 426 | local_ops->cache_all(); |
1da177e4 LT |
427 | local_irq_restore(flags); |
428 | } | |
429 | #endif | |
430 | } | |
431 | ||
432 | void __init sun4m_init_IRQ(void) | |
433 | { | |
69c010b2 DM |
434 | struct device_node *dp = of_find_node_by_name(NULL, "interrupt"); |
435 | int len, i, mid, num_cpu_iregs; | |
436 | const u32 *addr; | |
437 | ||
438 | if (!dp) { | |
439 | printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n"); | |
440 | return; | |
1da177e4 | 441 | } |
69c010b2 DM |
442 | |
443 | addr = of_get_property(dp, "address", &len); | |
c2e27c35 | 444 | of_node_put(dp); |
69c010b2 DM |
445 | if (!addr) { |
446 | printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n"); | |
447 | return; | |
1da177e4 LT |
448 | } |
449 | ||
69c010b2 DM |
450 | num_cpu_iregs = (len / sizeof(u32)) - 1; |
451 | for (i = 0; i < num_cpu_iregs; i++) { | |
452 | sun4m_irq_percpu[i] = (void __iomem *) | |
453 | (unsigned long) addr[i]; | |
454 | } | |
455 | sun4m_irq_global = (void __iomem *) | |
456 | (unsigned long) addr[num_cpu_iregs]; | |
1da177e4 | 457 | |
69c010b2 | 458 | local_irq_disable(); |
1da177e4 | 459 | |
69c010b2 | 460 | sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set); |
1da177e4 | 461 | for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++) |
69c010b2 DM |
462 | sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear); |
463 | ||
e7913de9 | 464 | if (num_cpu_iregs == 4) |
69c010b2 | 465 | sbus_writel(0, &sun4m_irq_global->interrupt_target); |
e7913de9 | 466 | |
08c9388f | 467 | sparc_config.init_timers = sun4m_init_timers; |
472bc4f2 | 468 | sparc_config.build_device_irq = sun4m_build_device_irq; |
62f08283 | 469 | sparc_config.clock_rate = SBUS_CLOCK_RATE; |
08c9388f SR |
470 | sparc_config.clear_clock_irq = sun4m_clear_clock_irq; |
471 | sparc_config.load_profile_irq = sun4m_load_profile_irq; | |
472 | ||
bbdc2661 | 473 | |
1da177e4 LT |
474 | /* Cannot enable interrupts until OBP ticker is disabled. */ |
475 | } |