[deliverable/linux.git] / arch / sparc / kernel / sun4m_irq.c

/*  sun4m_irq.c
 *  arch/sparc/kernel/sun4m_irq.c:
 *
 *  djhr: Hacked out of irq.c into a CPU dependent version.
 *
 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
 *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
 *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
 */

#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/ioport.h>

#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/psr.h>
#include <asm/vaddrs.h>
#include <asm/timer.h>
#include <asm/openprom.h>
#include <asm/oplib.h>
#include <asm/traps.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/smp.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/sbus.h>
#include <asm/cacheflush.h>

#include "irq.h"

/* On the sun4m, just like the timers, we have both per-cpu and master
 * interrupt registers.
 */

/* These registers are used for sending/receiving irqs from/to
 * different cpu's.
 */
struct sun4m_intreg_percpu {
	unsigned int tbt;        /* Interrupts still pending for this cpu. */

	/* These next two registers are WRITE-ONLY and are only
	 * "on bit" sensitive, "off bits" written have NO affect.
	 */
	unsigned int clear;  /* Clear this cpus irqs here. */
	unsigned int set;    /* Set this cpus irqs here. */
	unsigned char space[PAGE_SIZE - 12];
};

/*
 * djhr
 * Actually the clear and set fields in this struct are misleading..
 * according to the SLAVIO manual (and the same applies for the SEC)
 * the clear field clears bits in the mask which will ENABLE that IRQ
 * the set field sets bits in the mask to DISABLE the IRQ.
 *
 * Also the undirected_xx address in the SLAVIO is defined as
 * RESERVED and write only..
 *
 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
 *             sun4m machines, for MP the layout makes more sense.
 */
struct sun4m_intregs {
	struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
	unsigned int tbt;                /* IRQ's that are still pending. */
	unsigned int irqs;               /* Master IRQ bits. */

	/* Again, like the above, two these registers are WRITE-ONLY. */
	unsigned int clear;              /* Clear master IRQ's by setting bits here. */
	unsigned int set;                /* Set master IRQ's by setting bits here. */

	/* This register is both READ and WRITE. */
	unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
};

static unsigned long dummy;

struct sun4m_intregs *sun4m_interrupts;
unsigned long *irq_rcvreg = &dummy;

/* Dave Redman (djhr@tadpole.co.uk)
 * The sun4m interrupt registers.
 */
#define SUN4M_INT_ENABLE  	0x80000000
#define SUN4M_INT_E14     	0x00000080
#define SUN4M_INT_E10     	0x00080000

#define SUN4M_HARD_INT(x)	(0x000000001 << (x))
#define SUN4M_SOFT_INT(x)	(0x000010000 << (x))

#define	SUN4M_INT_MASKALL	0x80000000	  /* mask all interrupts */
#define	SUN4M_INT_MODULE_ERR	0x40000000	  /* module error */
#define	SUN4M_INT_M2S_WRITE	0x20000000	  /* write buffer error */
#define	SUN4M_INT_ECC		0x10000000	  /* ecc memory error */
#define	SUN4M_INT_FLOPPY	0x00400000	  /* floppy disk */
#define	SUN4M_INT_MODULE	0x00200000	  /* module interrupt */
#define	SUN4M_INT_VIDEO		0x00100000	  /* onboard video */
#define	SUN4M_INT_REALTIME	0x00080000	  /* system timer */
#define	SUN4M_INT_SCSI		0x00040000	  /* onboard scsi */
#define	SUN4M_INT_AUDIO		0x00020000	  /* audio/isdn */
#define	SUN4M_INT_ETHERNET	0x00010000	  /* onboard ethernet */
#define	SUN4M_INT_SERIAL	0x00008000	  /* serial ports */
#define	SUN4M_INT_KBDMS		0x00004000	  /* keyboard/mouse */
#define	SUN4M_INT_SBUSBITS	0x00003F80	  /* sbus int bits */

#define SUN4M_INT_SBUS(x)	(1 << (x+7))
#define SUN4M_INT_VME(x)	(1 << (x))

/* These tables only apply for interrupts greater than 15..
 * 
 * any intr value below 0x10 is considered to be a soft-int
 * this may be useful or it may not.. but that's how I've done it.
 * and it won't clash with what OBP is telling us about devices.
 *
 * take an encoded intr value and lookup if it's valid
 * then get the mask bits that match from irq_mask
 *
 * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
 */
static unsigned char irq_xlate[32] = {
    /*  0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  a,  b,  c,  d,  e,  f */
	0,  0,  0,  0,  1,  0,  2,  0,  3,  0,  4,  5,  6, 14,  0,  7,
	0,  0,  8,  9,  0, 10,  0, 11,  0, 12,  0, 13,  0, 14,  0,  0
};

static unsigned long irq_mask[] = {
	0,						  /* illegal index */
	SUN4M_INT_SCSI,				  	  /*  1 irq 4 */
	SUN4M_INT_ETHERNET,				  /*  2 irq 6 */
	SUN4M_INT_VIDEO,				  /*  3 irq 8 */
	SUN4M_INT_REALTIME,				  /*  4 irq 10 */
	SUN4M_INT_FLOPPY,				  /*  5 irq 11 */
	(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),	  	  /*  6 irq 12 */
	SUN4M_INT_MODULE_ERR,			  	  /*  7 irq 15 */
	SUN4M_INT_SBUS(0),				  /*  8 irq 2 */
	SUN4M_INT_SBUS(1),				  /*  9 irq 3 */
	SUN4M_INT_SBUS(2),				  /* 10 irq 5 */
	SUN4M_INT_SBUS(3),				  /* 11 irq 7 */
	SUN4M_INT_SBUS(4),				  /* 12 irq 9 */
	SUN4M_INT_SBUS(5),				  /* 13 irq 11 */
	SUN4M_INT_SBUS(6)				  /* 14 irq 13 */
};

static unsigned long sun4m_get_irqmask(unsigned int irq)
{
	unsigned long mask;
    
	if (irq > 0x20) {
		/* OBIO/SBUS interrupts */
		irq &= 0x1f;
		mask = irq_mask[irq_xlate[irq]];
		if (!mask)
			printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
	} else {
		/* Soft Interrupts will come here.
		 * Currently there is no way to trigger them but I'm sure
		 * something could be cooked up.
		 */
		irq &= 0xf;
		mask = SUN4M_SOFT_INT(irq);
	}
	return mask;
}

static void sun4m_disable_irq(unsigned int irq_nr)
{
	unsigned long mask, flags;
	int cpu = smp_processor_id();

	mask = sun4m_get_irqmask(irq_nr);
	local_irq_save(flags);
	if (irq_nr > 15)
		sun4m_interrupts->set = mask;
	else
		sun4m_interrupts->cpu_intregs[cpu].set = mask;
	local_irq_restore(flags);    
}

static void sun4m_enable_irq(unsigned int irq_nr)
{
	unsigned long mask, flags;
	int cpu = smp_processor_id();

	/* Dreadful floppy hack. When we use 0x2b instead of
         * 0x0b the system blows (it starts to whistle!).
         * So we continue to use 0x0b. Fixme ASAP. --P3
         */
        if (irq_nr != 0x0b) {
		mask = sun4m_get_irqmask(irq_nr);
		local_irq_save(flags);
		if (irq_nr > 15)
			sun4m_interrupts->clear = mask;
		else
			sun4m_interrupts->cpu_intregs[cpu].clear = mask;
		local_irq_restore(flags);    
	} else {
		local_irq_save(flags);
		sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
		local_irq_restore(flags);
	}
}

static unsigned long cpu_pil_to_imask[16] = {
/*0*/	0x00000000,
/*1*/	0x00000000,
/*2*/	SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
/*3*/	SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
/*4*/	SUN4M_INT_SCSI,
/*5*/	SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
/*6*/	SUN4M_INT_ETHERNET,
/*7*/	SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
/*8*/	SUN4M_INT_VIDEO,
/*9*/	SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
/*10*/	SUN4M_INT_REALTIME,
/*11*/	SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
/*12*/	SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
/*13*/	SUN4M_INT_AUDIO,
/*14*/	SUN4M_INT_E14,
/*15*/	0x00000000
};

/* We assume the caller has disabled local interrupts when these are called,
 * or else very bizarre behavior will result.
 */
static void sun4m_disable_pil_irq(unsigned int pil)
{
	sun4m_interrupts->set = cpu_pil_to_imask[pil];
}

static void sun4m_enable_pil_irq(unsigned int pil)
{
	sun4m_interrupts->clear = cpu_pil_to_imask[pil];
}

#ifdef CONFIG_SMP
static void sun4m_send_ipi(int cpu, int level)
{
	unsigned long mask;

	mask = sun4m_get_irqmask(level);
	sun4m_interrupts->cpu_intregs[cpu].set = mask;
}

static void sun4m_clear_ipi(int cpu, int level)
{
	unsigned long mask;

	mask = sun4m_get_irqmask(level);
	sun4m_interrupts->cpu_intregs[cpu].clear = mask;
}

static void sun4m_set_udt(int cpu)
{
	sun4m_interrupts->undirected_target = cpu;
}
#endif

#define OBIO_INTR	0x20
#define TIMER_IRQ  	(OBIO_INTR | 10)
#define PROFILE_IRQ	(OBIO_INTR | 14)

static struct sun4m_timer_regs *sun4m_timers;
unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);

static void sun4m_clear_clock_irq(void)
{
	volatile unsigned int clear_intr;
	clear_intr = sun4m_timers->l10_timer_limit;
}

static void sun4m_clear_profile_irq(int cpu)
{
	volatile unsigned int clear;
    
	clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
}

static void sun4m_load_profile_irq(int cpu, unsigned int limit)
{
	sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
}

static void __init sun4m_init_timers(irq_handler_t counter_fn)
{
	int reg_count, irq, cpu;
	struct linux_prom_registers cnt_regs[PROMREG_MAX];
	int obio_node, cnt_node;
	struct resource r;

	cnt_node = 0;
	if((obio_node =
	    prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
	   (obio_node = prom_getchild (obio_node)) == 0 ||
	   (cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
		prom_printf("Cannot find /obio/counter node\n");
		prom_halt();
	}
	reg_count = prom_getproperty(cnt_node, "reg",
				     (void *) cnt_regs, sizeof(cnt_regs));
	reg_count = (reg_count/sizeof(struct linux_prom_registers));
    
	/* Apply the obio ranges to the timer registers. */
	prom_apply_obio_ranges(cnt_regs, reg_count);
    
	cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
	cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
	cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
	for(obio_node = 1; obio_node < 4; obio_node++) {
		cnt_regs[obio_node].phys_addr =
			cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
		cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
		cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
	}

	memset((char*)&r, 0, sizeof(struct resource));
	/* Map the per-cpu Counter registers. */
	r.flags = cnt_regs[0].which_io;
	r.start = cnt_regs[0].phys_addr;
	sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
	    PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
	/* Map the system Counter register. */
	/* XXX Here we expect consequent calls to yeld adjusent maps. */
	r.flags = cnt_regs[4].which_io;
	r.start = cnt_regs[4].phys_addr;
	sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");

	sun4m_timers->l10_timer_limit =  (((1000000/HZ) + 1) << 10);
	master_l10_counter = &sun4m_timers->l10_cur_count;
	master_l10_limit = &sun4m_timers->l10_timer_limit;

	irq = request_irq(TIMER_IRQ,
			  counter_fn,
			  (IRQF_DISABLED | SA_STATIC_ALLOC),
			  "timer", NULL);
	if (irq) {
		prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
		prom_halt();
	}
   
	if (!cpu_find_by_instance(1, NULL, NULL)) {
		for(cpu = 0; cpu < 4; cpu++)
			sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
		sun4m_interrupts->set = SUN4M_INT_E14;
	} else {
		sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
	}
#ifdef CONFIG_SMP
	{
		unsigned long flags;
		extern unsigned long lvl14_save[4];
		struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];

		/* For SMP we use the level 14 ticker, however the bootup code
		 * has copied the firmware's level 14 vector into the boot cpu's
		 * trap table, we must fix this now or we get squashed.
		 */
		local_irq_save(flags);
		trap_table->inst_one = lvl14_save[0];
		trap_table->inst_two = lvl14_save[1];
		trap_table->inst_three = lvl14_save[2];
		trap_table->inst_four = lvl14_save[3];
		local_flush_cache_all();
		local_irq_restore(flags);
	}
#endif
}

void __init sun4m_init_IRQ(void)
{
	int ie_node,i;
	struct linux_prom_registers int_regs[PROMREG_MAX];
	int num_regs;
	struct resource r;
	int mid;
    
	local_irq_disable();
	if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
	   (ie_node = prom_getchild (ie_node)) == 0 ||
	   (ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
		prom_printf("Cannot find /obio/interrupt node\n");
		prom_halt();
	}
	num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
				    sizeof(int_regs));
	num_regs = (num_regs/sizeof(struct linux_prom_registers));
    
	/* Apply the obio ranges to these registers. */
	prom_apply_obio_ranges(int_regs, num_regs);
    
	int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
	int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
	int_regs[4].which_io = int_regs[num_regs-1].which_io;
	for(ie_node = 1; ie_node < 4; ie_node++) {
		int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
		int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
		int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
	}

	memset((char *)&r, 0, sizeof(struct resource));
	/* Map the interrupt registers for all possible cpus. */
	r.flags = int_regs[0].which_io;
	r.start = int_regs[0].phys_addr;
	sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0,
	    PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");

	/* Map the system interrupt control registers. */
	r.flags = int_regs[4].which_io;
	r.start = int_regs[4].phys_addr;
	sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");

	sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
	for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
		sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;

	if (!cpu_find_by_instance(1, NULL, NULL)) {
		/* system wide interrupts go to cpu 0, this should always
		 * be safe because it is guaranteed to be fitted or OBP doesn't
		 * come up
		 *
		 * Not sure, but writing here on SLAVIO systems may puke
		 * so I don't do it unless there is more than 1 cpu.
		 */
		irq_rcvreg = (unsigned long *)
				&sun4m_interrupts->undirected_target;
		sun4m_interrupts->undirected_target = 0;
	}
	BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
	sparc_init_timers = sun4m_init_timers;
#ifdef CONFIG_SMP
	BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
#endif
	/* Cannot enable interrupts until OBP ticker is disabled. */
}
Commit	Line	Data
1da177e4 LT	1	/* sun4m_irq.c
	2	* arch/sparc/kernel/sun4m_irq.c:
	3	*
	4	* djhr: Hacked out of irq.c into a CPU dependent version.
	5	*
	6	* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
	7	* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
	8	* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
	9	* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
	10	*/
	11
1da177e4 LT	12	#include <linux/errno.h>
	13	#include <linux/linkage.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/signal.h>
	16	#include <linux/sched.h>
	17	#include <linux/ptrace.h>
	18	#include <linux/smp.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/slab.h>
	21	#include <linux/init.h>
	22	#include <linux/ioport.h>
	23
	24	#include <asm/ptrace.h>
	25	#include <asm/processor.h>
	26	#include <asm/system.h>
	27	#include <asm/psr.h>
	28	#include <asm/vaddrs.h>
	29	#include <asm/timer.h>
	30	#include <asm/openprom.h>
	31	#include <asm/oplib.h>
	32	#include <asm/traps.h>
	33	#include <asm/pgalloc.h>
	34	#include <asm/pgtable.h>
	35	#include <asm/smp.h>
	36	#include <asm/irq.h>
	37	#include <asm/io.h>
	38	#include <asm/sbus.h>
	39	#include <asm/cacheflush.h>
	40
32231a66 AV	41	#include "irq.h"
	42
	43	/* On the sun4m, just like the timers, we have both per-cpu and master
	44	* interrupt registers.
	45	*/
	46
	47	/* These registers are used for sending/receiving irqs from/to
	48	* different cpu's.
	49	*/
	50	struct sun4m_intreg_percpu {
	51	unsigned int tbt; /* Interrupts still pending for this cpu. */
	52
	53	/* These next two registers are WRITE-ONLY and are only
	54	* "on bit" sensitive, "off bits" written have NO affect.
	55	*/
	56	unsigned int clear; /* Clear this cpus irqs here. */
	57	unsigned int set; /* Set this cpus irqs here. */
	58	unsigned char space[PAGE_SIZE - 12];
	59	};
	60
	61	/*
	62	* djhr
	63	* Actually the clear and set fields in this struct are misleading..
	64	* according to the SLAVIO manual (and the same applies for the SEC)
	65	* the clear field clears bits in the mask which will ENABLE that IRQ
	66	* the set field sets bits in the mask to DISABLE the IRQ.
	67	*
	68	* Also the undirected_xx address in the SLAVIO is defined as
	69	* RESERVED and write only..
	70	*
	71	* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
	72	* sun4m machines, for MP the layout makes more sense.
	73	*/
	74	struct sun4m_intregs {
	75	struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
	76	unsigned int tbt; /* IRQ's that are still pending. */
	77	unsigned int irqs; /* Master IRQ bits. */
	78
	79	/* Again, like the above, two these registers are WRITE-ONLY. */
	80	unsigned int clear; /* Clear master IRQ's by setting bits here. */
	81	unsigned int set; /* Set master IRQ's by setting bits here. */
	82
	83	/* This register is both READ and WRITE. */
	84	unsigned int undirected_target; /* Which cpu gets undirected irqs. */
	85	};
	86
1da177e4 LT	87	static unsigned long dummy;
	88
	89	struct sun4m_intregs *sun4m_interrupts;
	90	unsigned long *irq_rcvreg = &dummy;
	91
32231a66 AV	92	/* Dave Redman (djhr@tadpole.co.uk)
	93	* The sun4m interrupt registers.
	94	*/
	95	#define SUN4M_INT_ENABLE 0x80000000
	96	#define SUN4M_INT_E14 0x00000080
	97	#define SUN4M_INT_E10 0x00080000
	98
	99	#define SUN4M_HARD_INT(x) (0x000000001 << (x))
	100	#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
	101
	102	#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
	103	#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
	104	#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
	105	#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
	106	#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
	107	#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
	108	#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
	109	#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
	110	#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
	111	#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
	112	#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
	113	#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
	114	#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
	115	#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
	116
	117	#define SUN4M_INT_SBUS(x) (1 << (x+7))
	118	#define SUN4M_INT_VME(x) (1 << (x))
	119
1da177e4 LT	120	/* These tables only apply for interrupts greater than 15..
	121	*
	122	* any intr value below 0x10 is considered to be a soft-int
	123	* this may be useful or it may not.. but that's how I've done it.
	124	* and it won't clash with what OBP is telling us about devices.
	125	*
	126	* take an encoded intr value and lookup if it's valid
	127	* then get the mask bits that match from irq_mask
	128	*
	129	* P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
	130	*/
	131	static unsigned char irq_xlate[32] = {
	132	/* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
	133	0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
	134	0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
	135	};
	136
	137	static unsigned long irq_mask[] = {
	138	0, /* illegal index */
	139	SUN4M_INT_SCSI, /* 1 irq 4 */
	140	SUN4M_INT_ETHERNET, /* 2 irq 6 */
	141	SUN4M_INT_VIDEO, /* 3 irq 8 */
	142	SUN4M_INT_REALTIME, /* 4 irq 10 */
	143	SUN4M_INT_FLOPPY, /* 5 irq 11 */
	144	(SUN4M_INT_SERIAL \| SUN4M_INT_KBDMS), /* 6 irq 12 */
	145	SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
	146	SUN4M_INT_SBUS(0), /* 8 irq 2 */
	147	SUN4M_INT_SBUS(1), /* 9 irq 3 */
	148	SUN4M_INT_SBUS(2), /* 10 irq 5 */
	149	SUN4M_INT_SBUS(3), /* 11 irq 7 */
	150	SUN4M_INT_SBUS(4), /* 12 irq 9 */
	151	SUN4M_INT_SBUS(5), /* 13 irq 11 */
	152	SUN4M_INT_SBUS(6) /* 14 irq 13 */
	153	};
	154
c61c65cd	155	static unsigned long sun4m_get_irqmask(unsigned int irq)
1da177e4 LT	156	{
	157	unsigned long mask;
	158
	159	if (irq > 0x20) {
	160	/* OBIO/SBUS interrupts */
	161	irq &= 0x1f;
	162	mask = irq_mask[irq_xlate[irq]];
	163	if (!mask)
	164	printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
	165	} else {
	166	/* Soft Interrupts will come here.
	167	* Currently there is no way to trigger them but I'm sure
	168	* something could be cooked up.
	169	*/
	170	irq &= 0xf;
	171	mask = SUN4M_SOFT_INT(irq);
	172	}
	173	return mask;
	174	}
	175
	176	static void sun4m_disable_irq(unsigned int irq_nr)
	177	{
	178	unsigned long mask, flags;
	179	int cpu = smp_processor_id();
	180
	181	mask = sun4m_get_irqmask(irq_nr);
	182	local_irq_save(flags);
	183	if (irq_nr > 15)
	184	sun4m_interrupts->set = mask;
	185	else
	186	sun4m_interrupts->cpu_intregs[cpu].set = mask;
	187	local_irq_restore(flags);
	188	}
	189
	190	static void sun4m_enable_irq(unsigned int irq_nr)
	191	{
	192	unsigned long mask, flags;
	193	int cpu = smp_processor_id();
	194
	195	/* Dreadful floppy hack. When we use 0x2b instead of
	196	* 0x0b the system blows (it starts to whistle!).
	197	* So we continue to use 0x0b. Fixme ASAP. --P3
	198	*/
	199	if (irq_nr != 0x0b) {
	200	mask = sun4m_get_irqmask(irq_nr);
	201	local_irq_save(flags);
	202	if (irq_nr > 15)
	203	sun4m_interrupts->clear = mask;
	204	else
	205	sun4m_interrupts->cpu_intregs[cpu].clear = mask;
	206	local_irq_restore(flags);
	207	} else {
	208	local_irq_save(flags);
	209	sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
	210	local_irq_restore(flags);
	211	}
	212	}
	213
	214	static unsigned long cpu_pil_to_imask[16] = {
	215	/0/ 0x00000000,
	216	/1/ 0x00000000,
	217	/2/ SUN4M_INT_SBUS(0) \| SUN4M_INT_VME(0),
	218	/3/ SUN4M_INT_SBUS(1) \| SUN4M_INT_VME(1),
	219	/4/ SUN4M_INT_SCSI,
220	/5/ SUN4M_INT_SBUS(2) \| SUN4M_INT_VME(2),
221	/6/ SUN4M_INT_ETHERNET,
222	/7/ SUN4M_INT_SBUS(3) \| SUN4M_INT_VME(3),
223	/8/ SUN4M_INT_VIDEO,
224	/9/ SUN4M_INT_SBUS(4) \| SUN4M_INT_VME(4) \| SUN4M_INT_MODULE_ERR,
225	/10/ SUN4M_INT_REALTIME,
226	/11/ SUN4M_INT_SBUS(5) \| SUN4M_INT_VME(5) \| SUN4M_INT_FLOPPY,
227	/12/ SUN4M_INT_SERIAL \| SUN4M_INT_KBDMS,
228	/13/ SUN4M_INT_AUDIO,
229	/14/ SUN4M_INT_E14,
230	/15/ 0x00000000
231	};
232
233	/* We assume the caller has disabled local interrupts when these are called,
234	* or else very bizarre behavior will result.
235	*/
236	static void sun4m_disable_pil_irq(unsigned int pil)
237	{
238	sun4m_interrupts->set = cpu_pil_to_imask[pil];
239	}
240
241	static void sun4m_enable_pil_irq(unsigned int pil)
242	{
243	sun4m_interrupts->clear = cpu_pil_to_imask[pil];
244	}
245
246	#ifdef CONFIG_SMP
247	static void sun4m_send_ipi(int cpu, int level)
248	{
249	unsigned long mask;
250
251	mask = sun4m_get_irqmask(level);
252	sun4m_interrupts->cpu_intregs[cpu].set = mask;
253	}
254
255	static void sun4m_clear_ipi(int cpu, int level)
256	{
257	unsigned long mask;
258
259	mask = sun4m_get_irqmask(level);
260	sun4m_interrupts->cpu_intregs[cpu].clear = mask;
261	}
262
263	static void sun4m_set_udt(int cpu)
264	{
265	sun4m_interrupts->undirected_target = cpu;
266	}
267	#endif
268
269	#define OBIO_INTR 0x20
270	#define TIMER_IRQ (OBIO_INTR \| 10)
271	#define PROFILE_IRQ (OBIO_INTR \| 14)
272
c61c65cd	273	static struct sun4m_timer_regs *sun4m_timers;
1da177e4 LT	274	unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
	275
	276	static void sun4m_clear_clock_irq(void)
	277	{
	278	volatile unsigned int clear_intr;
	279	clear_intr = sun4m_timers->l10_timer_limit;
	280	}
	281
	282	static void sun4m_clear_profile_irq(int cpu)
	283	{
	284	volatile unsigned int clear;
	285
	286	clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
	287	}
	288
	289	static void sun4m_load_profile_irq(int cpu, unsigned int limit)
	290	{
	291	sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
	292	}
	293
40220c1a	294	static void __init sun4m_init_timers(irq_handler_t counter_fn)
1da177e4 LT	295	{
	296	int reg_count, irq, cpu;
	297	struct linux_prom_registers cnt_regs[PROMREG_MAX];
	298	int obio_node, cnt_node;
	299	struct resource r;
	300
	301	cnt_node = 0;
	302	if((obio_node =
	303	prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 \|\|
	304	(obio_node = prom_getchild (obio_node)) == 0 \|\|
	305	(cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
	306	prom_printf("Cannot find /obio/counter node\n");
	307	prom_halt();
	308	}
	309	reg_count = prom_getproperty(cnt_node, "reg",
	310	(void *) cnt_regs, sizeof(cnt_regs));
	311	reg_count = (reg_count/sizeof(struct linux_prom_registers));
	312
	313	/* Apply the obio ranges to the timer registers. */
	314	prom_apply_obio_ranges(cnt_regs, reg_count);
	315
	316	cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
	317	cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
	318	cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
	319	for(obio_node = 1; obio_node < 4; obio_node++) {
	320	cnt_regs[obio_node].phys_addr =
	321	cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
	322	cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
	323	cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
	324	}
	325
	326	memset((char*)&r, 0, sizeof(struct resource));
	327	/* Map the per-cpu Counter registers. */
	328	r.flags = cnt_regs[0].which_io;
	329	r.start = cnt_regs[0].phys_addr;
	330	sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
	331	PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
	332	/* Map the system Counter register. */
	333	/* XXX Here we expect consequent calls to yeld adjusent maps. */
	334	r.flags = cnt_regs[4].which_io;
	335	r.start = cnt_regs[4].phys_addr;
	336	sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
	337
	338	sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
	339	master_l10_counter = &sun4m_timers->l10_cur_count;
	340	master_l10_limit = &sun4m_timers->l10_timer_limit;
	341
	342	irq = request_irq(TIMER_IRQ,
	343	counter_fn,
67413202	344	(IRQF_DISABLED \| SA_STATIC_ALLOC),
1da177e4 LT	345	"timer", NULL);
	346	if (irq) {
	347	prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
	348	prom_halt();
	349	}
	350
	351	if (!cpu_find_by_instance(1, NULL, NULL)) {
	352	for(cpu = 0; cpu < 4; cpu++)
	353	sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
	354	sun4m_interrupts->set = SUN4M_INT_E14;
	355	} else {
	356	sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
	357	}
	358	#ifdef CONFIG_SMP
	359	{
	360	unsigned long flags;
	361	extern unsigned long lvl14_save[4];
	362	struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
	363
	364	/* For SMP we use the level 14 ticker, however the bootup code
d1a78c32	365	* has copied the firmware's level 14 vector into the boot cpu's
1da177e4 LT	366	* trap table, we must fix this now or we get squashed.
	367	*/
	368	local_irq_save(flags);
	369	trap_table->inst_one = lvl14_save[0];
	370	trap_table->inst_two = lvl14_save[1];
	371	trap_table->inst_three = lvl14_save[2];
	372	trap_table->inst_four = lvl14_save[3];
	373	local_flush_cache_all();
	374	local_irq_restore(flags);
	375	}
	376	#endif
	377	}
	378
	379	void __init sun4m_init_IRQ(void)
	380	{
	381	int ie_node,i;
	382	struct linux_prom_registers int_regs[PROMREG_MAX];
	383	int num_regs;
	384	struct resource r;
	385	int mid;
	386
	387	local_irq_disable();
	388	if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 \|\|
	389	(ie_node = prom_getchild (ie_node)) == 0 \|\|
	390	(ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
	391	prom_printf("Cannot find /obio/interrupt node\n");
	392	prom_halt();
	393	}
	394	num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
	395	sizeof(int_regs));
	396	num_regs = (num_regs/sizeof(struct linux_prom_registers));
	397
	398	/* Apply the obio ranges to these registers. */
	399	prom_apply_obio_ranges(int_regs, num_regs);
	400
	401	int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
	402	int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
	403	int_regs[4].which_io = int_regs[num_regs-1].which_io;
	404	for(ie_node = 1; ie_node < 4; ie_node++) {
	405	int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
	406	int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
	407	int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
	408	}
	409
	410	memset((char *)&r, 0, sizeof(struct resource));
	411	/* Map the interrupt registers for all possible cpus. */
	412	r.flags = int_regs[0].which_io;
	413	r.start = int_regs[0].phys_addr;
	414	sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0,
	415	PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
	416
	417	/* Map the system interrupt control registers. */
	418	r.flags = int_regs[4].which_io;
	419	r.start = int_regs[4].phys_addr;
	420	sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
	421
	422	sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
	423	for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
	424	sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;
	425
	426	if (!cpu_find_by_instance(1, NULL, NULL)) {
	427	/* system wide interrupts go to cpu 0, this should always
	428	* be safe because it is guaranteed to be fitted or OBP doesn't
	429	* come up
430	*
431	* Not sure, but writing here on SLAVIO systems may puke
432	* so I don't do it unless there is more than 1 cpu.
433	*/
434	irq_rcvreg = (unsigned long *)
435	&sun4m_interrupts->undirected_target;
436	sun4m_interrupts->undirected_target = 0;
437	}
1da177e4 LT	438	BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
	439	BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
	440	BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
	441	BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
	442	BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
	443	BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
	444	BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
1da177e4 LT	445	sparc_init_timers = sun4m_init_timers;
	446	#ifdef CONFIG_SMP
	447	BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
	448	BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
	449	BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
	450	#endif
	451	/* Cannot enable interrupts until OBP ticker is disabled. */
	452	}