Commit | Line | Data |
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1da177e4 LT |
1 | /* sun4m_smp.c: Sparc SUN4M SMP support. |
2 | * | |
3 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <asm/head.h> | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/threads.h> | |
11 | #include <linux/smp.h> | |
1da177e4 LT |
12 | #include <linux/interrupt.h> |
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/swap.h> | |
18 | #include <linux/profile.h> | |
6c81c32f | 19 | #include <linux/delay.h> |
4245e59d | 20 | #include <linux/cpu.h> |
6c81c32f | 21 | |
1da177e4 LT |
22 | #include <asm/cacheflush.h> |
23 | #include <asm/tlbflush.h> | |
0d84438d | 24 | #include <asm/irq_regs.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/atomic.h> | |
28 | ||
1da177e4 LT |
29 | #include <asm/irq.h> |
30 | #include <asm/page.h> | |
31 | #include <asm/pgalloc.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/oplib.h> | |
34 | #include <asm/cpudata.h> | |
35 | ||
32231a66 AV |
36 | #include "irq.h" |
37 | ||
1da177e4 LT |
38 | #define IRQ_CROSS_CALL 15 |
39 | ||
40 | extern ctxd_t *srmmu_ctx_table_phys; | |
41 | ||
1da177e4 LT |
42 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; |
43 | extern unsigned char boot_cpu_id; | |
a54123e2 BB |
44 | |
45 | extern cpumask_t smp_commenced_mask; | |
46 | ||
1da177e4 LT |
47 | extern int __smp4m_processor_id(void); |
48 | ||
49 | /*#define SMP_DEBUG*/ | |
50 | ||
51 | #ifdef SMP_DEBUG | |
52 | #define SMP_PRINTK(x) printk x | |
53 | #else | |
54 | #define SMP_PRINTK(x) | |
55 | #endif | |
56 | ||
1a8a27c9 WF |
57 | static inline unsigned long |
58 | swap_ulong(volatile unsigned long *ptr, unsigned long val) | |
1da177e4 LT |
59 | { |
60 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
61 | "=&r" (val), "=&r" (ptr) : | |
62 | "0" (val), "1" (ptr)); | |
63 | return val; | |
64 | } | |
65 | ||
66 | static void smp_setup_percpu_timer(void); | |
67 | extern void cpu_probe(void); | |
68 | ||
92d452f0 | 69 | void __cpuinit smp4m_callin(void) |
1da177e4 LT |
70 | { |
71 | int cpuid = hard_smp_processor_id(); | |
72 | ||
73 | local_flush_cache_all(); | |
74 | local_flush_tlb_all(); | |
75 | ||
e545a614 MS |
76 | notify_cpu_starting(cpuid); |
77 | ||
1da177e4 LT |
78 | /* Get our local ticker going. */ |
79 | smp_setup_percpu_timer(); | |
80 | ||
81 | calibrate_delay(); | |
82 | smp_store_cpu_info(cpuid); | |
83 | ||
84 | local_flush_cache_all(); | |
85 | local_flush_tlb_all(); | |
86 | ||
87 | /* | |
88 | * Unblock the master CPU _only_ when the scheduler state | |
89 | * of all secondary CPUs will be up-to-date, so after | |
90 | * the SMP initialization the master will be just allowed | |
91 | * to call the scheduler code. | |
92 | */ | |
93 | /* Allow master to continue. */ | |
1a8a27c9 | 94 | swap_ulong(&cpu_callin_map[cpuid], 1); |
1da177e4 | 95 | |
a54123e2 | 96 | /* XXX: What's up with all the flushes? */ |
1da177e4 LT |
97 | local_flush_cache_all(); |
98 | local_flush_tlb_all(); | |
99 | ||
100 | cpu_probe(); | |
101 | ||
102 | /* Fix idle thread fields. */ | |
103 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
104 | : : "r" (¤t_set[cpuid]) | |
105 | : "memory" /* paranoid */); | |
106 | ||
107 | /* Attach to the address space of init_task. */ | |
108 | atomic_inc(&init_mm.mm_count); | |
109 | current->active_mm = &init_mm; | |
110 | ||
a54123e2 BB |
111 | while (!cpu_isset(cpuid, smp_commenced_mask)) |
112 | mb(); | |
1da177e4 LT |
113 | |
114 | local_irq_enable(); | |
a54123e2 | 115 | |
fe73971c | 116 | set_cpu_online(cpuid, true); |
1da177e4 LT |
117 | } |
118 | ||
1da177e4 LT |
119 | /* |
120 | * Cycle through the processors asking the PROM to start each one. | |
121 | */ | |
122 | ||
123 | extern struct linux_prom_registers smp_penguin_ctable; | |
1da177e4 LT |
124 | |
125 | void __init smp4m_boot_cpus(void) | |
126 | { | |
a54123e2 BB |
127 | smp_setup_percpu_timer(); |
128 | local_flush_cache_all(); | |
129 | } | |
1da177e4 | 130 | |
92d452f0 | 131 | int __cpuinit smp4m_boot_one_cpu(int i) |
a54123e2 BB |
132 | { |
133 | extern unsigned long sun4m_cpu_startup; | |
134 | unsigned long *entry = &sun4m_cpu_startup; | |
135 | struct task_struct *p; | |
136 | int timeout; | |
137 | int cpu_node; | |
1da177e4 | 138 | |
a54123e2 BB |
139 | cpu_find_by_mid(i, &cpu_node); |
140 | ||
141 | /* Cook up an idler for this guy. */ | |
142 | p = fork_idle(i); | |
143 | current_set[i] = task_thread_info(p); | |
144 | /* See trampoline.S for details... */ | |
145 | entry += ((i-1) * 3); | |
1da177e4 | 146 | |
a54123e2 BB |
147 | /* |
148 | * Initialize the contexts table | |
149 | * Since the call to prom_startcpu() trashes the structure, | |
150 | * we need to re-initialize it for each cpu | |
151 | */ | |
152 | smp_penguin_ctable.which_io = 0; | |
153 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
154 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 155 | |
a54123e2 BB |
156 | /* whirrr, whirrr, whirrrrrrrrr... */ |
157 | printk("Starting CPU %d at %p\n", i, entry); | |
158 | local_flush_cache_all(); | |
159 | prom_startcpu(cpu_node, | |
160 | &smp_penguin_ctable, 0, (char *)entry); | |
161 | ||
162 | /* wheee... it's going... */ | |
163 | for(timeout = 0; timeout < 10000; timeout++) { | |
164 | if(cpu_callin_map[i]) | |
165 | break; | |
166 | udelay(200); | |
1da177e4 LT |
167 | } |
168 | ||
a54123e2 BB |
169 | if (!(cpu_callin_map[i])) { |
170 | printk("Processor %d is stuck.\n", i); | |
171 | return -ENODEV; | |
172 | } | |
1da177e4 | 173 | |
1da177e4 | 174 | local_flush_cache_all(); |
a54123e2 BB |
175 | return 0; |
176 | } | |
177 | ||
178 | void __init smp4m_smp_done(void) | |
179 | { | |
180 | int i, first; | |
181 | int *prev; | |
182 | ||
183 | /* setup cpu list for irq rotation */ | |
184 | first = 0; | |
185 | prev = &first; | |
ec7c14bd RR |
186 | for_each_online_cpu(i) { |
187 | *prev = i; | |
188 | prev = &cpu_data(i).next; | |
1da177e4 | 189 | } |
a54123e2 | 190 | *prev = first; |
1da177e4 | 191 | local_flush_cache_all(); |
1da177e4 | 192 | |
1da177e4 | 193 | /* Ok, they are spinning and ready to go. */ |
1da177e4 LT |
194 | } |
195 | ||
196 | /* At each hardware IRQ, we get this called to forward IRQ reception | |
197 | * to the next processor. The caller must disable the IRQ level being | |
198 | * serviced globally so that there are no double interrupts received. | |
199 | * | |
200 | * XXX See sparc64 irq.c. | |
201 | */ | |
202 | void smp4m_irq_rotate(int cpu) | |
203 | { | |
a54123e2 BB |
204 | int next = cpu_data(cpu).next; |
205 | if (next != cpu) | |
206 | set_irq_udt(next); | |
1da177e4 LT |
207 | } |
208 | ||
1da177e4 LT |
209 | static struct smp_funcall { |
210 | smpfunc_t func; | |
211 | unsigned long arg1; | |
212 | unsigned long arg2; | |
213 | unsigned long arg3; | |
214 | unsigned long arg4; | |
215 | unsigned long arg5; | |
a54123e2 BB |
216 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
217 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
218 | } ccall_info; |
219 | ||
220 | static DEFINE_SPINLOCK(cross_call_lock); | |
221 | ||
222 | /* Cross calls must be serialized, at least currently. */ | |
66e4f8c0 | 223 | static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 224 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 225 | unsigned long arg4) |
1da177e4 | 226 | { |
a54123e2 | 227 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
228 | unsigned long flags; |
229 | ||
230 | spin_lock_irqsave(&cross_call_lock, flags); | |
231 | ||
232 | /* Init function glue. */ | |
233 | ccall_info.func = func; | |
234 | ccall_info.arg1 = arg1; | |
235 | ccall_info.arg2 = arg2; | |
236 | ccall_info.arg3 = arg3; | |
237 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 238 | ccall_info.arg5 = 0; |
1da177e4 LT |
239 | |
240 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
241 | { | |
1da177e4 LT |
242 | register int i; |
243 | ||
244 | cpu_clear(smp_processor_id(), mask); | |
66e4f8c0 | 245 | cpus_and(mask, cpu_online_map, mask); |
1da177e4 LT |
246 | for(i = 0; i < ncpus; i++) { |
247 | if (cpu_isset(i, mask)) { | |
248 | ccall_info.processors_in[i] = 0; | |
249 | ccall_info.processors_out[i] = 0; | |
250 | set_cpu_int(i, IRQ_CROSS_CALL); | |
251 | } else { | |
252 | ccall_info.processors_in[i] = 1; | |
253 | ccall_info.processors_out[i] = 1; | |
254 | } | |
255 | } | |
256 | } | |
257 | ||
258 | { | |
259 | register int i; | |
260 | ||
261 | i = 0; | |
262 | do { | |
66e4f8c0 DM |
263 | if (!cpu_isset(i, mask)) |
264 | continue; | |
1da177e4 LT |
265 | while(!ccall_info.processors_in[i]) |
266 | barrier(); | |
267 | } while(++i < ncpus); | |
268 | ||
269 | i = 0; | |
270 | do { | |
66e4f8c0 DM |
271 | if (!cpu_isset(i, mask)) |
272 | continue; | |
1da177e4 LT |
273 | while(!ccall_info.processors_out[i]) |
274 | barrier(); | |
275 | } while(++i < ncpus); | |
276 | } | |
277 | ||
278 | spin_unlock_irqrestore(&cross_call_lock, flags); | |
1da177e4 LT |
279 | } |
280 | ||
281 | /* Running cross calls. */ | |
282 | void smp4m_cross_call_irq(void) | |
283 | { | |
284 | int i = smp_processor_id(); | |
285 | ||
286 | ccall_info.processors_in[i] = 1; | |
287 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
288 | ccall_info.arg4, ccall_info.arg5); | |
289 | ccall_info.processors_out[i] = 1; | |
290 | } | |
291 | ||
1de937a5 DM |
292 | extern void sun4m_clear_profile_irq(int cpu); |
293 | ||
1da177e4 LT |
294 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) |
295 | { | |
0d84438d | 296 | struct pt_regs *old_regs; |
1da177e4 LT |
297 | int cpu = smp_processor_id(); |
298 | ||
0d84438d AV |
299 | old_regs = set_irq_regs(regs); |
300 | ||
1de937a5 | 301 | sun4m_clear_profile_irq(cpu); |
1da177e4 | 302 | |
0d84438d | 303 | profile_tick(CPU_PROFILING); |
1da177e4 LT |
304 | |
305 | if(!--prof_counter(cpu)) { | |
306 | int user = user_mode(regs); | |
307 | ||
308 | irq_enter(); | |
309 | update_process_times(user); | |
310 | irq_exit(); | |
311 | ||
312 | prof_counter(cpu) = prof_multiplier(cpu); | |
313 | } | |
0d84438d | 314 | set_irq_regs(old_regs); |
1da177e4 LT |
315 | } |
316 | ||
317 | extern unsigned int lvl14_resolution; | |
318 | ||
409832f5 | 319 | static void __cpuinit smp_setup_percpu_timer(void) |
1da177e4 LT |
320 | { |
321 | int cpu = smp_processor_id(); | |
322 | ||
323 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
324 | load_profile_irq(cpu, lvl14_resolution); | |
325 | ||
326 | if(cpu == boot_cpu_id) | |
327 | enable_pil_irq(14); | |
328 | } | |
329 | ||
c61c65cd | 330 | static void __init smp4m_blackbox_id(unsigned *addr) |
1da177e4 LT |
331 | { |
332 | int rd = *addr & 0x3e000000; | |
333 | int rs1 = rd >> 11; | |
334 | ||
335 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ | |
336 | addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ | |
337 | addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */ | |
338 | } | |
339 | ||
c61c65cd | 340 | static void __init smp4m_blackbox_current(unsigned *addr) |
1da177e4 LT |
341 | { |
342 | int rd = *addr & 0x3e000000; | |
343 | int rs1 = rd >> 11; | |
344 | ||
345 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ | |
346 | addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ | |
4cad6917 | 347 | addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */ |
1da177e4 LT |
348 | } |
349 | ||
350 | void __init sun4m_init_smp(void) | |
351 | { | |
352 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id); | |
353 | BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current); | |
354 | BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM); | |
1da177e4 LT |
355 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM); |
356 | } |