Commit | Line | Data |
---|---|---|
aba20a82 SR |
1 | /* |
2 | * sun4m SMP support. | |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | */ | |
6 | ||
62f08283 | 7 | #include <linux/clockchips.h> |
1da177e4 | 8 | #include <linux/interrupt.h> |
1da177e4 | 9 | #include <linux/profile.h> |
6c81c32f | 10 | #include <linux/delay.h> |
5d83d666 | 11 | #include <linux/sched.h> |
4245e59d | 12 | #include <linux/cpu.h> |
6c81c32f | 13 | |
1da177e4 | 14 | #include <asm/cacheflush.h> |
bde4d8b2 | 15 | #include <asm/switch_to.h> |
1da177e4 | 16 | #include <asm/tlbflush.h> |
62f08283 | 17 | #include <asm/timer.h> |
5d83d666 | 18 | #include <asm/oplib.h> |
1da177e4 | 19 | |
32231a66 | 20 | #include "irq.h" |
aba20a82 | 21 | #include "kernel.h" |
32231a66 | 22 | |
ecbc42b7 DH |
23 | #define IRQ_IPI_SINGLE 12 |
24 | #define IRQ_IPI_MASK 13 | |
25 | #define IRQ_IPI_RESCHED 14 | |
1da177e4 LT |
26 | #define IRQ_CROSS_CALL 15 |
27 | ||
1a8a27c9 WF |
28 | static inline unsigned long |
29 | swap_ulong(volatile unsigned long *ptr, unsigned long val) | |
1da177e4 LT |
30 | { |
31 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
32 | "=&r" (val), "=&r" (ptr) : | |
33 | "0" (val), "1" (ptr)); | |
34 | return val; | |
35 | } | |
36 | ||
92d452f0 | 37 | void __cpuinit smp4m_callin(void) |
1da177e4 LT |
38 | { |
39 | int cpuid = hard_smp_processor_id(); | |
40 | ||
5d83d666 DM |
41 | local_ops->cache_all(); |
42 | local_ops->tlb_all(); | |
1da177e4 | 43 | |
e545a614 MS |
44 | notify_cpu_starting(cpuid); |
45 | ||
62f08283 | 46 | register_percpu_ce(cpuid); |
1da177e4 LT |
47 | |
48 | calibrate_delay(); | |
49 | smp_store_cpu_info(cpuid); | |
50 | ||
5d83d666 DM |
51 | local_ops->cache_all(); |
52 | local_ops->tlb_all(); | |
1da177e4 LT |
53 | |
54 | /* | |
55 | * Unblock the master CPU _only_ when the scheduler state | |
56 | * of all secondary CPUs will be up-to-date, so after | |
57 | * the SMP initialization the master will be just allowed | |
58 | * to call the scheduler code. | |
59 | */ | |
60 | /* Allow master to continue. */ | |
1a8a27c9 | 61 | swap_ulong(&cpu_callin_map[cpuid], 1); |
1da177e4 | 62 | |
a54123e2 | 63 | /* XXX: What's up with all the flushes? */ |
5d83d666 DM |
64 | local_ops->cache_all(); |
65 | local_ops->tlb_all(); | |
aba20a82 | 66 | |
1da177e4 LT |
67 | /* Fix idle thread fields. */ |
68 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
69 | : : "r" (¤t_set[cpuid]) | |
70 | : "memory" /* paranoid */); | |
71 | ||
72 | /* Attach to the address space of init_task. */ | |
73 | atomic_inc(&init_mm.mm_count); | |
74 | current->active_mm = &init_mm; | |
75 | ||
fb1fece5 | 76 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
a54123e2 | 77 | mb(); |
1da177e4 LT |
78 | |
79 | local_irq_enable(); | |
a54123e2 | 80 | |
fe73971c | 81 | set_cpu_online(cpuid, true); |
1da177e4 LT |
82 | } |
83 | ||
1da177e4 LT |
84 | /* |
85 | * Cycle through the processors asking the PROM to start each one. | |
86 | */ | |
1da177e4 LT |
87 | void __init smp4m_boot_cpus(void) |
88 | { | |
62f08283 | 89 | sun4m_unmask_profile_irq(); |
5d83d666 | 90 | local_ops->cache_all(); |
a54123e2 | 91 | } |
1da177e4 | 92 | |
92d452f0 | 93 | int __cpuinit smp4m_boot_one_cpu(int i) |
a54123e2 | 94 | { |
a54123e2 BB |
95 | unsigned long *entry = &sun4m_cpu_startup; |
96 | struct task_struct *p; | |
97 | int timeout; | |
98 | int cpu_node; | |
1da177e4 | 99 | |
a54123e2 BB |
100 | cpu_find_by_mid(i, &cpu_node); |
101 | ||
102 | /* Cook up an idler for this guy. */ | |
103 | p = fork_idle(i); | |
104 | current_set[i] = task_thread_info(p); | |
105 | /* See trampoline.S for details... */ | |
aba20a82 | 106 | entry += ((i - 1) * 3); |
1da177e4 | 107 | |
a54123e2 BB |
108 | /* |
109 | * Initialize the contexts table | |
110 | * Since the call to prom_startcpu() trashes the structure, | |
111 | * we need to re-initialize it for each cpu | |
112 | */ | |
113 | smp_penguin_ctable.which_io = 0; | |
114 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
115 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 116 | |
a54123e2 | 117 | /* whirrr, whirrr, whirrrrrrrrr... */ |
aba20a82 | 118 | printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); |
5d83d666 | 119 | local_ops->cache_all(); |
aba20a82 | 120 | prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); |
a54123e2 BB |
121 | |
122 | /* wheee... it's going... */ | |
aba20a82 SR |
123 | for (timeout = 0; timeout < 10000; timeout++) { |
124 | if (cpu_callin_map[i]) | |
a54123e2 BB |
125 | break; |
126 | udelay(200); | |
1da177e4 LT |
127 | } |
128 | ||
a54123e2 | 129 | if (!(cpu_callin_map[i])) { |
aba20a82 | 130 | printk(KERN_ERR "Processor %d is stuck.\n", i); |
a54123e2 BB |
131 | return -ENODEV; |
132 | } | |
1da177e4 | 133 | |
5d83d666 | 134 | local_ops->cache_all(); |
a54123e2 BB |
135 | return 0; |
136 | } | |
137 | ||
138 | void __init smp4m_smp_done(void) | |
139 | { | |
140 | int i, first; | |
141 | int *prev; | |
142 | ||
143 | /* setup cpu list for irq rotation */ | |
144 | first = 0; | |
145 | prev = &first; | |
ec7c14bd RR |
146 | for_each_online_cpu(i) { |
147 | *prev = i; | |
148 | prev = &cpu_data(i).next; | |
1da177e4 | 149 | } |
a54123e2 | 150 | *prev = first; |
5d83d666 | 151 | local_ops->cache_all(); |
1da177e4 | 152 | |
1da177e4 | 153 | /* Ok, they are spinning and ready to go. */ |
1da177e4 LT |
154 | } |
155 | ||
4ba22b16 | 156 | static void sun4m_send_ipi(int cpu, int level) |
ecbc42b7 | 157 | { |
4ba22b16 | 158 | sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set); |
ecbc42b7 DH |
159 | } |
160 | ||
4ba22b16 | 161 | static void sun4m_ipi_resched(int cpu) |
ecbc42b7 | 162 | { |
4ba22b16 | 163 | sun4m_send_ipi(cpu, IRQ_IPI_RESCHED); |
ecbc42b7 DH |
164 | } |
165 | ||
4ba22b16 | 166 | static void sun4m_ipi_single(int cpu) |
ecbc42b7 | 167 | { |
4ba22b16 | 168 | sun4m_send_ipi(cpu, IRQ_IPI_SINGLE); |
ecbc42b7 DH |
169 | } |
170 | ||
4ba22b16 | 171 | static void sun4m_ipi_mask_one(int cpu) |
ecbc42b7 | 172 | { |
4ba22b16 | 173 | sun4m_send_ipi(cpu, IRQ_IPI_MASK); |
ecbc42b7 DH |
174 | } |
175 | ||
1da177e4 LT |
176 | static struct smp_funcall { |
177 | smpfunc_t func; | |
178 | unsigned long arg1; | |
179 | unsigned long arg2; | |
180 | unsigned long arg3; | |
181 | unsigned long arg4; | |
182 | unsigned long arg5; | |
a54123e2 BB |
183 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
184 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
185 | } ccall_info; |
186 | ||
187 | static DEFINE_SPINLOCK(cross_call_lock); | |
188 | ||
189 | /* Cross calls must be serialized, at least currently. */ | |
4ba22b16 | 190 | static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 191 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 192 | unsigned long arg4) |
1da177e4 | 193 | { |
a54123e2 | 194 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
195 | unsigned long flags; |
196 | ||
197 | spin_lock_irqsave(&cross_call_lock, flags); | |
198 | ||
199 | /* Init function glue. */ | |
200 | ccall_info.func = func; | |
201 | ccall_info.arg1 = arg1; | |
202 | ccall_info.arg2 = arg2; | |
203 | ccall_info.arg3 = arg3; | |
204 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 205 | ccall_info.arg5 = 0; |
1da177e4 LT |
206 | |
207 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
208 | { | |
1da177e4 LT |
209 | register int i; |
210 | ||
fb1fece5 KM |
211 | cpumask_clear_cpu(smp_processor_id(), &mask); |
212 | cpumask_and(&mask, cpu_online_mask, &mask); | |
aba20a82 | 213 | for (i = 0; i < ncpus; i++) { |
fb1fece5 | 214 | if (cpumask_test_cpu(i, &mask)) { |
1da177e4 LT |
215 | ccall_info.processors_in[i] = 0; |
216 | ccall_info.processors_out[i] = 0; | |
4ba22b16 | 217 | sun4m_send_ipi(i, IRQ_CROSS_CALL); |
1da177e4 LT |
218 | } else { |
219 | ccall_info.processors_in[i] = 1; | |
220 | ccall_info.processors_out[i] = 1; | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
225 | { | |
226 | register int i; | |
227 | ||
228 | i = 0; | |
229 | do { | |
fb1fece5 | 230 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 231 | continue; |
aba20a82 | 232 | while (!ccall_info.processors_in[i]) |
1da177e4 | 233 | barrier(); |
aba20a82 | 234 | } while (++i < ncpus); |
1da177e4 LT |
235 | |
236 | i = 0; | |
237 | do { | |
fb1fece5 | 238 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 239 | continue; |
aba20a82 | 240 | while (!ccall_info.processors_out[i]) |
1da177e4 | 241 | barrier(); |
aba20a82 | 242 | } while (++i < ncpus); |
1da177e4 | 243 | } |
1da177e4 | 244 | spin_unlock_irqrestore(&cross_call_lock, flags); |
1da177e4 LT |
245 | } |
246 | ||
247 | /* Running cross calls. */ | |
248 | void smp4m_cross_call_irq(void) | |
249 | { | |
250 | int i = smp_processor_id(); | |
251 | ||
252 | ccall_info.processors_in[i] = 1; | |
253 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
254 | ccall_info.arg4, ccall_info.arg5); | |
255 | ccall_info.processors_out[i] = 1; | |
256 | } | |
257 | ||
258 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) | |
259 | { | |
0d84438d | 260 | struct pt_regs *old_regs; |
62f08283 | 261 | struct clock_event_device *ce; |
1da177e4 LT |
262 | int cpu = smp_processor_id(); |
263 | ||
0d84438d AV |
264 | old_regs = set_irq_regs(regs); |
265 | ||
62f08283 | 266 | ce = &per_cpu(sparc32_clockevent, cpu); |
1da177e4 | 267 | |
62f08283 TK |
268 | if (ce->mode & CLOCK_EVT_MODE_PERIODIC) |
269 | sun4m_clear_profile_irq(cpu); | |
270 | else | |
271 | load_profile_irq(cpu, 0); /* Is this needless? */ | |
1da177e4 | 272 | |
62f08283 TK |
273 | irq_enter(); |
274 | ce->event_handler(ce); | |
275 | irq_exit(); | |
1da177e4 | 276 | |
0d84438d | 277 | set_irq_regs(old_regs); |
1da177e4 LT |
278 | } |
279 | ||
4ba22b16 SR |
280 | static const struct sparc32_ipi_ops sun4m_ipi_ops = { |
281 | .cross_call = sun4m_cross_call, | |
282 | .resched = sun4m_ipi_resched, | |
283 | .single = sun4m_ipi_single, | |
284 | .mask_one = sun4m_ipi_mask_one, | |
285 | }; | |
286 | ||
1da177e4 LT |
287 | void __init sun4m_init_smp(void) |
288 | { | |
4ba22b16 | 289 | sparc32_ipi_ops = &sun4m_ipi_ops; |
1da177e4 | 290 | } |