Commit | Line | Data |
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1da177e4 LT |
1 | /* sun4m_smp.c: Sparc SUN4M SMP support. |
2 | * | |
3 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <asm/head.h> | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/threads.h> | |
11 | #include <linux/smp.h> | |
1da177e4 LT |
12 | #include <linux/interrupt.h> |
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/swap.h> | |
18 | #include <linux/profile.h> | |
6c81c32f | 19 | #include <linux/delay.h> |
4245e59d | 20 | #include <linux/cpu.h> |
6c81c32f | 21 | |
1da177e4 LT |
22 | #include <asm/cacheflush.h> |
23 | #include <asm/tlbflush.h> | |
0d84438d | 24 | #include <asm/irq_regs.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/atomic.h> | |
28 | ||
1da177e4 LT |
29 | #include <asm/irq.h> |
30 | #include <asm/page.h> | |
31 | #include <asm/pgalloc.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/oplib.h> | |
34 | #include <asm/cpudata.h> | |
35 | ||
32231a66 AV |
36 | #include "irq.h" |
37 | ||
1da177e4 LT |
38 | #define IRQ_CROSS_CALL 15 |
39 | ||
40 | extern ctxd_t *srmmu_ctx_table_phys; | |
41 | ||
1da177e4 LT |
42 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; |
43 | extern unsigned char boot_cpu_id; | |
a54123e2 BB |
44 | |
45 | extern cpumask_t smp_commenced_mask; | |
46 | ||
1da177e4 LT |
47 | extern int __smp4m_processor_id(void); |
48 | ||
49 | /*#define SMP_DEBUG*/ | |
50 | ||
51 | #ifdef SMP_DEBUG | |
52 | #define SMP_PRINTK(x) printk x | |
53 | #else | |
54 | #define SMP_PRINTK(x) | |
55 | #endif | |
56 | ||
57 | static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val) | |
58 | { | |
59 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
60 | "=&r" (val), "=&r" (ptr) : | |
61 | "0" (val), "1" (ptr)); | |
62 | return val; | |
63 | } | |
64 | ||
65 | static void smp_setup_percpu_timer(void); | |
66 | extern void cpu_probe(void); | |
67 | ||
92d452f0 | 68 | void __cpuinit smp4m_callin(void) |
1da177e4 LT |
69 | { |
70 | int cpuid = hard_smp_processor_id(); | |
71 | ||
72 | local_flush_cache_all(); | |
73 | local_flush_tlb_all(); | |
74 | ||
e545a614 MS |
75 | notify_cpu_starting(cpuid); |
76 | ||
1da177e4 LT |
77 | /* Get our local ticker going. */ |
78 | smp_setup_percpu_timer(); | |
79 | ||
80 | calibrate_delay(); | |
81 | smp_store_cpu_info(cpuid); | |
82 | ||
83 | local_flush_cache_all(); | |
84 | local_flush_tlb_all(); | |
85 | ||
86 | /* | |
87 | * Unblock the master CPU _only_ when the scheduler state | |
88 | * of all secondary CPUs will be up-to-date, so after | |
89 | * the SMP initialization the master will be just allowed | |
90 | * to call the scheduler code. | |
91 | */ | |
92 | /* Allow master to continue. */ | |
a54123e2 | 93 | swap(&cpu_callin_map[cpuid], 1); |
1da177e4 | 94 | |
a54123e2 | 95 | /* XXX: What's up with all the flushes? */ |
1da177e4 LT |
96 | local_flush_cache_all(); |
97 | local_flush_tlb_all(); | |
98 | ||
99 | cpu_probe(); | |
100 | ||
101 | /* Fix idle thread fields. */ | |
102 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
103 | : : "r" (¤t_set[cpuid]) | |
104 | : "memory" /* paranoid */); | |
105 | ||
106 | /* Attach to the address space of init_task. */ | |
107 | atomic_inc(&init_mm.mm_count); | |
108 | current->active_mm = &init_mm; | |
109 | ||
a54123e2 BB |
110 | while (!cpu_isset(cpuid, smp_commenced_mask)) |
111 | mb(); | |
1da177e4 LT |
112 | |
113 | local_irq_enable(); | |
a54123e2 BB |
114 | |
115 | cpu_set(cpuid, cpu_online_map); | |
1da177e4 LT |
116 | } |
117 | ||
1da177e4 LT |
118 | /* |
119 | * Cycle through the processors asking the PROM to start each one. | |
120 | */ | |
121 | ||
122 | extern struct linux_prom_registers smp_penguin_ctable; | |
123 | extern unsigned long trapbase_cpu1[]; | |
124 | extern unsigned long trapbase_cpu2[]; | |
125 | extern unsigned long trapbase_cpu3[]; | |
126 | ||
127 | void __init smp4m_boot_cpus(void) | |
128 | { | |
a54123e2 BB |
129 | smp_setup_percpu_timer(); |
130 | local_flush_cache_all(); | |
131 | } | |
1da177e4 | 132 | |
92d452f0 | 133 | int __cpuinit smp4m_boot_one_cpu(int i) |
a54123e2 BB |
134 | { |
135 | extern unsigned long sun4m_cpu_startup; | |
136 | unsigned long *entry = &sun4m_cpu_startup; | |
137 | struct task_struct *p; | |
138 | int timeout; | |
139 | int cpu_node; | |
1da177e4 | 140 | |
a54123e2 BB |
141 | cpu_find_by_mid(i, &cpu_node); |
142 | ||
143 | /* Cook up an idler for this guy. */ | |
144 | p = fork_idle(i); | |
145 | current_set[i] = task_thread_info(p); | |
146 | /* See trampoline.S for details... */ | |
147 | entry += ((i-1) * 3); | |
1da177e4 | 148 | |
a54123e2 BB |
149 | /* |
150 | * Initialize the contexts table | |
151 | * Since the call to prom_startcpu() trashes the structure, | |
152 | * we need to re-initialize it for each cpu | |
153 | */ | |
154 | smp_penguin_ctable.which_io = 0; | |
155 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
156 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 157 | |
a54123e2 BB |
158 | /* whirrr, whirrr, whirrrrrrrrr... */ |
159 | printk("Starting CPU %d at %p\n", i, entry); | |
160 | local_flush_cache_all(); | |
161 | prom_startcpu(cpu_node, | |
162 | &smp_penguin_ctable, 0, (char *)entry); | |
163 | ||
164 | /* wheee... it's going... */ | |
165 | for(timeout = 0; timeout < 10000; timeout++) { | |
166 | if(cpu_callin_map[i]) | |
167 | break; | |
168 | udelay(200); | |
1da177e4 LT |
169 | } |
170 | ||
a54123e2 BB |
171 | if (!(cpu_callin_map[i])) { |
172 | printk("Processor %d is stuck.\n", i); | |
173 | return -ENODEV; | |
174 | } | |
1da177e4 | 175 | |
1da177e4 | 176 | local_flush_cache_all(); |
a54123e2 BB |
177 | return 0; |
178 | } | |
179 | ||
180 | void __init smp4m_smp_done(void) | |
181 | { | |
182 | int i, first; | |
183 | int *prev; | |
184 | ||
185 | /* setup cpu list for irq rotation */ | |
186 | first = 0; | |
187 | prev = &first; | |
188 | for (i = 0; i < NR_CPUS; i++) { | |
189 | if (cpu_online(i)) { | |
190 | *prev = i; | |
191 | prev = &cpu_data(i).next; | |
1da177e4 LT |
192 | } |
193 | } | |
a54123e2 | 194 | *prev = first; |
1da177e4 | 195 | local_flush_cache_all(); |
1da177e4 LT |
196 | |
197 | /* Free unneeded trap tables */ | |
a54123e2 | 198 | if (!cpu_isset(1, cpu_present_map)) { |
1da177e4 | 199 | ClearPageReserved(virt_to_page(trapbase_cpu1)); |
7835e98b | 200 | init_page_count(virt_to_page(trapbase_cpu1)); |
1da177e4 LT |
201 | free_page((unsigned long)trapbase_cpu1); |
202 | totalram_pages++; | |
203 | num_physpages++; | |
204 | } | |
205 | if (!cpu_isset(2, cpu_present_map)) { | |
206 | ClearPageReserved(virt_to_page(trapbase_cpu2)); | |
7835e98b | 207 | init_page_count(virt_to_page(trapbase_cpu2)); |
1da177e4 LT |
208 | free_page((unsigned long)trapbase_cpu2); |
209 | totalram_pages++; | |
210 | num_physpages++; | |
211 | } | |
212 | if (!cpu_isset(3, cpu_present_map)) { | |
213 | ClearPageReserved(virt_to_page(trapbase_cpu3)); | |
7835e98b | 214 | init_page_count(virt_to_page(trapbase_cpu3)); |
1da177e4 LT |
215 | free_page((unsigned long)trapbase_cpu3); |
216 | totalram_pages++; | |
217 | num_physpages++; | |
218 | } | |
219 | ||
220 | /* Ok, they are spinning and ready to go. */ | |
1da177e4 LT |
221 | } |
222 | ||
223 | /* At each hardware IRQ, we get this called to forward IRQ reception | |
224 | * to the next processor. The caller must disable the IRQ level being | |
225 | * serviced globally so that there are no double interrupts received. | |
226 | * | |
227 | * XXX See sparc64 irq.c. | |
228 | */ | |
229 | void smp4m_irq_rotate(int cpu) | |
230 | { | |
a54123e2 BB |
231 | int next = cpu_data(cpu).next; |
232 | if (next != cpu) | |
233 | set_irq_udt(next); | |
1da177e4 LT |
234 | } |
235 | ||
1da177e4 LT |
236 | static struct smp_funcall { |
237 | smpfunc_t func; | |
238 | unsigned long arg1; | |
239 | unsigned long arg2; | |
240 | unsigned long arg3; | |
241 | unsigned long arg4; | |
242 | unsigned long arg5; | |
a54123e2 BB |
243 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
244 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
245 | } ccall_info; |
246 | ||
247 | static DEFINE_SPINLOCK(cross_call_lock); | |
248 | ||
249 | /* Cross calls must be serialized, at least currently. */ | |
66e4f8c0 | 250 | static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 251 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 252 | unsigned long arg4) |
1da177e4 | 253 | { |
a54123e2 | 254 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
255 | unsigned long flags; |
256 | ||
257 | spin_lock_irqsave(&cross_call_lock, flags); | |
258 | ||
259 | /* Init function glue. */ | |
260 | ccall_info.func = func; | |
261 | ccall_info.arg1 = arg1; | |
262 | ccall_info.arg2 = arg2; | |
263 | ccall_info.arg3 = arg3; | |
264 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 265 | ccall_info.arg5 = 0; |
1da177e4 LT |
266 | |
267 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
268 | { | |
1da177e4 LT |
269 | register int i; |
270 | ||
271 | cpu_clear(smp_processor_id(), mask); | |
66e4f8c0 | 272 | cpus_and(mask, cpu_online_map, mask); |
1da177e4 LT |
273 | for(i = 0; i < ncpus; i++) { |
274 | if (cpu_isset(i, mask)) { | |
275 | ccall_info.processors_in[i] = 0; | |
276 | ccall_info.processors_out[i] = 0; | |
277 | set_cpu_int(i, IRQ_CROSS_CALL); | |
278 | } else { | |
279 | ccall_info.processors_in[i] = 1; | |
280 | ccall_info.processors_out[i] = 1; | |
281 | } | |
282 | } | |
283 | } | |
284 | ||
285 | { | |
286 | register int i; | |
287 | ||
288 | i = 0; | |
289 | do { | |
66e4f8c0 DM |
290 | if (!cpu_isset(i, mask)) |
291 | continue; | |
1da177e4 LT |
292 | while(!ccall_info.processors_in[i]) |
293 | barrier(); | |
294 | } while(++i < ncpus); | |
295 | ||
296 | i = 0; | |
297 | do { | |
66e4f8c0 DM |
298 | if (!cpu_isset(i, mask)) |
299 | continue; | |
1da177e4 LT |
300 | while(!ccall_info.processors_out[i]) |
301 | barrier(); | |
302 | } while(++i < ncpus); | |
303 | } | |
304 | ||
305 | spin_unlock_irqrestore(&cross_call_lock, flags); | |
1da177e4 LT |
306 | } |
307 | ||
308 | /* Running cross calls. */ | |
309 | void smp4m_cross_call_irq(void) | |
310 | { | |
311 | int i = smp_processor_id(); | |
312 | ||
313 | ccall_info.processors_in[i] = 1; | |
314 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
315 | ccall_info.arg4, ccall_info.arg5); | |
316 | ccall_info.processors_out[i] = 1; | |
317 | } | |
318 | ||
1de937a5 DM |
319 | extern void sun4m_clear_profile_irq(int cpu); |
320 | ||
1da177e4 LT |
321 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) |
322 | { | |
0d84438d | 323 | struct pt_regs *old_regs; |
1da177e4 LT |
324 | int cpu = smp_processor_id(); |
325 | ||
0d84438d AV |
326 | old_regs = set_irq_regs(regs); |
327 | ||
1de937a5 | 328 | sun4m_clear_profile_irq(cpu); |
1da177e4 | 329 | |
0d84438d | 330 | profile_tick(CPU_PROFILING); |
1da177e4 LT |
331 | |
332 | if(!--prof_counter(cpu)) { | |
333 | int user = user_mode(regs); | |
334 | ||
335 | irq_enter(); | |
336 | update_process_times(user); | |
337 | irq_exit(); | |
338 | ||
339 | prof_counter(cpu) = prof_multiplier(cpu); | |
340 | } | |
0d84438d | 341 | set_irq_regs(old_regs); |
1da177e4 LT |
342 | } |
343 | ||
344 | extern unsigned int lvl14_resolution; | |
345 | ||
346 | static void __init smp_setup_percpu_timer(void) | |
347 | { | |
348 | int cpu = smp_processor_id(); | |
349 | ||
350 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
351 | load_profile_irq(cpu, lvl14_resolution); | |
352 | ||
353 | if(cpu == boot_cpu_id) | |
354 | enable_pil_irq(14); | |
355 | } | |
356 | ||
c61c65cd | 357 | static void __init smp4m_blackbox_id(unsigned *addr) |
1da177e4 LT |
358 | { |
359 | int rd = *addr & 0x3e000000; | |
360 | int rs1 = rd >> 11; | |
361 | ||
362 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ | |
363 | addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ | |
364 | addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */ | |
365 | } | |
366 | ||
c61c65cd | 367 | static void __init smp4m_blackbox_current(unsigned *addr) |
1da177e4 LT |
368 | { |
369 | int rd = *addr & 0x3e000000; | |
370 | int rs1 = rd >> 11; | |
371 | ||
372 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ | |
373 | addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ | |
4cad6917 | 374 | addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */ |
1da177e4 LT |
375 | } |
376 | ||
377 | void __init sun4m_init_smp(void) | |
378 | { | |
379 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id); | |
380 | BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current); | |
381 | BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM); | |
1da177e4 LT |
382 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM); |
383 | } |