[deliverable/linux.git] / arch / sparc / kernel / sun4m_smp.c

/* sun4m_smp.c: Sparc SUN4M SMP support.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <asm/head.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/profile.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/irq_regs.h>

#include <asm/ptrace.h>
#include <asm/atomic.h>

#include <asm/delay.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/cpudata.h>

#define IRQ_RESCHEDULE		13
#define IRQ_STOP_CPU		14
#define IRQ_CROSS_CALL		15

extern ctxd_t *srmmu_ctx_table_phys;

extern void calibrate_delay(void);

extern volatile unsigned long cpu_callin_map[NR_CPUS];
extern unsigned char boot_cpu_id;

extern cpumask_t smp_commenced_mask;

extern int __smp4m_processor_id(void);

/*#define SMP_DEBUG*/

#ifdef SMP_DEBUG
#define SMP_PRINTK(x)	printk x
#else
#define SMP_PRINTK(x)
#endif

static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp_setup_percpu_timer(void);
extern void cpu_probe(void);

void __cpuinit smp4m_callin(void)
{
	int cpuid = hard_smp_processor_id();

	local_flush_cache_all();
	local_flush_tlb_all();

	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);

	local_flush_cache_all();
	local_flush_tlb_all();

	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Allow master to continue. */
	swap(&cpu_callin_map[cpuid], 1);

	/* XXX: What's up with all the flushes? */
	local_flush_cache_all();
	local_flush_tlb_all();
	
	cpu_probe();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	while (!cpu_isset(cpuid, smp_commenced_mask))
		mb();

	local_irq_enable();

	cpu_set(cpuid, cpu_online_map);
}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
 
extern struct linux_prom_registers smp_penguin_ctable;
extern unsigned long trapbase_cpu1[];
extern unsigned long trapbase_cpu2[];
extern unsigned long trapbase_cpu3[];

void __init smp4m_boot_cpus(void)
{
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int __cpuinit smp4m_boot_one_cpu(int i)
{
	extern unsigned long sun4m_cpu_startup;
	unsigned long *entry = &sun4m_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_mid(i, &cpu_node);

	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);
	/* See trampoline.S for details... */
	entry += ((i-1) * 3);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk("Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	/* wheee... it's going... */
	for(timeout = 0; timeout < 10000; timeout++) {
		if(cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk("Processor %d is stuck.\n", i);
		return -ENODEV;
	}

	local_flush_cache_all();
	return 0;
}

void __init smp4m_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for (i = 0; i < NR_CPUS; i++) {
		if (cpu_online(i)) {
			*prev = i;
			prev = &cpu_data(i).next;
		}
	}
	*prev = first;
	local_flush_cache_all();

	/* Free unneeded trap tables */
	if (!cpu_isset(1, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu1));
		init_page_count(virt_to_page(trapbase_cpu1));
		free_page((unsigned long)trapbase_cpu1);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(2, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu2));
		init_page_count(virt_to_page(trapbase_cpu2));
		free_page((unsigned long)trapbase_cpu2);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(3, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu3));
		init_page_count(virt_to_page(trapbase_cpu3));
		free_page((unsigned long)trapbase_cpu3);
		totalram_pages++;
		num_physpages++;
	}

	/* Ok, they are spinning and ready to go. */
}

/* At each hardware IRQ, we get this called to forward IRQ reception
 * to the next processor.  The caller must disable the IRQ level being
 * serviced globally so that there are no double interrupts received.
 *
 * XXX See sparc64 irq.c.
 */
void smp4m_irq_rotate(int cpu)
{
	int next = cpu_data(cpu).next;
	if (next != cpu)
		set_irq_udt(next);
}

/* Cross calls, in order to work efficiently and atomically do all
 * the message passing work themselves, only stopcpu and reschedule
 * messages come through here.
 */
void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
{
	static unsigned long smp_cpu_in_msg[NR_CPUS];
	cpumask_t mask;
	int me = smp_processor_id();
	int irq, i;

	if(msg == MSG_RESCHEDULE) {
		irq = IRQ_RESCHEDULE;

		if(smp_cpu_in_msg[me])
			return;
	} else if(msg == MSG_STOP_CPU) {
		irq = IRQ_STOP_CPU;
	} else {
		goto barf;
	}

	smp_cpu_in_msg[me]++;
	if(target == MSG_ALL_BUT_SELF || target == MSG_ALL) {
		mask = cpu_online_map;
		if(target == MSG_ALL_BUT_SELF)
			cpu_clear(me, mask);
		for(i = 0; i < 4; i++) {
			if (cpu_isset(i, mask))
				set_cpu_int(i, irq);
		}
	} else {
		set_cpu_int(target, irq);
	}
	smp_cpu_in_msg[me]--;

	return;
barf:
	printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
	panic("Bogon SMP message pass.");
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned long processors_in[SUN4M_NCPUS];  /* Set when ipi entered. */
	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
} ccall_info;

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
void smp4m_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
		    unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
		register int ncpus = SUN4M_NCPUS;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		/* Init function glue. */
		ccall_info.func = func;
		ccall_info.arg1 = arg1;
		ccall_info.arg2 = arg2;
		ccall_info.arg3 = arg3;
		ccall_info.arg4 = arg4;
		ccall_info.arg5 = arg5;

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			cpumask_t mask = cpu_online_map;
			register int i;

			cpu_clear(smp_processor_id(), mask);
			for(i = 0; i < ncpus; i++) {
				if (cpu_isset(i, mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					set_cpu_int(i, IRQ_CROSS_CALL);
				} else {
					ccall_info.processors_in[i] = 1;
					ccall_info.processors_out[i] = 1;
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				while(!ccall_info.processors_in[i])
					barrier();
			} while(++i < ncpus);

			i = 0;
			do {
				while(!ccall_info.processors_out[i])
					barrier();
			} while(++i < ncpus);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
}

/* Running cross calls. */
void smp4m_cross_call_irq(void)
{
	int i = smp_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = smp_processor_id();

	old_regs = set_irq_regs(regs);

	clear_profile_irq(cpu);

	profile_tick(CPU_PROFILING);

	if(!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
	set_irq_regs(old_regs);
}

extern unsigned int lvl14_resolution;

static void __init smp_setup_percpu_timer(void)
{
	int cpu = smp_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);

	if(cpu == boot_cpu_id)
		enable_pil_irq(14);
}

void __init smp4m_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[1] = 0x8130200c | rd | rs1;    	/* srl reg, 0xc, reg */
	addr[2] = 0x80082003 | rd | rs1;	/* and reg, 3, reg */
}

void __init smp4m_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[2] = 0x8130200a | rd | rs1;    	/* srl reg, 0xa, reg */
	addr[4] = 0x8008200c | rd | rs1;	/* and reg, 3, reg */
}

void __init sun4m_init_smp(void)
{
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
}
Commit	Line	Data
1da177e4 LT	1	/* sun4m_smp.c: Sparc SUN4M SMP support.
	2	*
	3	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	4	*/
	5
	6	#include <asm/head.h>
	7
	8	#include <linux/kernel.h>
	9	#include <linux/sched.h>
	10	#include <linux/threads.h>
	11	#include <linux/smp.h>
	12	#include <linux/smp_lock.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/init.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/mm.h>
	18	#include <linux/swap.h>
	19	#include <linux/profile.h>
	20	#include <asm/cacheflush.h>
	21	#include <asm/tlbflush.h>
0d84438d	22	#include <asm/irq_regs.h>
1da177e4 LT	23
	24	#include <asm/ptrace.h>
	25	#include <asm/atomic.h>
	26
	27	#include <asm/delay.h>
	28	#include <asm/irq.h>
	29	#include <asm/page.h>
	30	#include <asm/pgalloc.h>
	31	#include <asm/pgtable.h>
	32	#include <asm/oplib.h>
	33	#include <asm/cpudata.h>
	34
	35	#define IRQ_RESCHEDULE 13
	36	#define IRQ_STOP_CPU 14
	37	#define IRQ_CROSS_CALL 15
	38
	39	extern ctxd_t *srmmu_ctx_table_phys;
	40
	41	extern void calibrate_delay(void);
	42
1da177e4 LT	43	extern volatile unsigned long cpu_callin_map[NR_CPUS];
1da177e4 LT	44	extern unsigned char boot_cpu_id;
a54123e2 BB	45
	46	extern cpumask_t smp_commenced_mask;
	47
1da177e4 LT	48	extern int __smp4m_processor_id(void);
	49
	50	/#define SMP_DEBUG/
	51
	52	#ifdef SMP_DEBUG
	53	#define SMP_PRINTK(x) printk x
	54	#else
	55	#define SMP_PRINTK(x)
	56	#endif
	57
	58	static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
	59	{
	60	__asm__ __volatile__("swap [%1], %0\n\t" :
	61	"=&r" (val), "=&r" (ptr) :
	62	"0" (val), "1" (ptr));
	63	return val;
	64	}
	65
	66	static void smp_setup_percpu_timer(void);
	67	extern void cpu_probe(void);
	68
92d452f0	69	void __cpuinit smp4m_callin(void)
1da177e4 LT	70	{
	71	int cpuid = hard_smp_processor_id();
	72
	73	local_flush_cache_all();
	74	local_flush_tlb_all();
	75
1da177e4 LT	76	/* Get our local ticker going. */
	77	smp_setup_percpu_timer();
	78
	79	calibrate_delay();
	80	smp_store_cpu_info(cpuid);
	81
	82	local_flush_cache_all();
	83	local_flush_tlb_all();
	84
	85	/*
	86	* Unblock the master CPU _only_ when the scheduler state
	87	* of all secondary CPUs will be up-to-date, so after
	88	* the SMP initialization the master will be just allowed
	89	* to call the scheduler code.
	90	*/
	91	/* Allow master to continue. */
a54123e2	92	swap(&cpu_callin_map[cpuid], 1);
1da177e4	93
a54123e2	94	/* XXX: What's up with all the flushes? */
1da177e4 LT	95	local_flush_cache_all();
	96	local_flush_tlb_all();
	97
	98	cpu_probe();
	99
	100	/* Fix idle thread fields. */
	101	__asm__ __volatile__("ld [%0], %%g6\n\t"
	102	: : "r" (&current_set[cpuid])
	103	: "memory" /* paranoid */);
	104
	105	/* Attach to the address space of init_task. */
	106	atomic_inc(&init_mm.mm_count);
	107	current->active_mm = &init_mm;
	108
a54123e2 BB	109	while (!cpu_isset(cpuid, smp_commenced_mask))
a54123e2 BB	110	mb();
1da177e4 LT	111
1da177e4 LT	112	local_irq_enable();
a54123e2 BB	113
a54123e2 BB	114	cpu_set(cpuid, cpu_online_map);
1da177e4 LT	115	}
1da177e4 LT	116
1da177e4 LT	117	/*
	118	* Cycle through the processors asking the PROM to start each one.
	119	*/
	120
	121	extern struct linux_prom_registers smp_penguin_ctable;
	122	extern unsigned long trapbase_cpu1[];
	123	extern unsigned long trapbase_cpu2[];
	124	extern unsigned long trapbase_cpu3[];
	125
	126	void __init smp4m_boot_cpus(void)
	127	{
a54123e2 BB	128	smp_setup_percpu_timer();
	129	local_flush_cache_all();
	130	}
1da177e4	131
92d452f0	132	int __cpuinit smp4m_boot_one_cpu(int i)
a54123e2 BB	133	{
	134	extern unsigned long sun4m_cpu_startup;
	135	unsigned long *entry = &sun4m_cpu_startup;
	136	struct task_struct *p;
	137	int timeout;
	138	int cpu_node;
1da177e4	139
a54123e2 BB	140	cpu_find_by_mid(i, &cpu_node);
	141
	142	/* Cook up an idler for this guy. */
	143	p = fork_idle(i);
	144	current_set[i] = task_thread_info(p);
	145	/* See trampoline.S for details... */
	146	entry += ((i-1) * 3);
1da177e4	147
a54123e2 BB	148	/*
	149	* Initialize the contexts table
	150	* Since the call to prom_startcpu() trashes the structure,
	151	* we need to re-initialize it for each cpu
	152	*/
	153	smp_penguin_ctable.which_io = 0;
	154	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	155	smp_penguin_ctable.reg_size = 0;
1da177e4	156
a54123e2 BB	157	/* whirrr, whirrr, whirrrrrrrrr... */
	158	printk("Starting CPU %d at %p\n", i, entry);
	159	local_flush_cache_all();
	160	prom_startcpu(cpu_node,
	161	&smp_penguin_ctable, 0, (char *)entry);
	162
	163	/* wheee... it's going... */
	164	for(timeout = 0; timeout < 10000; timeout++) {
	165	if(cpu_callin_map[i])
	166	break;
	167	udelay(200);
1da177e4 LT	168	}
1da177e4 LT	169
a54123e2 BB	170	if (!(cpu_callin_map[i])) {
	171	printk("Processor %d is stuck.\n", i);
	172	return -ENODEV;
	173	}
1da177e4	174
1da177e4	175	local_flush_cache_all();
a54123e2 BB	176	return 0;
	177	}
	178
	179	void __init smp4m_smp_done(void)
	180	{
	181	int i, first;
	182	int *prev;
	183
	184	/* setup cpu list for irq rotation */
	185	first = 0;
	186	prev = &first;
	187	for (i = 0; i < NR_CPUS; i++) {
	188	if (cpu_online(i)) {
	189	*prev = i;
	190	prev = &cpu_data(i).next;
1da177e4 LT	191	}
1da177e4 LT	192	}
a54123e2	193	*prev = first;
1da177e4	194	local_flush_cache_all();
1da177e4 LT	195
1da177e4 LT	196	/* Free unneeded trap tables */
a54123e2	197	if (!cpu_isset(1, cpu_present_map)) {
1da177e4	198	ClearPageReserved(virt_to_page(trapbase_cpu1));
7835e98b	199	init_page_count(virt_to_page(trapbase_cpu1));
1da177e4 LT	200	free_page((unsigned long)trapbase_cpu1);
	201	totalram_pages++;
	202	num_physpages++;
	203	}
	204	if (!cpu_isset(2, cpu_present_map)) {
	205	ClearPageReserved(virt_to_page(trapbase_cpu2));
7835e98b	206	init_page_count(virt_to_page(trapbase_cpu2));
1da177e4 LT	207	free_page((unsigned long)trapbase_cpu2);
	208	totalram_pages++;
	209	num_physpages++;
	210	}
	211	if (!cpu_isset(3, cpu_present_map)) {
	212	ClearPageReserved(virt_to_page(trapbase_cpu3));
7835e98b	213	init_page_count(virt_to_page(trapbase_cpu3));
1da177e4 LT	214	free_page((unsigned long)trapbase_cpu3);
	215	totalram_pages++;
	216	num_physpages++;
	217	}
	218
	219	/* Ok, they are spinning and ready to go. */
1da177e4 LT	220	}
	221
	222	/* At each hardware IRQ, we get this called to forward IRQ reception
	223	* to the next processor. The caller must disable the IRQ level being
	224	* serviced globally so that there are no double interrupts received.
	225	*
	226	* XXX See sparc64 irq.c.
	227	*/
	228	void smp4m_irq_rotate(int cpu)
	229	{
a54123e2 BB	230	int next = cpu_data(cpu).next;
	231	if (next != cpu)
	232	set_irq_udt(next);
1da177e4 LT	233	}
	234
	235	/* Cross calls, in order to work efficiently and atomically do all
	236	* the message passing work themselves, only stopcpu and reschedule
	237	* messages come through here.
	238	*/
	239	void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
	240	{
	241	static unsigned long smp_cpu_in_msg[NR_CPUS];
	242	cpumask_t mask;
	243	int me = smp_processor_id();
	244	int irq, i;
	245
	246	if(msg == MSG_RESCHEDULE) {
	247	irq = IRQ_RESCHEDULE;
	248
	249	if(smp_cpu_in_msg[me])
	250	return;
	251	} else if(msg == MSG_STOP_CPU) {
	252	irq = IRQ_STOP_CPU;
	253	} else {
	254	goto barf;
	255	}
	256
	257	smp_cpu_in_msg[me]++;
	258	if(target == MSG_ALL_BUT_SELF \|\| target == MSG_ALL) {
a54123e2	259	mask = cpu_online_map;
1da177e4 LT	260	if(target == MSG_ALL_BUT_SELF)
	261	cpu_clear(me, mask);
	262	for(i = 0; i < 4; i++) {
	263	if (cpu_isset(i, mask))
	264	set_cpu_int(i, irq);
	265	}
	266	} else {
	267	set_cpu_int(target, irq);
	268	}
	269	smp_cpu_in_msg[me]--;
	270
	271	return;
	272	barf:
	273	printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
	274	panic("Bogon SMP message pass.");
	275	}
	276
	277	static struct smp_funcall {
	278	smpfunc_t func;
	279	unsigned long arg1;
	280	unsigned long arg2;
	281	unsigned long arg3;
	282	unsigned long arg4;
	283	unsigned long arg5;
a54123e2 BB	284	unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
a54123e2 BB	285	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
1da177e4 LT	286	} ccall_info;
	287
	288	static DEFINE_SPINLOCK(cross_call_lock);
	289
	290	/* Cross calls must be serialized, at least currently. */
	291	void smp4m_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
	292	unsigned long arg3, unsigned long arg4, unsigned long arg5)
	293	{
a54123e2	294	register int ncpus = SUN4M_NCPUS;
1da177e4 LT	295	unsigned long flags;
	296
	297	spin_lock_irqsave(&cross_call_lock, flags);
	298
	299	/* Init function glue. */
	300	ccall_info.func = func;
	301	ccall_info.arg1 = arg1;
	302	ccall_info.arg2 = arg2;
	303	ccall_info.arg3 = arg3;
	304	ccall_info.arg4 = arg4;
	305	ccall_info.arg5 = arg5;
	306
	307	/* Init receive/complete mapping, plus fire the IPI's off. */
	308	{
a54123e2	309	cpumask_t mask = cpu_online_map;
1da177e4 LT	310	register int i;
	311
	312	cpu_clear(smp_processor_id(), mask);
	313	for(i = 0; i < ncpus; i++) {
	314	if (cpu_isset(i, mask)) {
	315	ccall_info.processors_in[i] = 0;
	316	ccall_info.processors_out[i] = 0;
	317	set_cpu_int(i, IRQ_CROSS_CALL);
	318	} else {
	319	ccall_info.processors_in[i] = 1;
	320	ccall_info.processors_out[i] = 1;
	321	}
	322	}
	323	}
	324
	325	{
	326	register int i;
	327
	328	i = 0;
	329	do {
	330	while(!ccall_info.processors_in[i])
	331	barrier();
	332	} while(++i < ncpus);
	333
	334	i = 0;
	335	do {
	336	while(!ccall_info.processors_out[i])
	337	barrier();
	338	} while(++i < ncpus);
	339	}
	340
	341	spin_unlock_irqrestore(&cross_call_lock, flags);
1da177e4 LT	342	}
	343
	344	/* Running cross calls. */
	345	void smp4m_cross_call_irq(void)
	346	{
	347	int i = smp_processor_id();
	348
	349	ccall_info.processors_in[i] = 1;
	350	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	351	ccall_info.arg4, ccall_info.arg5);
	352	ccall_info.processors_out[i] = 1;
	353	}
	354
	355	void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
	356	{
0d84438d	357	struct pt_regs *old_regs;
1da177e4 LT	358	int cpu = smp_processor_id();
1da177e4 LT	359
0d84438d AV	360	old_regs = set_irq_regs(regs);
0d84438d AV	361
1da177e4 LT	362	clear_profile_irq(cpu);
1da177e4 LT	363
0d84438d	364	profile_tick(CPU_PROFILING);
1da177e4 LT	365
	366	if(!--prof_counter(cpu)) {
	367	int user = user_mode(regs);
	368
	369	irq_enter();
	370	update_process_times(user);
	371	irq_exit();
	372
	373	prof_counter(cpu) = prof_multiplier(cpu);
	374	}
0d84438d	375	set_irq_regs(old_regs);
1da177e4 LT	376	}
	377
	378	extern unsigned int lvl14_resolution;
	379
	380	static void __init smp_setup_percpu_timer(void)
	381	{
	382	int cpu = smp_processor_id();
	383
	384	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	385	load_profile_irq(cpu, lvl14_resolution);
	386
	387	if(cpu == boot_cpu_id)
	388	enable_pil_irq(14);
	389	}
	390
	391	void __init smp4m_blackbox_id(unsigned *addr)
	392	{
	393	int rd = *addr & 0x3e000000;
	394	int rs1 = rd >> 11;
	395
	396	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	397	addr[1] = 0x8130200c \| rd \| rs1; /* srl reg, 0xc, reg */
	398	addr[2] = 0x80082003 \| rd \| rs1; /* and reg, 3, reg */
	399	}
	400
	401	void __init smp4m_blackbox_current(unsigned *addr)
	402	{
	403	int rd = *addr & 0x3e000000;
	404	int rs1 = rd >> 11;
	405
	406	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	407	addr[2] = 0x8130200a \| rd \| rs1; /* srl reg, 0xa, reg */
	408	addr[4] = 0x8008200c \| rd \| rs1; /* and reg, 3, reg */
	409	}
	410
	411	void __init sun4m_init_smp(void)
	412	{
	413	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	414	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	415	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
	416	BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
	417	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
	418	}