[deliverable/linux.git] / arch / sparc / kernel / sun4m_smp.c

/* sun4m_smp.c: Sparc SUN4M SMP support.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <asm/head.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/profile.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>

#include <asm/ptrace.h>
#include <asm/atomic.h>

#include <asm/delay.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/cpudata.h>

#define IRQ_RESCHEDULE		13
#define IRQ_STOP_CPU		14
#define IRQ_CROSS_CALL		15

extern ctxd_t *srmmu_ctx_table_phys;

extern void calibrate_delay(void);

extern volatile int smp_processors_ready;
extern volatile unsigned long cpu_callin_map[NR_CPUS];
extern unsigned char boot_cpu_id;

extern cpumask_t smp_commenced_mask;

extern int __smp4m_processor_id(void);

/*#define SMP_DEBUG*/

#ifdef SMP_DEBUG
#define SMP_PRINTK(x)	printk x
#else
#define SMP_PRINTK(x)
#endif

static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp_setup_percpu_timer(void);
extern void cpu_probe(void);

void __init smp4m_callin(void)
{
	int cpuid = hard_smp_processor_id();

	local_flush_cache_all();
	local_flush_tlb_all();

	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);

	local_flush_cache_all();
	local_flush_tlb_all();

	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Allow master to continue. */
	swap(&cpu_callin_map[cpuid], 1);

	/* XXX: What's up with all the flushes? */
	local_flush_cache_all();
	local_flush_tlb_all();
	
	cpu_probe();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	while (!cpu_isset(cpuid, smp_commenced_mask))
		mb();

	local_irq_enable();

	cpu_set(cpuid, cpu_online_map);
	/* last one in gets all the interrupts (for testing) */
	set_irq_udt(boot_cpu_id);
}

extern void init_IRQ(void);
extern void cpu_panic(void);

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
 
extern struct linux_prom_registers smp_penguin_ctable;
extern unsigned long trapbase_cpu1[];
extern unsigned long trapbase_cpu2[];
extern unsigned long trapbase_cpu3[];

void __init smp4m_boot_cpus(void)
{
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int smp4m_boot_one_cpu(int i)
{
	extern unsigned long sun4m_cpu_startup;
	unsigned long *entry = &sun4m_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_mid(i, &cpu_node);

	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);
	/* See trampoline.S for details... */
	entry += ((i-1) * 3);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk("Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	/* wheee... it's going... */
	for(timeout = 0; timeout < 10000; timeout++) {
		if(cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk("Processor %d is stuck.\n", i);
		return -ENODEV;
	}

	local_flush_cache_all();
	return 0;
}

void __init smp4m_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for (i = 0; i < NR_CPUS; i++) {
		if (cpu_online(i)) {
			*prev = i;
			prev = &cpu_data(i).next;
		}
	}
	*prev = first;
	local_flush_cache_all();

	/* Free unneeded trap tables */
	if (!cpu_isset(1, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu1));
		init_page_count(virt_to_page(trapbase_cpu1));
		free_page((unsigned long)trapbase_cpu1);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(2, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu2));
		init_page_count(virt_to_page(trapbase_cpu2));
		free_page((unsigned long)trapbase_cpu2);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(3, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu3));
		init_page_count(virt_to_page(trapbase_cpu3));
		free_page((unsigned long)trapbase_cpu3);
		totalram_pages++;
		num_physpages++;
	}

	/* Ok, they are spinning and ready to go. */
	smp_processors_ready = 1;
}

/* At each hardware IRQ, we get this called to forward IRQ reception
 * to the next processor.  The caller must disable the IRQ level being
 * serviced globally so that there are no double interrupts received.
 *
 * XXX See sparc64 irq.c.
 */
void smp4m_irq_rotate(int cpu)
{
	int next = cpu_data(cpu).next;
	if (next != cpu)
		set_irq_udt(next);
}

/* Cross calls, in order to work efficiently and atomically do all
 * the message passing work themselves, only stopcpu and reschedule
 * messages come through here.
 */
void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
{
	static unsigned long smp_cpu_in_msg[NR_CPUS];
	cpumask_t mask;
	int me = smp_processor_id();
	int irq, i;

	if(msg == MSG_RESCHEDULE) {
		irq = IRQ_RESCHEDULE;

		if(smp_cpu_in_msg[me])
			return;
	} else if(msg == MSG_STOP_CPU) {
		irq = IRQ_STOP_CPU;
	} else {
		goto barf;
	}

	smp_cpu_in_msg[me]++;
	if(target == MSG_ALL_BUT_SELF || target == MSG_ALL) {
		mask = cpu_online_map;
		if(target == MSG_ALL_BUT_SELF)
			cpu_clear(me, mask);
		for(i = 0; i < 4; i++) {
			if (cpu_isset(i, mask))
				set_cpu_int(i, irq);
		}
	} else {
		set_cpu_int(target, irq);
	}
	smp_cpu_in_msg[me]--;

	return;
barf:
	printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
	panic("Bogon SMP message pass.");
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned long processors_in[SUN4M_NCPUS];  /* Set when ipi entered. */
	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
} ccall_info;

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
void smp4m_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
		    unsigned long arg3, unsigned long arg4, unsigned long arg5)
{
		register int ncpus = SUN4M_NCPUS;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		/* Init function glue. */
		ccall_info.func = func;
		ccall_info.arg1 = arg1;
		ccall_info.arg2 = arg2;
		ccall_info.arg3 = arg3;
		ccall_info.arg4 = arg4;
		ccall_info.arg5 = arg5;

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			cpumask_t mask = cpu_online_map;
			register int i;

			cpu_clear(smp_processor_id(), mask);
			for(i = 0; i < ncpus; i++) {
				if (cpu_isset(i, mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					set_cpu_int(i, IRQ_CROSS_CALL);
				} else {
					ccall_info.processors_in[i] = 1;
					ccall_info.processors_out[i] = 1;
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				while(!ccall_info.processors_in[i])
					barrier();
			} while(++i < ncpus);

			i = 0;
			do {
				while(!ccall_info.processors_out[i])
					barrier();
			} while(++i < ncpus);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
}

/* Running cross calls. */
void smp4m_cross_call_irq(void)
{
	int i = smp_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
{
	int cpu = smp_processor_id();

	clear_profile_irq(cpu);

	profile_tick(CPU_PROFILING, regs);

	if(!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
}

extern unsigned int lvl14_resolution;

static void __init smp_setup_percpu_timer(void)
{
	int cpu = smp_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);

	if(cpu == boot_cpu_id)
		enable_pil_irq(14);
}

void __init smp4m_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[1] = 0x8130200c | rd | rs1;    	/* srl reg, 0xc, reg */
	addr[2] = 0x80082003 | rd | rs1;	/* and reg, 3, reg */
}

void __init smp4m_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[2] = 0x8130200a | rd | rs1;    	/* srl reg, 0xa, reg */
	addr[4] = 0x8008200c | rd | rs1;	/* and reg, 3, reg */
}

void __init sun4m_init_smp(void)
{
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
}
Commit	Line	Data
1da177e4 LT	1	/* sun4m_smp.c: Sparc SUN4M SMP support.
	2	*
	3	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	4	*/
	5
	6	#include <asm/head.h>
	7
	8	#include <linux/kernel.h>
	9	#include <linux/sched.h>
	10	#include <linux/threads.h>
	11	#include <linux/smp.h>
	12	#include <linux/smp_lock.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel_stat.h>
	15	#include <linux/init.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/mm.h>
	18	#include <linux/swap.h>
	19	#include <linux/profile.h>
	20	#include <asm/cacheflush.h>
	21	#include <asm/tlbflush.h>
	22
	23	#include <asm/ptrace.h>
	24	#include <asm/atomic.h>
	25
	26	#include <asm/delay.h>
	27	#include <asm/irq.h>
	28	#include <asm/page.h>
	29	#include <asm/pgalloc.h>
	30	#include <asm/pgtable.h>
	31	#include <asm/oplib.h>
	32	#include <asm/cpudata.h>
	33
	34	#define IRQ_RESCHEDULE 13
	35	#define IRQ_STOP_CPU 14
	36	#define IRQ_CROSS_CALL 15
	37
	38	extern ctxd_t *srmmu_ctx_table_phys;
	39
	40	extern void calibrate_delay(void);
	41
	42	extern volatile int smp_processors_ready;
1da177e4 LT	43	extern volatile unsigned long cpu_callin_map[NR_CPUS];
1da177e4 LT	44	extern unsigned char boot_cpu_id;
a54123e2 BB	45
	46	extern cpumask_t smp_commenced_mask;
	47
1da177e4 LT	48	extern int __smp4m_processor_id(void);
	49
	50	/#define SMP_DEBUG/
	51
	52	#ifdef SMP_DEBUG
	53	#define SMP_PRINTK(x) printk x
	54	#else
	55	#define SMP_PRINTK(x)
	56	#endif
	57
	58	static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
	59	{
	60	__asm__ __volatile__("swap [%1], %0\n\t" :
	61	"=&r" (val), "=&r" (ptr) :
	62	"0" (val), "1" (ptr));
	63	return val;
	64	}
	65
	66	static void smp_setup_percpu_timer(void);
	67	extern void cpu_probe(void);
	68
	69	void __init smp4m_callin(void)
	70	{
	71	int cpuid = hard_smp_processor_id();
	72
	73	local_flush_cache_all();
	74	local_flush_tlb_all();
	75
1da177e4 LT	76	/* Get our local ticker going. */
	77	smp_setup_percpu_timer();
	78
	79	calibrate_delay();
	80	smp_store_cpu_info(cpuid);
	81
	82	local_flush_cache_all();
	83	local_flush_tlb_all();
	84
	85	/*
	86	* Unblock the master CPU _only_ when the scheduler state
	87	* of all secondary CPUs will be up-to-date, so after
	88	* the SMP initialization the master will be just allowed
	89	* to call the scheduler code.
	90	*/
	91	/* Allow master to continue. */
a54123e2	92	swap(&cpu_callin_map[cpuid], 1);
1da177e4	93
a54123e2	94	/* XXX: What's up with all the flushes? */
1da177e4 LT	95	local_flush_cache_all();
	96	local_flush_tlb_all();
	97
	98	cpu_probe();
	99
	100	/* Fix idle thread fields. */
	101	__asm__ __volatile__("ld [%0], %%g6\n\t"
	102	: : "r" (&current_set[cpuid])
	103	: "memory" /* paranoid */);
	104
	105	/* Attach to the address space of init_task. */
	106	atomic_inc(&init_mm.mm_count);
	107	current->active_mm = &init_mm;
	108
a54123e2 BB	109	while (!cpu_isset(cpuid, smp_commenced_mask))
a54123e2 BB	110	mb();
1da177e4 LT	111
1da177e4 LT	112	local_irq_enable();
a54123e2 BB	113
	114	cpu_set(cpuid, cpu_online_map);
	115	/* last one in gets all the interrupts (for testing) */
	116	set_irq_udt(boot_cpu_id);
1da177e4 LT	117	}
	118
	119	extern void init_IRQ(void);
	120	extern void cpu_panic(void);
	121
	122	/*
	123	* Cycle through the processors asking the PROM to start each one.
	124	*/
	125
	126	extern struct linux_prom_registers smp_penguin_ctable;
	127	extern unsigned long trapbase_cpu1[];
	128	extern unsigned long trapbase_cpu2[];
	129	extern unsigned long trapbase_cpu3[];
	130
	131	void __init smp4m_boot_cpus(void)
	132	{
a54123e2 BB	133	smp_setup_percpu_timer();
	134	local_flush_cache_all();
	135	}
1da177e4	136
a54123e2 BB	137	int smp4m_boot_one_cpu(int i)
	138	{
	139	extern unsigned long sun4m_cpu_startup;
	140	unsigned long *entry = &sun4m_cpu_startup;
	141	struct task_struct *p;
	142	int timeout;
	143	int cpu_node;
1da177e4	144
a54123e2 BB	145	cpu_find_by_mid(i, &cpu_node);
	146
	147	/* Cook up an idler for this guy. */
	148	p = fork_idle(i);
	149	current_set[i] = task_thread_info(p);
	150	/* See trampoline.S for details... */
	151	entry += ((i-1) * 3);
1da177e4	152
a54123e2 BB	153	/*
	154	* Initialize the contexts table
	155	* Since the call to prom_startcpu() trashes the structure,
	156	* we need to re-initialize it for each cpu
	157	*/
	158	smp_penguin_ctable.which_io = 0;
	159	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	160	smp_penguin_ctable.reg_size = 0;
1da177e4	161
a54123e2 BB	162	/* whirrr, whirrr, whirrrrrrrrr... */
	163	printk("Starting CPU %d at %p\n", i, entry);
	164	local_flush_cache_all();
	165	prom_startcpu(cpu_node,
	166	&smp_penguin_ctable, 0, (char *)entry);
	167
	168	/* wheee... it's going... */
	169	for(timeout = 0; timeout < 10000; timeout++) {
	170	if(cpu_callin_map[i])
	171	break;
	172	udelay(200);
1da177e4 LT	173	}
1da177e4 LT	174
a54123e2 BB	175	if (!(cpu_callin_map[i])) {
	176	printk("Processor %d is stuck.\n", i);
	177	return -ENODEV;
	178	}
1da177e4	179
1da177e4	180	local_flush_cache_all();
a54123e2 BB	181	return 0;
	182	}
	183
	184	void __init smp4m_smp_done(void)
	185	{
	186	int i, first;
	187	int *prev;
	188
	189	/* setup cpu list for irq rotation */
	190	first = 0;
	191	prev = &first;
	192	for (i = 0; i < NR_CPUS; i++) {
	193	if (cpu_online(i)) {
	194	*prev = i;
	195	prev = &cpu_data(i).next;
1da177e4 LT	196	}
1da177e4 LT	197	}
a54123e2	198	*prev = first;
1da177e4	199	local_flush_cache_all();
1da177e4 LT	200
1da177e4 LT	201	/* Free unneeded trap tables */
a54123e2	202	if (!cpu_isset(1, cpu_present_map)) {
1da177e4	203	ClearPageReserved(virt_to_page(trapbase_cpu1));
7835e98b	204	init_page_count(virt_to_page(trapbase_cpu1));
1da177e4 LT	205	free_page((unsigned long)trapbase_cpu1);
	206	totalram_pages++;
	207	num_physpages++;
	208	}
	209	if (!cpu_isset(2, cpu_present_map)) {
	210	ClearPageReserved(virt_to_page(trapbase_cpu2));
7835e98b	211	init_page_count(virt_to_page(trapbase_cpu2));
1da177e4 LT	212	free_page((unsigned long)trapbase_cpu2);
	213	totalram_pages++;
	214	num_physpages++;
	215	}
	216	if (!cpu_isset(3, cpu_present_map)) {
	217	ClearPageReserved(virt_to_page(trapbase_cpu3));
7835e98b	218	init_page_count(virt_to_page(trapbase_cpu3));
1da177e4 LT	219	free_page((unsigned long)trapbase_cpu3);
	220	totalram_pages++;
	221	num_physpages++;
	222	}
	223
	224	/* Ok, they are spinning and ready to go. */
	225	smp_processors_ready = 1;
	226	}
	227
	228	/* At each hardware IRQ, we get this called to forward IRQ reception
	229	* to the next processor. The caller must disable the IRQ level being
	230	* serviced globally so that there are no double interrupts received.
	231	*
	232	* XXX See sparc64 irq.c.
	233	*/
	234	void smp4m_irq_rotate(int cpu)
	235	{
a54123e2 BB	236	int next = cpu_data(cpu).next;
	237	if (next != cpu)
	238	set_irq_udt(next);
1da177e4 LT	239	}
	240
	241	/* Cross calls, in order to work efficiently and atomically do all
	242	* the message passing work themselves, only stopcpu and reschedule
	243	* messages come through here.
	244	*/
	245	void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
	246	{
	247	static unsigned long smp_cpu_in_msg[NR_CPUS];
	248	cpumask_t mask;
	249	int me = smp_processor_id();
	250	int irq, i;
	251
	252	if(msg == MSG_RESCHEDULE) {
	253	irq = IRQ_RESCHEDULE;
	254
	255	if(smp_cpu_in_msg[me])
	256	return;
	257	} else if(msg == MSG_STOP_CPU) {
	258	irq = IRQ_STOP_CPU;
	259	} else {
	260	goto barf;
	261	}
	262
	263	smp_cpu_in_msg[me]++;
	264	if(target == MSG_ALL_BUT_SELF \|\| target == MSG_ALL) {
a54123e2	265	mask = cpu_online_map;
1da177e4 LT	266	if(target == MSG_ALL_BUT_SELF)
	267	cpu_clear(me, mask);
	268	for(i = 0; i < 4; i++) {
	269	if (cpu_isset(i, mask))
	270	set_cpu_int(i, irq);
	271	}
	272	} else {
	273	set_cpu_int(target, irq);
	274	}
	275	smp_cpu_in_msg[me]--;
	276
	277	return;
	278	barf:
	279	printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
	280	panic("Bogon SMP message pass.");
	281	}
	282
	283	static struct smp_funcall {
	284	smpfunc_t func;
	285	unsigned long arg1;
	286	unsigned long arg2;
	287	unsigned long arg3;
	288	unsigned long arg4;
	289	unsigned long arg5;
a54123e2 BB	290	unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
a54123e2 BB	291	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
1da177e4 LT	292	} ccall_info;
	293
	294	static DEFINE_SPINLOCK(cross_call_lock);
	295
	296	/* Cross calls must be serialized, at least currently. */
	297	void smp4m_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
	298	unsigned long arg3, unsigned long arg4, unsigned long arg5)
	299	{
a54123e2	300	register int ncpus = SUN4M_NCPUS;
1da177e4 LT	301	unsigned long flags;
	302
	303	spin_lock_irqsave(&cross_call_lock, flags);
	304
	305	/* Init function glue. */
	306	ccall_info.func = func;
	307	ccall_info.arg1 = arg1;
	308	ccall_info.arg2 = arg2;
	309	ccall_info.arg3 = arg3;
	310	ccall_info.arg4 = arg4;
	311	ccall_info.arg5 = arg5;
	312
	313	/* Init receive/complete mapping, plus fire the IPI's off. */
	314	{
a54123e2	315	cpumask_t mask = cpu_online_map;
1da177e4 LT	316	register int i;
	317
	318	cpu_clear(smp_processor_id(), mask);
	319	for(i = 0; i < ncpus; i++) {
	320	if (cpu_isset(i, mask)) {
	321	ccall_info.processors_in[i] = 0;
	322	ccall_info.processors_out[i] = 0;
	323	set_cpu_int(i, IRQ_CROSS_CALL);
	324	} else {
	325	ccall_info.processors_in[i] = 1;
	326	ccall_info.processors_out[i] = 1;
	327	}
	328	}
	329	}
	330
	331	{
	332	register int i;
	333
	334	i = 0;
	335	do {
	336	while(!ccall_info.processors_in[i])
	337	barrier();
	338	} while(++i < ncpus);
	339
	340	i = 0;
	341	do {
	342	while(!ccall_info.processors_out[i])
	343	barrier();
	344	} while(++i < ncpus);
	345	}
	346
	347	spin_unlock_irqrestore(&cross_call_lock, flags);
1da177e4 LT	348	}
	349
	350	/* Running cross calls. */
	351	void smp4m_cross_call_irq(void)
	352	{
	353	int i = smp_processor_id();
	354
	355	ccall_info.processors_in[i] = 1;
	356	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	357	ccall_info.arg4, ccall_info.arg5);
	358	ccall_info.processors_out[i] = 1;
	359	}
	360
	361	void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
	362	{
	363	int cpu = smp_processor_id();
	364
	365	clear_profile_irq(cpu);
	366
	367	profile_tick(CPU_PROFILING, regs);
	368
	369	if(!--prof_counter(cpu)) {
	370	int user = user_mode(regs);
	371
	372	irq_enter();
	373	update_process_times(user);
	374	irq_exit();
	375
	376	prof_counter(cpu) = prof_multiplier(cpu);
	377	}
	378	}
	379
	380	extern unsigned int lvl14_resolution;
	381
	382	static void __init smp_setup_percpu_timer(void)
	383	{
	384	int cpu = smp_processor_id();
	385
	386	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	387	load_profile_irq(cpu, lvl14_resolution);
	388
	389	if(cpu == boot_cpu_id)
	390	enable_pil_irq(14);
	391	}
	392
	393	void __init smp4m_blackbox_id(unsigned *addr)
	394	{
	395	int rd = *addr & 0x3e000000;
	396	int rs1 = rd >> 11;
	397
	398	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	399	addr[1] = 0x8130200c \| rd \| rs1; /* srl reg, 0xc, reg */
	400	addr[2] = 0x80082003 \| rd \| rs1; /* and reg, 3, reg */
	401	}
	402
	403	void __init smp4m_blackbox_current(unsigned *addr)
	404	{
	405	int rd = *addr & 0x3e000000;
	406	int rs1 = rd >> 11;
	407
	408	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	409	addr[2] = 0x8130200a \| rd \| rs1; /* srl reg, 0xa, reg */
	410	addr[4] = 0x8008200c \| rd \| rs1; /* and reg, 3, reg */
	411	}
412
413	void __init sun4m_init_smp(void)
414	{
415	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
416	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
417	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
418	BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
419	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
420	}