Commit | Line | Data |
---|---|---|
aba20a82 SR |
1 | /* |
2 | * sun4m SMP support. | |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | */ | |
6 | ||
1da177e4 | 7 | #include <linux/interrupt.h> |
1da177e4 | 8 | #include <linux/profile.h> |
6c81c32f | 9 | #include <linux/delay.h> |
4245e59d | 10 | #include <linux/cpu.h> |
6c81c32f | 11 | |
1da177e4 LT |
12 | #include <asm/cacheflush.h> |
13 | #include <asm/tlbflush.h> | |
1da177e4 | 14 | |
32231a66 | 15 | #include "irq.h" |
aba20a82 | 16 | #include "kernel.h" |
32231a66 | 17 | |
ecbc42b7 DH |
18 | #define IRQ_IPI_SINGLE 12 |
19 | #define IRQ_IPI_MASK 13 | |
20 | #define IRQ_IPI_RESCHED 14 | |
1da177e4 LT |
21 | #define IRQ_CROSS_CALL 15 |
22 | ||
1a8a27c9 WF |
23 | static inline unsigned long |
24 | swap_ulong(volatile unsigned long *ptr, unsigned long val) | |
1da177e4 LT |
25 | { |
26 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
27 | "=&r" (val), "=&r" (ptr) : | |
28 | "0" (val), "1" (ptr)); | |
29 | return val; | |
30 | } | |
31 | ||
ecbc42b7 | 32 | static void smp4m_ipi_init(void); |
1da177e4 | 33 | static void smp_setup_percpu_timer(void); |
1da177e4 | 34 | |
92d452f0 | 35 | void __cpuinit smp4m_callin(void) |
1da177e4 LT |
36 | { |
37 | int cpuid = hard_smp_processor_id(); | |
38 | ||
39 | local_flush_cache_all(); | |
40 | local_flush_tlb_all(); | |
41 | ||
e545a614 MS |
42 | notify_cpu_starting(cpuid); |
43 | ||
1da177e4 LT |
44 | /* Get our local ticker going. */ |
45 | smp_setup_percpu_timer(); | |
46 | ||
47 | calibrate_delay(); | |
48 | smp_store_cpu_info(cpuid); | |
49 | ||
50 | local_flush_cache_all(); | |
51 | local_flush_tlb_all(); | |
52 | ||
53 | /* | |
54 | * Unblock the master CPU _only_ when the scheduler state | |
55 | * of all secondary CPUs will be up-to-date, so after | |
56 | * the SMP initialization the master will be just allowed | |
57 | * to call the scheduler code. | |
58 | */ | |
59 | /* Allow master to continue. */ | |
1a8a27c9 | 60 | swap_ulong(&cpu_callin_map[cpuid], 1); |
1da177e4 | 61 | |
a54123e2 | 62 | /* XXX: What's up with all the flushes? */ |
1da177e4 LT |
63 | local_flush_cache_all(); |
64 | local_flush_tlb_all(); | |
aba20a82 | 65 | |
1da177e4 LT |
66 | /* Fix idle thread fields. */ |
67 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
68 | : : "r" (¤t_set[cpuid]) | |
69 | : "memory" /* paranoid */); | |
70 | ||
71 | /* Attach to the address space of init_task. */ | |
72 | atomic_inc(&init_mm.mm_count); | |
73 | current->active_mm = &init_mm; | |
74 | ||
fb1fece5 | 75 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
a54123e2 | 76 | mb(); |
1da177e4 LT |
77 | |
78 | local_irq_enable(); | |
a54123e2 | 79 | |
fe73971c | 80 | set_cpu_online(cpuid, true); |
1da177e4 LT |
81 | } |
82 | ||
1da177e4 LT |
83 | /* |
84 | * Cycle through the processors asking the PROM to start each one. | |
85 | */ | |
1da177e4 LT |
86 | void __init smp4m_boot_cpus(void) |
87 | { | |
ecbc42b7 | 88 | smp4m_ipi_init(); |
a54123e2 BB |
89 | smp_setup_percpu_timer(); |
90 | local_flush_cache_all(); | |
91 | } | |
1da177e4 | 92 | |
92d452f0 | 93 | int __cpuinit smp4m_boot_one_cpu(int i) |
a54123e2 | 94 | { |
a54123e2 BB |
95 | unsigned long *entry = &sun4m_cpu_startup; |
96 | struct task_struct *p; | |
97 | int timeout; | |
98 | int cpu_node; | |
1da177e4 | 99 | |
a54123e2 BB |
100 | cpu_find_by_mid(i, &cpu_node); |
101 | ||
102 | /* Cook up an idler for this guy. */ | |
103 | p = fork_idle(i); | |
104 | current_set[i] = task_thread_info(p); | |
105 | /* See trampoline.S for details... */ | |
aba20a82 | 106 | entry += ((i - 1) * 3); |
1da177e4 | 107 | |
a54123e2 BB |
108 | /* |
109 | * Initialize the contexts table | |
110 | * Since the call to prom_startcpu() trashes the structure, | |
111 | * we need to re-initialize it for each cpu | |
112 | */ | |
113 | smp_penguin_ctable.which_io = 0; | |
114 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
115 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 116 | |
a54123e2 | 117 | /* whirrr, whirrr, whirrrrrrrrr... */ |
aba20a82 | 118 | printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); |
a54123e2 | 119 | local_flush_cache_all(); |
aba20a82 | 120 | prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); |
a54123e2 BB |
121 | |
122 | /* wheee... it's going... */ | |
aba20a82 SR |
123 | for (timeout = 0; timeout < 10000; timeout++) { |
124 | if (cpu_callin_map[i]) | |
a54123e2 BB |
125 | break; |
126 | udelay(200); | |
1da177e4 LT |
127 | } |
128 | ||
a54123e2 | 129 | if (!(cpu_callin_map[i])) { |
aba20a82 | 130 | printk(KERN_ERR "Processor %d is stuck.\n", i); |
a54123e2 BB |
131 | return -ENODEV; |
132 | } | |
1da177e4 | 133 | |
1da177e4 | 134 | local_flush_cache_all(); |
a54123e2 BB |
135 | return 0; |
136 | } | |
137 | ||
138 | void __init smp4m_smp_done(void) | |
139 | { | |
140 | int i, first; | |
141 | int *prev; | |
142 | ||
143 | /* setup cpu list for irq rotation */ | |
144 | first = 0; | |
145 | prev = &first; | |
ec7c14bd RR |
146 | for_each_online_cpu(i) { |
147 | *prev = i; | |
148 | prev = &cpu_data(i).next; | |
1da177e4 | 149 | } |
a54123e2 | 150 | *prev = first; |
1da177e4 | 151 | local_flush_cache_all(); |
1da177e4 | 152 | |
1da177e4 | 153 | /* Ok, they are spinning and ready to go. */ |
1da177e4 LT |
154 | } |
155 | ||
ecbc42b7 DH |
156 | |
157 | /* Initialize IPIs on the SUN4M SMP machine */ | |
158 | static void __init smp4m_ipi_init(void) | |
159 | { | |
160 | } | |
161 | ||
162 | static void smp4m_ipi_resched(int cpu) | |
163 | { | |
164 | set_cpu_int(cpu, IRQ_IPI_RESCHED); | |
165 | } | |
166 | ||
167 | static void smp4m_ipi_single(int cpu) | |
168 | { | |
169 | set_cpu_int(cpu, IRQ_IPI_SINGLE); | |
170 | } | |
171 | ||
172 | static void smp4m_ipi_mask_one(int cpu) | |
173 | { | |
174 | set_cpu_int(cpu, IRQ_IPI_MASK); | |
175 | } | |
176 | ||
1da177e4 LT |
177 | static struct smp_funcall { |
178 | smpfunc_t func; | |
179 | unsigned long arg1; | |
180 | unsigned long arg2; | |
181 | unsigned long arg3; | |
182 | unsigned long arg4; | |
183 | unsigned long arg5; | |
a54123e2 BB |
184 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
185 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
186 | } ccall_info; |
187 | ||
188 | static DEFINE_SPINLOCK(cross_call_lock); | |
189 | ||
190 | /* Cross calls must be serialized, at least currently. */ | |
66e4f8c0 | 191 | static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 192 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 193 | unsigned long arg4) |
1da177e4 | 194 | { |
a54123e2 | 195 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
196 | unsigned long flags; |
197 | ||
198 | spin_lock_irqsave(&cross_call_lock, flags); | |
199 | ||
200 | /* Init function glue. */ | |
201 | ccall_info.func = func; | |
202 | ccall_info.arg1 = arg1; | |
203 | ccall_info.arg2 = arg2; | |
204 | ccall_info.arg3 = arg3; | |
205 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 206 | ccall_info.arg5 = 0; |
1da177e4 LT |
207 | |
208 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
209 | { | |
1da177e4 LT |
210 | register int i; |
211 | ||
fb1fece5 KM |
212 | cpumask_clear_cpu(smp_processor_id(), &mask); |
213 | cpumask_and(&mask, cpu_online_mask, &mask); | |
aba20a82 | 214 | for (i = 0; i < ncpus; i++) { |
fb1fece5 | 215 | if (cpumask_test_cpu(i, &mask)) { |
1da177e4 LT |
216 | ccall_info.processors_in[i] = 0; |
217 | ccall_info.processors_out[i] = 0; | |
218 | set_cpu_int(i, IRQ_CROSS_CALL); | |
219 | } else { | |
220 | ccall_info.processors_in[i] = 1; | |
221 | ccall_info.processors_out[i] = 1; | |
222 | } | |
223 | } | |
224 | } | |
225 | ||
226 | { | |
227 | register int i; | |
228 | ||
229 | i = 0; | |
230 | do { | |
fb1fece5 | 231 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 232 | continue; |
aba20a82 | 233 | while (!ccall_info.processors_in[i]) |
1da177e4 | 234 | barrier(); |
aba20a82 | 235 | } while (++i < ncpus); |
1da177e4 LT |
236 | |
237 | i = 0; | |
238 | do { | |
fb1fece5 | 239 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 240 | continue; |
aba20a82 | 241 | while (!ccall_info.processors_out[i]) |
1da177e4 | 242 | barrier(); |
aba20a82 | 243 | } while (++i < ncpus); |
1da177e4 | 244 | } |
1da177e4 | 245 | spin_unlock_irqrestore(&cross_call_lock, flags); |
1da177e4 LT |
246 | } |
247 | ||
248 | /* Running cross calls. */ | |
249 | void smp4m_cross_call_irq(void) | |
250 | { | |
251 | int i = smp_processor_id(); | |
252 | ||
253 | ccall_info.processors_in[i] = 1; | |
254 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
255 | ccall_info.arg4, ccall_info.arg5); | |
256 | ccall_info.processors_out[i] = 1; | |
257 | } | |
258 | ||
259 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) | |
260 | { | |
0d84438d | 261 | struct pt_regs *old_regs; |
1da177e4 LT |
262 | int cpu = smp_processor_id(); |
263 | ||
0d84438d AV |
264 | old_regs = set_irq_regs(regs); |
265 | ||
1de937a5 | 266 | sun4m_clear_profile_irq(cpu); |
1da177e4 | 267 | |
0d84438d | 268 | profile_tick(CPU_PROFILING); |
1da177e4 | 269 | |
aba20a82 | 270 | if (!--prof_counter(cpu)) { |
1da177e4 LT |
271 | int user = user_mode(regs); |
272 | ||
273 | irq_enter(); | |
274 | update_process_times(user); | |
275 | irq_exit(); | |
276 | ||
277 | prof_counter(cpu) = prof_multiplier(cpu); | |
278 | } | |
0d84438d | 279 | set_irq_regs(old_regs); |
1da177e4 LT |
280 | } |
281 | ||
409832f5 | 282 | static void __cpuinit smp_setup_percpu_timer(void) |
1da177e4 LT |
283 | { |
284 | int cpu = smp_processor_id(); | |
285 | ||
286 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
287 | load_profile_irq(cpu, lvl14_resolution); | |
288 | ||
aba20a82 | 289 | if (cpu == boot_cpu_id) |
6baa9b20 | 290 | sun4m_unmask_profile_irq(); |
1da177e4 LT |
291 | } |
292 | ||
c61c65cd | 293 | static void __init smp4m_blackbox_id(unsigned *addr) |
1da177e4 LT |
294 | { |
295 | int rd = *addr & 0x3e000000; | |
296 | int rs1 = rd >> 11; | |
aba20a82 | 297 | |
1da177e4 | 298 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ |
aba20a82 | 299 | addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ |
1da177e4 LT |
300 | addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */ |
301 | } | |
302 | ||
c61c65cd | 303 | static void __init smp4m_blackbox_current(unsigned *addr) |
1da177e4 LT |
304 | { |
305 | int rd = *addr & 0x3e000000; | |
306 | int rs1 = rd >> 11; | |
aba20a82 | 307 | |
1da177e4 | 308 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ |
aba20a82 | 309 | addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ |
4cad6917 | 310 | addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */ |
1da177e4 LT |
311 | } |
312 | ||
313 | void __init sun4m_init_smp(void) | |
314 | { | |
315 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id); | |
316 | BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current); | |
317 | BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM); | |
1da177e4 | 318 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM); |
ecbc42b7 DH |
319 | BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM); |
320 | BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM); | |
321 | BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM); | |
1da177e4 | 322 | } |