[deliverable/linux.git] / arch / sparc / kernel / sun4m_smp.c

/* sun4m_smp.c: Sparc SUN4M SMP support.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <asm/head.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/profile.h>
#include <linux/delay.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/irq_regs.h>

#include <asm/ptrace.h>
#include <asm/atomic.h>

#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/cpudata.h>

#include "irq.h"

#define IRQ_CROSS_CALL		15

extern ctxd_t *srmmu_ctx_table_phys;

extern volatile unsigned long cpu_callin_map[NR_CPUS];
extern unsigned char boot_cpu_id;

extern cpumask_t smp_commenced_mask;

extern int __smp4m_processor_id(void);

/*#define SMP_DEBUG*/

#ifdef SMP_DEBUG
#define SMP_PRINTK(x)	printk x
#else
#define SMP_PRINTK(x)
#endif

static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp_setup_percpu_timer(void);
extern void cpu_probe(void);

void __cpuinit smp4m_callin(void)
{
	int cpuid = hard_smp_processor_id();

	local_flush_cache_all();
	local_flush_tlb_all();

	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);

	local_flush_cache_all();
	local_flush_tlb_all();

	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Allow master to continue. */
	swap(&cpu_callin_map[cpuid], 1);

	/* XXX: What's up with all the flushes? */
	local_flush_cache_all();
	local_flush_tlb_all();
	
	cpu_probe();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	while (!cpu_isset(cpuid, smp_commenced_mask))
		mb();

	local_irq_enable();

	cpu_set(cpuid, cpu_online_map);
}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
 
extern struct linux_prom_registers smp_penguin_ctable;
extern unsigned long trapbase_cpu1[];
extern unsigned long trapbase_cpu2[];
extern unsigned long trapbase_cpu3[];

void __init smp4m_boot_cpus(void)
{
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int __cpuinit smp4m_boot_one_cpu(int i)
{
	extern unsigned long sun4m_cpu_startup;
	unsigned long *entry = &sun4m_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_mid(i, &cpu_node);

	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);
	/* See trampoline.S for details... */
	entry += ((i-1) * 3);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk("Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	/* wheee... it's going... */
	for(timeout = 0; timeout < 10000; timeout++) {
		if(cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk("Processor %d is stuck.\n", i);
		return -ENODEV;
	}

	local_flush_cache_all();
	return 0;
}

void __init smp4m_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for (i = 0; i < NR_CPUS; i++) {
		if (cpu_online(i)) {
			*prev = i;
			prev = &cpu_data(i).next;
		}
	}
	*prev = first;
	local_flush_cache_all();

	/* Free unneeded trap tables */
	if (!cpu_isset(1, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu1));
		init_page_count(virt_to_page(trapbase_cpu1));
		free_page((unsigned long)trapbase_cpu1);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(2, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu2));
		init_page_count(virt_to_page(trapbase_cpu2));
		free_page((unsigned long)trapbase_cpu2);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(3, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu3));
		init_page_count(virt_to_page(trapbase_cpu3));
		free_page((unsigned long)trapbase_cpu3);
		totalram_pages++;
		num_physpages++;
	}

	/* Ok, they are spinning and ready to go. */
}

/* At each hardware IRQ, we get this called to forward IRQ reception
 * to the next processor.  The caller must disable the IRQ level being
 * serviced globally so that there are no double interrupts received.
 *
 * XXX See sparc64 irq.c.
 */
void smp4m_irq_rotate(int cpu)
{
	int next = cpu_data(cpu).next;
	if (next != cpu)
		set_irq_udt(next);
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned long processors_in[SUN4M_NCPUS];  /* Set when ipi entered. */
	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
} ccall_info;

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
		register int ncpus = SUN4M_NCPUS;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		/* Init function glue. */
		ccall_info.func = func;
		ccall_info.arg1 = arg1;
		ccall_info.arg2 = arg2;
		ccall_info.arg3 = arg3;
		ccall_info.arg4 = arg4;
		ccall_info.arg5 = 0;

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpu_clear(smp_processor_id(), mask);
			cpus_and(mask, cpu_online_map, mask);
			for(i = 0; i < ncpus; i++) {
				if (cpu_isset(i, mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					set_cpu_int(i, IRQ_CROSS_CALL);
				} else {
					ccall_info.processors_in[i] = 1;
					ccall_info.processors_out[i] = 1;
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while(!ccall_info.processors_in[i])
					barrier();
			} while(++i < ncpus);

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while(!ccall_info.processors_out[i])
					barrier();
			} while(++i < ncpus);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
}

/* Running cross calls. */
void smp4m_cross_call_irq(void)
{
	int i = smp_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = smp_processor_id();

	old_regs = set_irq_regs(regs);

	clear_profile_irq(cpu);

	profile_tick(CPU_PROFILING);

	if(!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
	set_irq_regs(old_regs);
}

extern unsigned int lvl14_resolution;

static void __init smp_setup_percpu_timer(void)
{
	int cpu = smp_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);

	if(cpu == boot_cpu_id)
		enable_pil_irq(14);
}

static void __init smp4m_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[1] = 0x8130200c | rd | rs1;    	/* srl reg, 0xc, reg */
	addr[2] = 0x80082003 | rd | rs1;	/* and reg, 3, reg */
}

static void __init smp4m_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[2] = 0x8130200a | rd | rs1;    	/* srl reg, 0xa, reg */
	addr[4] = 0x8008200c | rd | rs1;	/* and reg, 0xc, reg */
}

void __init sun4m_init_smp(void)
{
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
}
Commit	Line	Data
1da177e4 LT	1	/* sun4m_smp.c: Sparc SUN4M SMP support.
	2	*
	3	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	4	*/
	5
	6	#include <asm/head.h>
	7
	8	#include <linux/kernel.h>
	9	#include <linux/sched.h>
	10	#include <linux/threads.h>
	11	#include <linux/smp.h>
1da177e4 LT	12	#include <linux/interrupt.h>
	13	#include <linux/kernel_stat.h>
	14	#include <linux/init.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/mm.h>
	17	#include <linux/swap.h>
	18	#include <linux/profile.h>
6c81c32f AB	19	#include <linux/delay.h>
6c81c32f AB	20
1da177e4 LT	21	#include <asm/cacheflush.h>
1da177e4 LT	22	#include <asm/tlbflush.h>
0d84438d	23	#include <asm/irq_regs.h>
1da177e4 LT	24
	25	#include <asm/ptrace.h>
	26	#include <asm/atomic.h>
	27
1da177e4 LT	28	#include <asm/irq.h>
	29	#include <asm/page.h>
	30	#include <asm/pgalloc.h>
	31	#include <asm/pgtable.h>
	32	#include <asm/oplib.h>
	33	#include <asm/cpudata.h>
	34
32231a66 AV	35	#include "irq.h"
32231a66 AV	36
1da177e4 LT	37	#define IRQ_CROSS_CALL 15
	38
	39	extern ctxd_t *srmmu_ctx_table_phys;
	40
1da177e4 LT	41	extern volatile unsigned long cpu_callin_map[NR_CPUS];
1da177e4 LT	42	extern unsigned char boot_cpu_id;
a54123e2 BB	43
	44	extern cpumask_t smp_commenced_mask;
	45
1da177e4 LT	46	extern int __smp4m_processor_id(void);
	47
	48	/#define SMP_DEBUG/
	49
	50	#ifdef SMP_DEBUG
	51	#define SMP_PRINTK(x) printk x
	52	#else
	53	#define SMP_PRINTK(x)
	54	#endif
	55
	56	static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
	57	{
	58	__asm__ __volatile__("swap [%1], %0\n\t" :
	59	"=&r" (val), "=&r" (ptr) :
	60	"0" (val), "1" (ptr));
	61	return val;
	62	}
	63
	64	static void smp_setup_percpu_timer(void);
	65	extern void cpu_probe(void);
	66
92d452f0	67	void __cpuinit smp4m_callin(void)
1da177e4 LT	68	{
	69	int cpuid = hard_smp_processor_id();
	70
	71	local_flush_cache_all();
	72	local_flush_tlb_all();
	73
1da177e4 LT	74	/* Get our local ticker going. */
	75	smp_setup_percpu_timer();
	76
	77	calibrate_delay();
	78	smp_store_cpu_info(cpuid);
	79
	80	local_flush_cache_all();
	81	local_flush_tlb_all();
	82
	83	/*
	84	* Unblock the master CPU _only_ when the scheduler state
	85	* of all secondary CPUs will be up-to-date, so after
	86	* the SMP initialization the master will be just allowed
	87	* to call the scheduler code.
	88	*/
	89	/* Allow master to continue. */
a54123e2	90	swap(&cpu_callin_map[cpuid], 1);
1da177e4	91
a54123e2	92	/* XXX: What's up with all the flushes? */
1da177e4 LT	93	local_flush_cache_all();
	94	local_flush_tlb_all();
	95
	96	cpu_probe();
	97
	98	/* Fix idle thread fields. */
	99	__asm__ __volatile__("ld [%0], %%g6\n\t"
	100	: : "r" (&current_set[cpuid])
	101	: "memory" /* paranoid */);
	102
	103	/* Attach to the address space of init_task. */
	104	atomic_inc(&init_mm.mm_count);
	105	current->active_mm = &init_mm;
	106
a54123e2 BB	107	while (!cpu_isset(cpuid, smp_commenced_mask))
a54123e2 BB	108	mb();
1da177e4 LT	109
1da177e4 LT	110	local_irq_enable();
a54123e2 BB	111
a54123e2 BB	112	cpu_set(cpuid, cpu_online_map);
1da177e4 LT	113	}
1da177e4 LT	114
1da177e4 LT	115	/*
	116	* Cycle through the processors asking the PROM to start each one.
	117	*/
	118
	119	extern struct linux_prom_registers smp_penguin_ctable;
	120	extern unsigned long trapbase_cpu1[];
	121	extern unsigned long trapbase_cpu2[];
	122	extern unsigned long trapbase_cpu3[];
	123
	124	void __init smp4m_boot_cpus(void)
	125	{
a54123e2 BB	126	smp_setup_percpu_timer();
	127	local_flush_cache_all();
	128	}
1da177e4	129
92d452f0	130	int __cpuinit smp4m_boot_one_cpu(int i)
a54123e2 BB	131	{
	132	extern unsigned long sun4m_cpu_startup;
	133	unsigned long *entry = &sun4m_cpu_startup;
	134	struct task_struct *p;
	135	int timeout;
	136	int cpu_node;
1da177e4	137
a54123e2 BB	138	cpu_find_by_mid(i, &cpu_node);
	139
	140	/* Cook up an idler for this guy. */
	141	p = fork_idle(i);
	142	current_set[i] = task_thread_info(p);
	143	/* See trampoline.S for details... */
	144	entry += ((i-1) * 3);
1da177e4	145
a54123e2 BB	146	/*
	147	* Initialize the contexts table
	148	* Since the call to prom_startcpu() trashes the structure,
	149	* we need to re-initialize it for each cpu
	150	*/
	151	smp_penguin_ctable.which_io = 0;
	152	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	153	smp_penguin_ctable.reg_size = 0;
1da177e4	154
a54123e2 BB	155	/* whirrr, whirrr, whirrrrrrrrr... */
	156	printk("Starting CPU %d at %p\n", i, entry);
	157	local_flush_cache_all();
	158	prom_startcpu(cpu_node,
	159	&smp_penguin_ctable, 0, (char *)entry);
	160
	161	/* wheee... it's going... */
	162	for(timeout = 0; timeout < 10000; timeout++) {
	163	if(cpu_callin_map[i])
	164	break;
	165	udelay(200);
1da177e4 LT	166	}
1da177e4 LT	167
a54123e2 BB	168	if (!(cpu_callin_map[i])) {
	169	printk("Processor %d is stuck.\n", i);
	170	return -ENODEV;
	171	}
1da177e4	172
1da177e4	173	local_flush_cache_all();
a54123e2 BB	174	return 0;
	175	}
	176
	177	void __init smp4m_smp_done(void)
	178	{
	179	int i, first;
	180	int *prev;
	181
	182	/* setup cpu list for irq rotation */
	183	first = 0;
	184	prev = &first;
	185	for (i = 0; i < NR_CPUS; i++) {
	186	if (cpu_online(i)) {
	187	*prev = i;
	188	prev = &cpu_data(i).next;
1da177e4 LT	189	}
1da177e4 LT	190	}
a54123e2	191	*prev = first;
1da177e4	192	local_flush_cache_all();
1da177e4 LT	193
1da177e4 LT	194	/* Free unneeded trap tables */
a54123e2	195	if (!cpu_isset(1, cpu_present_map)) {
1da177e4	196	ClearPageReserved(virt_to_page(trapbase_cpu1));
7835e98b	197	init_page_count(virt_to_page(trapbase_cpu1));
1da177e4 LT	198	free_page((unsigned long)trapbase_cpu1);
	199	totalram_pages++;
	200	num_physpages++;
	201	}
	202	if (!cpu_isset(2, cpu_present_map)) {
	203	ClearPageReserved(virt_to_page(trapbase_cpu2));
7835e98b	204	init_page_count(virt_to_page(trapbase_cpu2));
1da177e4 LT	205	free_page((unsigned long)trapbase_cpu2);
	206	totalram_pages++;
	207	num_physpages++;
	208	}
	209	if (!cpu_isset(3, cpu_present_map)) {
	210	ClearPageReserved(virt_to_page(trapbase_cpu3));
7835e98b	211	init_page_count(virt_to_page(trapbase_cpu3));
1da177e4 LT	212	free_page((unsigned long)trapbase_cpu3);
	213	totalram_pages++;
	214	num_physpages++;
	215	}
	216
	217	/* Ok, they are spinning and ready to go. */
1da177e4 LT	218	}
	219
	220	/* At each hardware IRQ, we get this called to forward IRQ reception
	221	* to the next processor. The caller must disable the IRQ level being
	222	* serviced globally so that there are no double interrupts received.
	223	*
	224	* XXX See sparc64 irq.c.
	225	*/
	226	void smp4m_irq_rotate(int cpu)
	227	{
a54123e2 BB	228	int next = cpu_data(cpu).next;
	229	if (next != cpu)
	230	set_irq_udt(next);
1da177e4 LT	231	}
1da177e4 LT	232
1da177e4 LT	233	static struct smp_funcall {
	234	smpfunc_t func;
	235	unsigned long arg1;
	236	unsigned long arg2;
	237	unsigned long arg3;
	238	unsigned long arg4;
	239	unsigned long arg5;
a54123e2 BB	240	unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
a54123e2 BB	241	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
1da177e4 LT	242	} ccall_info;
	243
	244	static DEFINE_SPINLOCK(cross_call_lock);
	245
	246	/* Cross calls must be serialized, at least currently. */
66e4f8c0	247	static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
c61c65cd	248	unsigned long arg2, unsigned long arg3,
66e4f8c0	249	unsigned long arg4)
1da177e4	250	{
a54123e2	251	register int ncpus = SUN4M_NCPUS;
1da177e4 LT	252	unsigned long flags;
	253
	254	spin_lock_irqsave(&cross_call_lock, flags);
	255
	256	/* Init function glue. */
	257	ccall_info.func = func;
	258	ccall_info.arg1 = arg1;
	259	ccall_info.arg2 = arg2;
	260	ccall_info.arg3 = arg3;
	261	ccall_info.arg4 = arg4;
66e4f8c0	262	ccall_info.arg5 = 0;
1da177e4 LT	263
	264	/* Init receive/complete mapping, plus fire the IPI's off. */
	265	{
1da177e4 LT	266	register int i;
	267
	268	cpu_clear(smp_processor_id(), mask);
66e4f8c0	269	cpus_and(mask, cpu_online_map, mask);
1da177e4 LT	270	for(i = 0; i < ncpus; i++) {
	271	if (cpu_isset(i, mask)) {
	272	ccall_info.processors_in[i] = 0;
	273	ccall_info.processors_out[i] = 0;
	274	set_cpu_int(i, IRQ_CROSS_CALL);
	275	} else {
	276	ccall_info.processors_in[i] = 1;
	277	ccall_info.processors_out[i] = 1;
	278	}
	279	}
	280	}
	281
	282	{
	283	register int i;
	284
	285	i = 0;
	286	do {
66e4f8c0 DM	287	if (!cpu_isset(i, mask))
66e4f8c0 DM	288	continue;
1da177e4 LT	289	while(!ccall_info.processors_in[i])
	290	barrier();
	291	} while(++i < ncpus);
	292
	293	i = 0;
	294	do {
66e4f8c0 DM	295	if (!cpu_isset(i, mask))
66e4f8c0 DM	296	continue;
1da177e4 LT	297	while(!ccall_info.processors_out[i])
	298	barrier();
	299	} while(++i < ncpus);
	300	}
	301
	302	spin_unlock_irqrestore(&cross_call_lock, flags);
1da177e4 LT	303	}
	304
	305	/* Running cross calls. */
	306	void smp4m_cross_call_irq(void)
	307	{
	308	int i = smp_processor_id();
	309
	310	ccall_info.processors_in[i] = 1;
	311	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	312	ccall_info.arg4, ccall_info.arg5);
	313	ccall_info.processors_out[i] = 1;
	314	}
	315
	316	void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
	317	{
0d84438d	318	struct pt_regs *old_regs;
1da177e4 LT	319	int cpu = smp_processor_id();
1da177e4 LT	320
0d84438d AV	321	old_regs = set_irq_regs(regs);
0d84438d AV	322
1da177e4 LT	323	clear_profile_irq(cpu);
1da177e4 LT	324
0d84438d	325	profile_tick(CPU_PROFILING);
1da177e4 LT	326
	327	if(!--prof_counter(cpu)) {
	328	int user = user_mode(regs);
	329
	330	irq_enter();
	331	update_process_times(user);
	332	irq_exit();
	333
	334	prof_counter(cpu) = prof_multiplier(cpu);
	335	}
0d84438d	336	set_irq_regs(old_regs);
1da177e4 LT	337	}
	338
	339	extern unsigned int lvl14_resolution;
	340
	341	static void __init smp_setup_percpu_timer(void)
	342	{
	343	int cpu = smp_processor_id();
	344
	345	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	346	load_profile_irq(cpu, lvl14_resolution);
	347
	348	if(cpu == boot_cpu_id)
	349	enable_pil_irq(14);
	350	}
	351
c61c65cd	352	static void __init smp4m_blackbox_id(unsigned *addr)
1da177e4 LT	353	{
	354	int rd = *addr & 0x3e000000;
	355	int rs1 = rd >> 11;
	356
	357	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	358	addr[1] = 0x8130200c \| rd \| rs1; /* srl reg, 0xc, reg */
	359	addr[2] = 0x80082003 \| rd \| rs1; /* and reg, 3, reg */
	360	}
	361
c61c65cd	362	static void __init smp4m_blackbox_current(unsigned *addr)
1da177e4 LT	363	{
	364	int rd = *addr & 0x3e000000;
	365	int rs1 = rd >> 11;
	366
	367	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	368	addr[2] = 0x8130200a \| rd \| rs1; /* srl reg, 0xa, reg */
4cad6917	369	addr[4] = 0x8008200c \| rd \| rs1; /* and reg, 0xc, reg */
1da177e4 LT	370	}
	371
	372	void __init sun4m_init_smp(void)
	373	{
	374	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	375	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	376	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
1da177e4 LT	377	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
1da177e4 LT	378	}