Commit | Line | Data |
---|---|---|
aba20a82 SR |
1 | /* |
2 | * sun4m SMP support. | |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | */ | |
6 | ||
62f08283 | 7 | #include <linux/clockchips.h> |
1da177e4 | 8 | #include <linux/interrupt.h> |
1da177e4 | 9 | #include <linux/profile.h> |
6c81c32f | 10 | #include <linux/delay.h> |
4245e59d | 11 | #include <linux/cpu.h> |
6c81c32f | 12 | |
1da177e4 | 13 | #include <asm/cacheflush.h> |
bde4d8b2 | 14 | #include <asm/switch_to.h> |
1da177e4 | 15 | #include <asm/tlbflush.h> |
62f08283 | 16 | #include <asm/timer.h> |
1da177e4 | 17 | |
32231a66 | 18 | #include "irq.h" |
aba20a82 | 19 | #include "kernel.h" |
32231a66 | 20 | |
ecbc42b7 DH |
21 | #define IRQ_IPI_SINGLE 12 |
22 | #define IRQ_IPI_MASK 13 | |
23 | #define IRQ_IPI_RESCHED 14 | |
1da177e4 LT |
24 | #define IRQ_CROSS_CALL 15 |
25 | ||
1a8a27c9 WF |
26 | static inline unsigned long |
27 | swap_ulong(volatile unsigned long *ptr, unsigned long val) | |
1da177e4 LT |
28 | { |
29 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
30 | "=&r" (val), "=&r" (ptr) : | |
31 | "0" (val), "1" (ptr)); | |
32 | return val; | |
33 | } | |
34 | ||
ecbc42b7 | 35 | static void smp4m_ipi_init(void); |
1da177e4 | 36 | |
92d452f0 | 37 | void __cpuinit smp4m_callin(void) |
1da177e4 LT |
38 | { |
39 | int cpuid = hard_smp_processor_id(); | |
40 | ||
41 | local_flush_cache_all(); | |
42 | local_flush_tlb_all(); | |
43 | ||
e545a614 MS |
44 | notify_cpu_starting(cpuid); |
45 | ||
62f08283 | 46 | register_percpu_ce(cpuid); |
1da177e4 LT |
47 | |
48 | calibrate_delay(); | |
49 | smp_store_cpu_info(cpuid); | |
50 | ||
51 | local_flush_cache_all(); | |
52 | local_flush_tlb_all(); | |
53 | ||
54 | /* | |
55 | * Unblock the master CPU _only_ when the scheduler state | |
56 | * of all secondary CPUs will be up-to-date, so after | |
57 | * the SMP initialization the master will be just allowed | |
58 | * to call the scheduler code. | |
59 | */ | |
60 | /* Allow master to continue. */ | |
1a8a27c9 | 61 | swap_ulong(&cpu_callin_map[cpuid], 1); |
1da177e4 | 62 | |
a54123e2 | 63 | /* XXX: What's up with all the flushes? */ |
1da177e4 LT |
64 | local_flush_cache_all(); |
65 | local_flush_tlb_all(); | |
aba20a82 | 66 | |
1da177e4 LT |
67 | /* Fix idle thread fields. */ |
68 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
69 | : : "r" (¤t_set[cpuid]) | |
70 | : "memory" /* paranoid */); | |
71 | ||
72 | /* Attach to the address space of init_task. */ | |
73 | atomic_inc(&init_mm.mm_count); | |
74 | current->active_mm = &init_mm; | |
75 | ||
fb1fece5 | 76 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
a54123e2 | 77 | mb(); |
1da177e4 LT |
78 | |
79 | local_irq_enable(); | |
a54123e2 | 80 | |
fe73971c | 81 | set_cpu_online(cpuid, true); |
1da177e4 LT |
82 | } |
83 | ||
1da177e4 LT |
84 | /* |
85 | * Cycle through the processors asking the PROM to start each one. | |
86 | */ | |
1da177e4 LT |
87 | void __init smp4m_boot_cpus(void) |
88 | { | |
ecbc42b7 | 89 | smp4m_ipi_init(); |
62f08283 | 90 | sun4m_unmask_profile_irq(); |
a54123e2 BB |
91 | local_flush_cache_all(); |
92 | } | |
1da177e4 | 93 | |
92d452f0 | 94 | int __cpuinit smp4m_boot_one_cpu(int i) |
a54123e2 | 95 | { |
a54123e2 BB |
96 | unsigned long *entry = &sun4m_cpu_startup; |
97 | struct task_struct *p; | |
98 | int timeout; | |
99 | int cpu_node; | |
1da177e4 | 100 | |
a54123e2 BB |
101 | cpu_find_by_mid(i, &cpu_node); |
102 | ||
103 | /* Cook up an idler for this guy. */ | |
104 | p = fork_idle(i); | |
105 | current_set[i] = task_thread_info(p); | |
106 | /* See trampoline.S for details... */ | |
aba20a82 | 107 | entry += ((i - 1) * 3); |
1da177e4 | 108 | |
a54123e2 BB |
109 | /* |
110 | * Initialize the contexts table | |
111 | * Since the call to prom_startcpu() trashes the structure, | |
112 | * we need to re-initialize it for each cpu | |
113 | */ | |
114 | smp_penguin_ctable.which_io = 0; | |
115 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
116 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 117 | |
a54123e2 | 118 | /* whirrr, whirrr, whirrrrrrrrr... */ |
aba20a82 | 119 | printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); |
a54123e2 | 120 | local_flush_cache_all(); |
aba20a82 | 121 | prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); |
a54123e2 BB |
122 | |
123 | /* wheee... it's going... */ | |
aba20a82 SR |
124 | for (timeout = 0; timeout < 10000; timeout++) { |
125 | if (cpu_callin_map[i]) | |
a54123e2 BB |
126 | break; |
127 | udelay(200); | |
1da177e4 LT |
128 | } |
129 | ||
a54123e2 | 130 | if (!(cpu_callin_map[i])) { |
aba20a82 | 131 | printk(KERN_ERR "Processor %d is stuck.\n", i); |
a54123e2 BB |
132 | return -ENODEV; |
133 | } | |
1da177e4 | 134 | |
1da177e4 | 135 | local_flush_cache_all(); |
a54123e2 BB |
136 | return 0; |
137 | } | |
138 | ||
139 | void __init smp4m_smp_done(void) | |
140 | { | |
141 | int i, first; | |
142 | int *prev; | |
143 | ||
144 | /* setup cpu list for irq rotation */ | |
145 | first = 0; | |
146 | prev = &first; | |
ec7c14bd RR |
147 | for_each_online_cpu(i) { |
148 | *prev = i; | |
149 | prev = &cpu_data(i).next; | |
1da177e4 | 150 | } |
a54123e2 | 151 | *prev = first; |
1da177e4 | 152 | local_flush_cache_all(); |
1da177e4 | 153 | |
1da177e4 | 154 | /* Ok, they are spinning and ready to go. */ |
1da177e4 LT |
155 | } |
156 | ||
ecbc42b7 DH |
157 | |
158 | /* Initialize IPIs on the SUN4M SMP machine */ | |
159 | static void __init smp4m_ipi_init(void) | |
160 | { | |
161 | } | |
162 | ||
163 | static void smp4m_ipi_resched(int cpu) | |
164 | { | |
165 | set_cpu_int(cpu, IRQ_IPI_RESCHED); | |
166 | } | |
167 | ||
168 | static void smp4m_ipi_single(int cpu) | |
169 | { | |
170 | set_cpu_int(cpu, IRQ_IPI_SINGLE); | |
171 | } | |
172 | ||
173 | static void smp4m_ipi_mask_one(int cpu) | |
174 | { | |
175 | set_cpu_int(cpu, IRQ_IPI_MASK); | |
176 | } | |
177 | ||
1da177e4 LT |
178 | static struct smp_funcall { |
179 | smpfunc_t func; | |
180 | unsigned long arg1; | |
181 | unsigned long arg2; | |
182 | unsigned long arg3; | |
183 | unsigned long arg4; | |
184 | unsigned long arg5; | |
a54123e2 BB |
185 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
186 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
187 | } ccall_info; |
188 | ||
189 | static DEFINE_SPINLOCK(cross_call_lock); | |
190 | ||
191 | /* Cross calls must be serialized, at least currently. */ | |
66e4f8c0 | 192 | static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 193 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 194 | unsigned long arg4) |
1da177e4 | 195 | { |
a54123e2 | 196 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
197 | unsigned long flags; |
198 | ||
199 | spin_lock_irqsave(&cross_call_lock, flags); | |
200 | ||
201 | /* Init function glue. */ | |
202 | ccall_info.func = func; | |
203 | ccall_info.arg1 = arg1; | |
204 | ccall_info.arg2 = arg2; | |
205 | ccall_info.arg3 = arg3; | |
206 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 207 | ccall_info.arg5 = 0; |
1da177e4 LT |
208 | |
209 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
210 | { | |
1da177e4 LT |
211 | register int i; |
212 | ||
fb1fece5 KM |
213 | cpumask_clear_cpu(smp_processor_id(), &mask); |
214 | cpumask_and(&mask, cpu_online_mask, &mask); | |
aba20a82 | 215 | for (i = 0; i < ncpus; i++) { |
fb1fece5 | 216 | if (cpumask_test_cpu(i, &mask)) { |
1da177e4 LT |
217 | ccall_info.processors_in[i] = 0; |
218 | ccall_info.processors_out[i] = 0; | |
219 | set_cpu_int(i, IRQ_CROSS_CALL); | |
220 | } else { | |
221 | ccall_info.processors_in[i] = 1; | |
222 | ccall_info.processors_out[i] = 1; | |
223 | } | |
224 | } | |
225 | } | |
226 | ||
227 | { | |
228 | register int i; | |
229 | ||
230 | i = 0; | |
231 | do { | |
fb1fece5 | 232 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 233 | continue; |
aba20a82 | 234 | while (!ccall_info.processors_in[i]) |
1da177e4 | 235 | barrier(); |
aba20a82 | 236 | } while (++i < ncpus); |
1da177e4 LT |
237 | |
238 | i = 0; | |
239 | do { | |
fb1fece5 | 240 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 241 | continue; |
aba20a82 | 242 | while (!ccall_info.processors_out[i]) |
1da177e4 | 243 | barrier(); |
aba20a82 | 244 | } while (++i < ncpus); |
1da177e4 | 245 | } |
1da177e4 | 246 | spin_unlock_irqrestore(&cross_call_lock, flags); |
1da177e4 LT |
247 | } |
248 | ||
249 | /* Running cross calls. */ | |
250 | void smp4m_cross_call_irq(void) | |
251 | { | |
252 | int i = smp_processor_id(); | |
253 | ||
254 | ccall_info.processors_in[i] = 1; | |
255 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
256 | ccall_info.arg4, ccall_info.arg5); | |
257 | ccall_info.processors_out[i] = 1; | |
258 | } | |
259 | ||
260 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) | |
261 | { | |
0d84438d | 262 | struct pt_regs *old_regs; |
62f08283 | 263 | struct clock_event_device *ce; |
1da177e4 LT |
264 | int cpu = smp_processor_id(); |
265 | ||
0d84438d AV |
266 | old_regs = set_irq_regs(regs); |
267 | ||
62f08283 | 268 | ce = &per_cpu(sparc32_clockevent, cpu); |
1da177e4 | 269 | |
62f08283 TK |
270 | if (ce->mode & CLOCK_EVT_MODE_PERIODIC) |
271 | sun4m_clear_profile_irq(cpu); | |
272 | else | |
273 | load_profile_irq(cpu, 0); /* Is this needless? */ | |
1da177e4 | 274 | |
62f08283 TK |
275 | irq_enter(); |
276 | ce->event_handler(ce); | |
277 | irq_exit(); | |
1da177e4 | 278 | |
0d84438d | 279 | set_irq_regs(old_regs); |
1da177e4 LT |
280 | } |
281 | ||
c61c65cd | 282 | static void __init smp4m_blackbox_id(unsigned *addr) |
1da177e4 LT |
283 | { |
284 | int rd = *addr & 0x3e000000; | |
285 | int rs1 = rd >> 11; | |
aba20a82 | 286 | |
1da177e4 | 287 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ |
aba20a82 | 288 | addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */ |
1da177e4 LT |
289 | addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */ |
290 | } | |
291 | ||
c61c65cd | 292 | static void __init smp4m_blackbox_current(unsigned *addr) |
1da177e4 LT |
293 | { |
294 | int rd = *addr & 0x3e000000; | |
295 | int rs1 = rd >> 11; | |
aba20a82 | 296 | |
1da177e4 | 297 | addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ |
aba20a82 | 298 | addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ |
4cad6917 | 299 | addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */ |
1da177e4 LT |
300 | } |
301 | ||
302 | void __init sun4m_init_smp(void) | |
303 | { | |
304 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id); | |
305 | BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current); | |
306 | BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM); | |
1da177e4 | 307 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM); |
ecbc42b7 DH |
308 | BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM); |
309 | BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM); | |
310 | BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM); | |
1da177e4 | 311 | } |