[deliverable/linux.git] / arch / sparc / kernel / sun4m_smp.c

/* sun4m_smp.c: Sparc SUN4M SMP support.
 *
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <asm/head.h>

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/threads.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/profile.h>
#include <linux/delay.h>
#include <linux/cpu.h>

#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/irq_regs.h>

#include <asm/ptrace.h>
#include <asm/atomic.h>

#include <asm/irq.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/oplib.h>
#include <asm/cpudata.h>

#include "irq.h"

#define IRQ_CROSS_CALL		15

extern ctxd_t *srmmu_ctx_table_phys;

extern volatile unsigned long cpu_callin_map[NR_CPUS];
extern unsigned char boot_cpu_id;

extern cpumask_t smp_commenced_mask;

extern int __smp4m_processor_id(void);

/*#define SMP_DEBUG*/

#ifdef SMP_DEBUG
#define SMP_PRINTK(x)	printk x
#else
#define SMP_PRINTK(x)
#endif

static inline unsigned long
swap_ulong(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp_setup_percpu_timer(void);
extern void cpu_probe(void);

void __cpuinit smp4m_callin(void)
{
	int cpuid = hard_smp_processor_id();

	local_flush_cache_all();
	local_flush_tlb_all();

	notify_cpu_starting(cpuid);

	/* Get our local ticker going. */
	smp_setup_percpu_timer();

	calibrate_delay();
	smp_store_cpu_info(cpuid);

	local_flush_cache_all();
	local_flush_tlb_all();

	/*
	 * Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	/* Allow master to continue. */
	swap_ulong(&cpu_callin_map[cpuid], 1);

	/* XXX: What's up with all the flushes? */
	local_flush_cache_all();
	local_flush_tlb_all();
	
	cpu_probe();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	/* Attach to the address space of init_task. */
	atomic_inc(&init_mm.mm_count);
	current->active_mm = &init_mm;

	while (!cpu_isset(cpuid, smp_commenced_mask))
		mb();

	local_irq_enable();

	cpu_set(cpuid, cpu_online_map);
}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
 
extern struct linux_prom_registers smp_penguin_ctable;
extern unsigned long trapbase_cpu1[];
extern unsigned long trapbase_cpu2[];
extern unsigned long trapbase_cpu3[];

void __init smp4m_boot_cpus(void)
{
	smp_setup_percpu_timer();
	local_flush_cache_all();
}

int __cpuinit smp4m_boot_one_cpu(int i)
{
	extern unsigned long sun4m_cpu_startup;
	unsigned long *entry = &sun4m_cpu_startup;
	struct task_struct *p;
	int timeout;
	int cpu_node;

	cpu_find_by_mid(i, &cpu_node);

	/* Cook up an idler for this guy. */
	p = fork_idle(i);
	current_set[i] = task_thread_info(p);
	/* See trampoline.S for details... */
	entry += ((i-1) * 3);

	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk("Starting CPU %d at %p\n", i, entry);
	local_flush_cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	/* wheee... it's going... */
	for(timeout = 0; timeout < 10000; timeout++) {
		if(cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk("Processor %d is stuck.\n", i);
		return -ENODEV;
	}

	local_flush_cache_all();
	return 0;
}

void __init smp4m_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for (i = 0; i < NR_CPUS; i++) {
		if (cpu_online(i)) {
			*prev = i;
			prev = &cpu_data(i).next;
		}
	}
	*prev = first;
	local_flush_cache_all();

	/* Free unneeded trap tables */
	if (!cpu_isset(1, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu1));
		init_page_count(virt_to_page(trapbase_cpu1));
		free_page((unsigned long)trapbase_cpu1);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(2, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu2));
		init_page_count(virt_to_page(trapbase_cpu2));
		free_page((unsigned long)trapbase_cpu2);
		totalram_pages++;
		num_physpages++;
	}
	if (!cpu_isset(3, cpu_present_map)) {
		ClearPageReserved(virt_to_page(trapbase_cpu3));
		init_page_count(virt_to_page(trapbase_cpu3));
		free_page((unsigned long)trapbase_cpu3);
		totalram_pages++;
		num_physpages++;
	}

	/* Ok, they are spinning and ready to go. */
}

/* At each hardware IRQ, we get this called to forward IRQ reception
 * to the next processor.  The caller must disable the IRQ level being
 * serviced globally so that there are no double interrupts received.
 *
 * XXX See sparc64 irq.c.
 */
void smp4m_irq_rotate(int cpu)
{
	int next = cpu_data(cpu).next;
	if (next != cpu)
		set_irq_udt(next);
}

static struct smp_funcall {
	smpfunc_t func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned long processors_in[SUN4M_NCPUS];  /* Set when ipi entered. */
	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
} ccall_info;

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
		register int ncpus = SUN4M_NCPUS;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		/* Init function glue. */
		ccall_info.func = func;
		ccall_info.arg1 = arg1;
		ccall_info.arg2 = arg2;
		ccall_info.arg3 = arg3;
		ccall_info.arg4 = arg4;
		ccall_info.arg5 = 0;

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpu_clear(smp_processor_id(), mask);
			cpus_and(mask, cpu_online_map, mask);
			for(i = 0; i < ncpus; i++) {
				if (cpu_isset(i, mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					set_cpu_int(i, IRQ_CROSS_CALL);
				} else {
					ccall_info.processors_in[i] = 1;
					ccall_info.processors_out[i] = 1;
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while(!ccall_info.processors_in[i])
					barrier();
			} while(++i < ncpus);

			i = 0;
			do {
				if (!cpu_isset(i, mask))
					continue;
				while(!ccall_info.processors_out[i])
					barrier();
			} while(++i < ncpus);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
}

/* Running cross calls. */
void smp4m_cross_call_irq(void)
{
	int i = smp_processor_id();

	ccall_info.processors_in[i] = 1;
	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
			ccall_info.arg4, ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

extern void sun4m_clear_profile_irq(int cpu);

void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = smp_processor_id();

	old_regs = set_irq_regs(regs);

	sun4m_clear_profile_irq(cpu);

	profile_tick(CPU_PROFILING);

	if(!--prof_counter(cpu)) {
		int user = user_mode(regs);

		irq_enter();
		update_process_times(user);
		irq_exit();

		prof_counter(cpu) = prof_multiplier(cpu);
	}
	set_irq_regs(old_regs);
}

extern unsigned int lvl14_resolution;

static void __cpuinit smp_setup_percpu_timer(void)
{
	int cpu = smp_processor_id();

	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	load_profile_irq(cpu, lvl14_resolution);

	if(cpu == boot_cpu_id)
		enable_pil_irq(14);
}

static void __init smp4m_blackbox_id(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[1] = 0x8130200c | rd | rs1;    	/* srl reg, 0xc, reg */
	addr[2] = 0x80082003 | rd | rs1;	/* and reg, 3, reg */
}

static void __init smp4m_blackbox_current(unsigned *addr)
{
	int rd = *addr & 0x3e000000;
	int rs1 = rd >> 11;
	
	addr[0] = 0x81580000 | rd;		/* rd %tbr, reg */
	addr[2] = 0x8130200a | rd | rs1;    	/* srl reg, 0xa, reg */
	addr[4] = 0x8008200c | rd | rs1;	/* and reg, 0xc, reg */
}

void __init sun4m_init_smp(void)
{
	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
}
Commit	Line	Data
1da177e4 LT	1	/* sun4m_smp.c: Sparc SUN4M SMP support.
	2	*
	3	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	4	*/
	5
	6	#include <asm/head.h>
	7
	8	#include <linux/kernel.h>
	9	#include <linux/sched.h>
	10	#include <linux/threads.h>
	11	#include <linux/smp.h>
1da177e4 LT	12	#include <linux/interrupt.h>
	13	#include <linux/kernel_stat.h>
	14	#include <linux/init.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/mm.h>
	17	#include <linux/swap.h>
	18	#include <linux/profile.h>
6c81c32f	19	#include <linux/delay.h>
4245e59d	20	#include <linux/cpu.h>
6c81c32f	21
1da177e4 LT	22	#include <asm/cacheflush.h>
1da177e4 LT	23	#include <asm/tlbflush.h>
0d84438d	24	#include <asm/irq_regs.h>
1da177e4 LT	25
	26	#include <asm/ptrace.h>
	27	#include <asm/atomic.h>
	28
1da177e4 LT	29	#include <asm/irq.h>
	30	#include <asm/page.h>
	31	#include <asm/pgalloc.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/oplib.h>
	34	#include <asm/cpudata.h>
	35
32231a66 AV	36	#include "irq.h"
32231a66 AV	37
1da177e4 LT	38	#define IRQ_CROSS_CALL 15
	39
	40	extern ctxd_t *srmmu_ctx_table_phys;
	41
1da177e4 LT	42	extern volatile unsigned long cpu_callin_map[NR_CPUS];
1da177e4 LT	43	extern unsigned char boot_cpu_id;
a54123e2 BB	44
	45	extern cpumask_t smp_commenced_mask;
	46
1da177e4 LT	47	extern int __smp4m_processor_id(void);
	48
	49	/#define SMP_DEBUG/
	50
	51	#ifdef SMP_DEBUG
	52	#define SMP_PRINTK(x) printk x
	53	#else
	54	#define SMP_PRINTK(x)
	55	#endif
	56
1a8a27c9 WF	57	static inline unsigned long
1a8a27c9 WF	58	swap_ulong(volatile unsigned long *ptr, unsigned long val)
1da177e4 LT	59	{
	60	__asm__ __volatile__("swap [%1], %0\n\t" :
	61	"=&r" (val), "=&r" (ptr) :
	62	"0" (val), "1" (ptr));
	63	return val;
	64	}
	65
	66	static void smp_setup_percpu_timer(void);
	67	extern void cpu_probe(void);
	68
92d452f0	69	void __cpuinit smp4m_callin(void)
1da177e4 LT	70	{
	71	int cpuid = hard_smp_processor_id();
	72
	73	local_flush_cache_all();
	74	local_flush_tlb_all();
	75
e545a614 MS	76	notify_cpu_starting(cpuid);
e545a614 MS	77
1da177e4 LT	78	/* Get our local ticker going. */
	79	smp_setup_percpu_timer();
	80
	81	calibrate_delay();
	82	smp_store_cpu_info(cpuid);
	83
	84	local_flush_cache_all();
	85	local_flush_tlb_all();
	86
	87	/*
	88	* Unblock the master CPU _only_ when the scheduler state
	89	* of all secondary CPUs will be up-to-date, so after
	90	* the SMP initialization the master will be just allowed
	91	* to call the scheduler code.
	92	*/
	93	/* Allow master to continue. */
1a8a27c9	94	swap_ulong(&cpu_callin_map[cpuid], 1);
1da177e4	95
a54123e2	96	/* XXX: What's up with all the flushes? */
1da177e4 LT	97	local_flush_cache_all();
	98	local_flush_tlb_all();
	99
	100	cpu_probe();
	101
	102	/* Fix idle thread fields. */
	103	__asm__ __volatile__("ld [%0], %%g6\n\t"
	104	: : "r" (&current_set[cpuid])
	105	: "memory" /* paranoid */);
	106
	107	/* Attach to the address space of init_task. */
	108	atomic_inc(&init_mm.mm_count);
	109	current->active_mm = &init_mm;
	110
a54123e2 BB	111	while (!cpu_isset(cpuid, smp_commenced_mask))
a54123e2 BB	112	mb();
1da177e4 LT	113
1da177e4 LT	114	local_irq_enable();
a54123e2 BB	115
a54123e2 BB	116	cpu_set(cpuid, cpu_online_map);
1da177e4 LT	117	}
1da177e4 LT	118
1da177e4 LT	119	/*
	120	* Cycle through the processors asking the PROM to start each one.
	121	*/
	122
	123	extern struct linux_prom_registers smp_penguin_ctable;
	124	extern unsigned long trapbase_cpu1[];
	125	extern unsigned long trapbase_cpu2[];
	126	extern unsigned long trapbase_cpu3[];
	127
	128	void __init smp4m_boot_cpus(void)
	129	{
a54123e2 BB	130	smp_setup_percpu_timer();
	131	local_flush_cache_all();
	132	}
1da177e4	133
92d452f0	134	int __cpuinit smp4m_boot_one_cpu(int i)
a54123e2 BB	135	{
	136	extern unsigned long sun4m_cpu_startup;
	137	unsigned long *entry = &sun4m_cpu_startup;
	138	struct task_struct *p;
	139	int timeout;
	140	int cpu_node;
1da177e4	141
a54123e2 BB	142	cpu_find_by_mid(i, &cpu_node);
	143
	144	/* Cook up an idler for this guy. */
	145	p = fork_idle(i);
	146	current_set[i] = task_thread_info(p);
	147	/* See trampoline.S for details... */
	148	entry += ((i-1) * 3);
1da177e4	149
a54123e2 BB	150	/*
	151	* Initialize the contexts table
	152	* Since the call to prom_startcpu() trashes the structure,
	153	* we need to re-initialize it for each cpu
	154	*/
	155	smp_penguin_ctable.which_io = 0;
	156	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	157	smp_penguin_ctable.reg_size = 0;
1da177e4	158
a54123e2 BB	159	/* whirrr, whirrr, whirrrrrrrrr... */
	160	printk("Starting CPU %d at %p\n", i, entry);
	161	local_flush_cache_all();
	162	prom_startcpu(cpu_node,
	163	&smp_penguin_ctable, 0, (char *)entry);
	164
	165	/* wheee... it's going... */
	166	for(timeout = 0; timeout < 10000; timeout++) {
	167	if(cpu_callin_map[i])
	168	break;
	169	udelay(200);
1da177e4 LT	170	}
1da177e4 LT	171
a54123e2 BB	172	if (!(cpu_callin_map[i])) {
	173	printk("Processor %d is stuck.\n", i);
	174	return -ENODEV;
	175	}
1da177e4	176
1da177e4	177	local_flush_cache_all();
a54123e2 BB	178	return 0;
	179	}
	180
	181	void __init smp4m_smp_done(void)
	182	{
	183	int i, first;
	184	int *prev;
	185
	186	/* setup cpu list for irq rotation */
	187	first = 0;
	188	prev = &first;
	189	for (i = 0; i < NR_CPUS; i++) {
	190	if (cpu_online(i)) {
	191	*prev = i;
	192	prev = &cpu_data(i).next;
1da177e4 LT	193	}
1da177e4 LT	194	}
a54123e2	195	*prev = first;
1da177e4	196	local_flush_cache_all();
1da177e4 LT	197
1da177e4 LT	198	/* Free unneeded trap tables */
a54123e2	199	if (!cpu_isset(1, cpu_present_map)) {
1da177e4	200	ClearPageReserved(virt_to_page(trapbase_cpu1));
7835e98b	201	init_page_count(virt_to_page(trapbase_cpu1));
1da177e4 LT	202	free_page((unsigned long)trapbase_cpu1);
	203	totalram_pages++;
	204	num_physpages++;
	205	}
	206	if (!cpu_isset(2, cpu_present_map)) {
	207	ClearPageReserved(virt_to_page(trapbase_cpu2));
7835e98b	208	init_page_count(virt_to_page(trapbase_cpu2));
1da177e4 LT	209	free_page((unsigned long)trapbase_cpu2);
	210	totalram_pages++;
	211	num_physpages++;
	212	}
	213	if (!cpu_isset(3, cpu_present_map)) {
	214	ClearPageReserved(virt_to_page(trapbase_cpu3));
7835e98b	215	init_page_count(virt_to_page(trapbase_cpu3));
1da177e4 LT	216	free_page((unsigned long)trapbase_cpu3);
	217	totalram_pages++;
	218	num_physpages++;
	219	}
	220
	221	/* Ok, they are spinning and ready to go. */
1da177e4 LT	222	}
	223
	224	/* At each hardware IRQ, we get this called to forward IRQ reception
	225	* to the next processor. The caller must disable the IRQ level being
	226	* serviced globally so that there are no double interrupts received.
	227	*
	228	* XXX See sparc64 irq.c.
	229	*/
	230	void smp4m_irq_rotate(int cpu)
	231	{
a54123e2 BB	232	int next = cpu_data(cpu).next;
	233	if (next != cpu)
	234	set_irq_udt(next);
1da177e4 LT	235	}
1da177e4 LT	236
1da177e4 LT	237	static struct smp_funcall {
	238	smpfunc_t func;
	239	unsigned long arg1;
	240	unsigned long arg2;
	241	unsigned long arg3;
	242	unsigned long arg4;
	243	unsigned long arg5;
a54123e2 BB	244	unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
a54123e2 BB	245	unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
1da177e4 LT	246	} ccall_info;
	247
	248	static DEFINE_SPINLOCK(cross_call_lock);
	249
	250	/* Cross calls must be serialized, at least currently. */
66e4f8c0	251	static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
c61c65cd	252	unsigned long arg2, unsigned long arg3,
66e4f8c0	253	unsigned long arg4)
1da177e4	254	{
a54123e2	255	register int ncpus = SUN4M_NCPUS;
1da177e4 LT	256	unsigned long flags;
	257
	258	spin_lock_irqsave(&cross_call_lock, flags);
	259
	260	/* Init function glue. */
	261	ccall_info.func = func;
	262	ccall_info.arg1 = arg1;
	263	ccall_info.arg2 = arg2;
	264	ccall_info.arg3 = arg3;
	265	ccall_info.arg4 = arg4;
66e4f8c0	266	ccall_info.arg5 = 0;
1da177e4 LT	267
	268	/* Init receive/complete mapping, plus fire the IPI's off. */
	269	{
1da177e4 LT	270	register int i;
	271
	272	cpu_clear(smp_processor_id(), mask);
66e4f8c0	273	cpus_and(mask, cpu_online_map, mask);
1da177e4 LT	274	for(i = 0; i < ncpus; i++) {
	275	if (cpu_isset(i, mask)) {
	276	ccall_info.processors_in[i] = 0;
	277	ccall_info.processors_out[i] = 0;
	278	set_cpu_int(i, IRQ_CROSS_CALL);
	279	} else {
	280	ccall_info.processors_in[i] = 1;
	281	ccall_info.processors_out[i] = 1;
	282	}
	283	}
	284	}
	285
	286	{
	287	register int i;
	288
	289	i = 0;
	290	do {
66e4f8c0 DM	291	if (!cpu_isset(i, mask))
66e4f8c0 DM	292	continue;
1da177e4 LT	293	while(!ccall_info.processors_in[i])
	294	barrier();
	295	} while(++i < ncpus);
	296
	297	i = 0;
	298	do {
66e4f8c0 DM	299	if (!cpu_isset(i, mask))
66e4f8c0 DM	300	continue;
1da177e4 LT	301	while(!ccall_info.processors_out[i])
	302	barrier();
	303	} while(++i < ncpus);
	304	}
	305
	306	spin_unlock_irqrestore(&cross_call_lock, flags);
1da177e4 LT	307	}
	308
	309	/* Running cross calls. */
	310	void smp4m_cross_call_irq(void)
	311	{
	312	int i = smp_processor_id();
	313
	314	ccall_info.processors_in[i] = 1;
	315	ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
	316	ccall_info.arg4, ccall_info.arg5);
	317	ccall_info.processors_out[i] = 1;
	318	}
	319
1de937a5 DM	320	extern void sun4m_clear_profile_irq(int cpu);
1de937a5 DM	321
1da177e4 LT	322	void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
1da177e4 LT	323	{
0d84438d	324	struct pt_regs *old_regs;
1da177e4 LT	325	int cpu = smp_processor_id();
1da177e4 LT	326
0d84438d AV	327	old_regs = set_irq_regs(regs);
0d84438d AV	328
1de937a5	329	sun4m_clear_profile_irq(cpu);
1da177e4	330
0d84438d	331	profile_tick(CPU_PROFILING);
1da177e4 LT	332
	333	if(!--prof_counter(cpu)) {
	334	int user = user_mode(regs);
	335
	336	irq_enter();
	337	update_process_times(user);
	338	irq_exit();
	339
	340	prof_counter(cpu) = prof_multiplier(cpu);
	341	}
0d84438d	342	set_irq_regs(old_regs);
1da177e4 LT	343	}
	344
	345	extern unsigned int lvl14_resolution;
	346
409832f5	347	static void __cpuinit smp_setup_percpu_timer(void)
1da177e4 LT	348	{
	349	int cpu = smp_processor_id();
	350
	351	prof_counter(cpu) = prof_multiplier(cpu) = 1;
	352	load_profile_irq(cpu, lvl14_resolution);
	353
	354	if(cpu == boot_cpu_id)
	355	enable_pil_irq(14);
	356	}
	357
c61c65cd	358	static void __init smp4m_blackbox_id(unsigned *addr)
1da177e4 LT	359	{
	360	int rd = *addr & 0x3e000000;
	361	int rs1 = rd >> 11;
	362
	363	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	364	addr[1] = 0x8130200c \| rd \| rs1; /* srl reg, 0xc, reg */
	365	addr[2] = 0x80082003 \| rd \| rs1; /* and reg, 3, reg */
	366	}
	367
c61c65cd	368	static void __init smp4m_blackbox_current(unsigned *addr)
1da177e4 LT	369	{
	370	int rd = *addr & 0x3e000000;
	371	int rs1 = rd >> 11;
	372
	373	addr[0] = 0x81580000 \| rd; /* rd %tbr, reg */
	374	addr[2] = 0x8130200a \| rd \| rs1; /* srl reg, 0xa, reg */
4cad6917	375	addr[4] = 0x8008200c \| rd \| rs1; /* and reg, 0xc, reg */
1da177e4 LT	376	}
	377
	378	void __init sun4m_init_smp(void)
	379	{
	380	BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
	381	BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
	382	BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
1da177e4 LT	383	BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
1da177e4 LT	384	}