[deliverable/linux.git] / arch / sparc / kernel / time_32.c

/* linux/arch/sparc/kernel/time.c
 *
 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
 *
 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
 * Added support for the intersil on the sun4/4200
 *
 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
 * Support for MicroSPARC-IIep, PCI CPU.
 *
 * This file handles the Sparc specific time handling details.
 *
 * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
 *		"A Kernel Model for Precision Timekeeping" by Dave Mills
 */
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/rtc/m48t59.h>
#include <linux/timex.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/profile.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include <asm/mc146818rtc.h>
#include <asm/oplib.h>
#include <asm/timex.h>
#include <asm/timer.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/idprom.h>
#include <asm/page.h>
#include <asm/pcic.h>
#include <asm/irq_regs.h>
#include <asm/setup.h>

#include "kernel.h"
#include "irq.h"

static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
static __volatile__ u64 timer_cs_internal_counter = 0;
static char timer_cs_enabled = 0;

static struct clock_event_device timer_ce;
static char timer_ce_enabled = 0;

#ifdef CONFIG_SMP
DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
#endif

DEFINE_SPINLOCK(rtc_lock);
EXPORT_SYMBOL(rtc_lock);

static int set_rtc_mmss(unsigned long);

unsigned long profile_pc(struct pt_regs *regs)
{
	extern char __copy_user_begin[], __copy_user_end[];
	extern char __bzero_begin[], __bzero_end[];

	unsigned long pc = regs->pc;

	if (in_lock_functions(pc) ||
	    (pc >= (unsigned long) __copy_user_begin &&
	     pc < (unsigned long) __copy_user_end) ||
	    (pc >= (unsigned long) __bzero_begin &&
	     pc < (unsigned long) __bzero_end))
		pc = regs->u_regs[UREG_RETPC];
	return pc;
}

EXPORT_SYMBOL(profile_pc);

volatile u32 __iomem *master_l10_counter;

int update_persistent_clock(struct timespec now)
{
	return set_rtc_mmss(now.tv_sec);
}

irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
{
	if (timer_cs_enabled) {
		write_seqlock(&timer_cs_lock);
		timer_cs_internal_counter++;
		sparc_config.clear_clock_irq();
		write_sequnlock(&timer_cs_lock);
	} else {
		sparc_config.clear_clock_irq();
	}

	if (timer_ce_enabled)
		timer_ce.event_handler(&timer_ce);

	return IRQ_HANDLED;
}

static void timer_ce_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
		case CLOCK_EVT_MODE_RESUME:
			timer_ce_enabled = 1;
			break;
		case CLOCK_EVT_MODE_SHUTDOWN:
			timer_ce_enabled = 0;
			break;
		default:
			break;
	}
	smp_mb();
}

static __init void setup_timer_ce(void)
{
	struct clock_event_device *ce = &timer_ce;

	BUG_ON(smp_processor_id() != boot_cpu_id);

	ce->name     = "timer_ce";
	ce->rating   = 100;
	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	ce->set_mode = timer_ce_set_mode;
	ce->cpumask  = cpu_possible_mask;
	ce->shift    = 32;
	ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                      ce->shift);
	clockevents_register_device(ce);
}

static unsigned int sbus_cycles_offset(void)
{
	u32 val, offset;

	val = sbus_readl(master_l10_counter);
	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;

	/* Limit hit? */
	if (val & TIMER_LIMIT_BIT)
		offset += sparc_config.cs_period;

	return offset;
}

static cycle_t timer_cs_read(struct clocksource *cs)
{
	unsigned int seq, offset;
	u64 cycles;

	do {
		seq = read_seqbegin(&timer_cs_lock);

		cycles = timer_cs_internal_counter;
		offset = sparc_config.get_cycles_offset();
	} while (read_seqretry(&timer_cs_lock, seq));

	/* Count absolute cycles */
	cycles *= sparc_config.cs_period;
	cycles += offset;

	return cycles;
}

static struct clocksource timer_cs = {
	.name	= "timer_cs",
	.rating	= 100,
	.read	= timer_cs_read,
	.mask	= CLOCKSOURCE_MASK(64),
	.shift	= 2,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static __init int setup_timer_cs(void)
{
	timer_cs_enabled = 1;
	timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
	                                    timer_cs.shift);

	return clocksource_register(&timer_cs);
}

#ifdef CONFIG_SMP
static void percpu_ce_setup(enum clock_event_mode mode,
			struct clock_event_device *evt)
{
	int cpu = __first_cpu(evt->cpumask);

	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
			sparc_config.load_profile_irq(cpu,
						      SBUS_CLOCK_RATE / HZ);
			break;
		case CLOCK_EVT_MODE_ONESHOT:
		case CLOCK_EVT_MODE_SHUTDOWN:
		case CLOCK_EVT_MODE_UNUSED:
			sparc_config.load_profile_irq(cpu, 0);
			break;
		default:
			break;
	}
}

static int percpu_ce_set_next_event(unsigned long delta,
				    struct clock_event_device *evt)
{
	int cpu = __first_cpu(evt->cpumask);
	unsigned int next = (unsigned int)delta;

	sparc_config.load_profile_irq(cpu, next);
	return 0;
}

void register_percpu_ce(int cpu)
{
	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;

	if (sparc_config.features & FEAT_L14_ONESHOT)
		features |= CLOCK_EVT_FEAT_ONESHOT;

	ce->name           = "percpu_ce";
	ce->rating         = 200;
	ce->features       = features;
	ce->set_mode       = percpu_ce_setup;
	ce->set_next_event = percpu_ce_set_next_event;
	ce->cpumask        = cpumask_of(cpu);
	ce->shift          = 32;
	ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                            ce->shift);
	ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
	ce->min_delta_ns   = clockevent_delta2ns(100, ce);

	clockevents_register_device(ce);
}
#endif

static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	return readb(pdata->ioaddr + ofs);
}

static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	writeb(val, pdata->ioaddr + ofs);
}

static struct m48t59_plat_data m48t59_data = {
	.read_byte = mostek_read_byte,
	.write_byte = mostek_write_byte,
};

/* resource is set at runtime */
static struct platform_device m48t59_rtc = {
	.name		= "rtc-m48t59",
	.id		= 0,
	.num_resources	= 1,
	.dev	= {
		.platform_data = &m48t59_data,
	},
};

static int clock_probe(struct platform_device *op)
{
	struct device_node *dp = op->dev.of_node;
	const char *model = of_get_property(dp, "model", NULL);

	if (!model)
		return -ENODEV;

	/* Only the primary RTC has an address property */
	if (!of_find_property(dp, "address", NULL))
		return -ENODEV;

	m48t59_rtc.resource = &op->resource[0];
	if (!strcmp(model, "mk48t02")) {
		/* Map the clock register io area read-only */
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						2048, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T02;
	} else if (!strcmp(model, "mk48t08")) {
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						8192, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T08;
	} else
		return -ENODEV;

	if (platform_device_register(&m48t59_rtc) < 0)
		printk(KERN_ERR "Registering RTC device failed\n");

	return 0;
}

static struct of_device_id clock_match[] = {
	{
		.name = "eeprom",
	},
	{},
};

static struct platform_driver clock_driver = {
	.probe		= clock_probe,
	.driver = {
		.name = "rtc",
		.owner = THIS_MODULE,
		.of_match_table = clock_match,
	},
};


/* Probe for the mostek real time clock chip. */
static int __init clock_init(void)
{
	return platform_driver_register(&clock_driver);
}
/* Must be after subsys_initcall() so that busses are probed.  Must
 * be before device_initcall() because things like the RTC driver
 * need to see the clock registers.
 */
fs_initcall(clock_init);

static void __init sparc32_late_time_init(void)
{
	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
		setup_timer_ce();
	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
		setup_timer_cs();
#ifdef CONFIG_SMP
	register_percpu_ce(smp_processor_id());
#endif
}

static void __init sbus_time_init(void)
{
	sparc_config.get_cycles_offset = sbus_cycles_offset;
	sparc_config.init_timers();
}

void __init time_init(void)
{
	sparc_config.features = 0;
	late_time_init = sparc32_late_time_init;

	if (pcic_present())
		pci_time_init();
	else
		sbus_time_init();
}


static int set_rtc_mmss(unsigned long secs)
{
	struct rtc_device *rtc = rtc_class_open("rtc0");
	int err = -1;

	if (rtc) {
		err = rtc_set_mmss(rtc, secs);
		rtc_class_close(rtc);
	}

	return err;
}
Commit	Line	Data
64d329ee	1	/* linux/arch/sparc/kernel/time.c
1da177e4	2	*
64d329ee	3	* Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
	5	*
	6	* Chris Davis (cdavis@cois.on.ca) 03/27/1998
	7	* Added support for the intersil on the sun4/4200
	8	*
	9	* Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
	10	* Support for MicroSPARC-IIep, PCI CPU.
	11	*
	12	* This file handles the Sparc specific time handling details.
	13	*
	14	* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
	15	* "A Kernel Model for Precision Timekeeping" by Dave Mills
	16	*/
1da177e4 LT	17	#include <linux/errno.h>
	18	#include <linux/module.h>
	19	#include <linux/sched.h>
	20	#include <linux/kernel.h>
	21	#include <linux/param.h>
	22	#include <linux/string.h>
	23	#include <linux/mm.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/time.h>
c4cbe6f9 DM	26	#include <linux/rtc.h>
c4cbe6f9 DM	27	#include <linux/rtc/m48t59.h>
1da177e4	28	#include <linux/timex.h>
62f08283 TK	29	#include <linux/clocksource.h>
62f08283 TK	30	#include <linux/clockchips.h>
1da177e4 LT	31	#include <linux/init.h>
	32	#include <linux/pci.h>
	33	#include <linux/ioport.h>
	34	#include <linux/profile.h>
454eeb2d	35	#include <linux/of.h>
764f2579	36	#include <linux/of_device.h>
c4cbe6f9	37	#include <linux/platform_device.h>
1da177e4	38
fcea8b27	39	#include <asm/mc146818rtc.h>
1da177e4	40	#include <asm/oplib.h>
0299b137	41	#include <asm/timex.h>
1da177e4	42	#include <asm/timer.h>
1da177e4 LT	43	#include <asm/irq.h>
	44	#include <asm/io.h>
	45	#include <asm/idprom.h>
1da177e4 LT	46	#include <asm/page.h>
1da177e4 LT	47	#include <asm/pcic.h>
0d84438d	48	#include <asm/irq_regs.h>
62f08283	49	#include <asm/setup.h>
1da177e4	50
fcea8b27	51	#include "kernel.h"
32231a66 AV	52	#include "irq.h"
32231a66 AV	53
62f08283 TK	54	static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
	55	static __volatile__ u64 timer_cs_internal_counter = 0;
	56	static char timer_cs_enabled = 0;
	57
	58	static struct clock_event_device timer_ce;
	59	static char timer_ce_enabled = 0;
	60
	61	#ifdef CONFIG_SMP
	62	DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
	63	#endif
	64
1da177e4	65	DEFINE_SPINLOCK(rtc_lock);
6943f3da SR	66	EXPORT_SYMBOL(rtc_lock);
6943f3da SR	67
1da177e4	68	static int set_rtc_mmss(unsigned long);
1da177e4	69
1da177e4 LT	70	unsigned long profile_pc(struct pt_regs *regs)
	71	{
	72	extern char __copy_user_begin[], __copy_user_end[];
1da177e4	73	extern char __bzero_begin[], __bzero_end[];
1da177e4 LT	74
	75	unsigned long pc = regs->pc;
	76
	77	if (in_lock_functions(pc) \|\|
	78	(pc >= (unsigned long) __copy_user_begin &&
	79	pc < (unsigned long) __copy_user_end) \|\|
1da177e4	80	(pc >= (unsigned long) __bzero_begin &&
8a8b836b	81	pc < (unsigned long) __bzero_end))
1da177e4 LT	82	pc = regs->u_regs[UREG_RETPC];
	83	return pc;
	84	}
	85
9550e59c MH	86	EXPORT_SYMBOL(profile_pc);
9550e59c MH	87
fcea8b27	88	volatile u32 __iomem *master_l10_counter;
1da177e4	89
f5c9c9be JS	90	int update_persistent_clock(struct timespec now)
	91	{
	92	return set_rtc_mmss(now.tv_sec);
	93	}
	94
62f08283 TK	95	irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
	96	{
	97	if (timer_cs_enabled) {
	98	write_seqlock(&timer_cs_lock);
	99	timer_cs_internal_counter++;
08c9388f	100	sparc_config.clear_clock_irq();
62f08283 TK	101	write_sequnlock(&timer_cs_lock);
62f08283 TK	102	} else {
08c9388f	103	sparc_config.clear_clock_irq();
62f08283	104	}
1da177e4	105
62f08283 TK	106	if (timer_ce_enabled)
62f08283 TK	107	timer_ce.event_handler(&timer_ce);
1da177e4	108
62f08283 TK	109	return IRQ_HANDLED;
	110	}
	111
	112	static void timer_ce_set_mode(enum clock_event_mode mode,
	113	struct clock_event_device *evt)
1da177e4	114	{
62f08283 TK	115	switch (mode) {
	116	case CLOCK_EVT_MODE_PERIODIC:
	117	case CLOCK_EVT_MODE_RESUME:
	118	timer_ce_enabled = 1;
	119	break;
	120	case CLOCK_EVT_MODE_SHUTDOWN:
	121	timer_ce_enabled = 0;
	122	break;
	123	default:
	124	break;
	125	}
	126	smp_mb();
	127	}
	128
	129	static __init void setup_timer_ce(void)
	130	{
	131	struct clock_event_device *ce = &timer_ce;
	132
	133	BUG_ON(smp_processor_id() != boot_cpu_id);
	134
	135	ce->name = "timer_ce";
	136	ce->rating = 100;
	137	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	138	ce->set_mode = timer_ce_set_mode;
	139	ce->cpumask = cpu_possible_mask;
	140	ce->shift = 32;
	141	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	142	ce->shift);
	143	clockevents_register_device(ce);
	144	}
1da177e4	145
62f08283 TK	146	static unsigned int sbus_cycles_offset(void)
62f08283 TK	147	{
fcea8b27	148	u32 val, offset;
1da177e4	149
fcea8b27	150	val = sbus_readl(master_l10_counter);
62f08283	151	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
1da177e4	152
62f08283 TK	153	/* Limit hit? */
	154	if (val & TIMER_LIMIT_BIT)
	155	offset += sparc_config.cs_period;
	156
	157	return offset;
1da177e4 LT	158	}
1da177e4 LT	159
62f08283 TK	160	static cycle_t timer_cs_read(struct clocksource *cs)
	161	{
	162	unsigned int seq, offset;
	163	u64 cycles;
	164
	165	do {
	166	seq = read_seqbegin(&timer_cs_lock);
	167
	168	cycles = timer_cs_internal_counter;
	169	offset = sparc_config.get_cycles_offset();
	170	} while (read_seqretry(&timer_cs_lock, seq));
	171
	172	/* Count absolute cycles */
	173	cycles *= sparc_config.cs_period;
	174	cycles += offset;
	175
	176	return cycles;
	177	}
	178
	179	static struct clocksource timer_cs = {
	180	.name = "timer_cs",
	181	.rating = 100,
	182	.read = timer_cs_read,
	183	.mask = CLOCKSOURCE_MASK(64),
	184	.shift = 2,
	185	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	186	};
	187
	188	static __init int setup_timer_cs(void)
	189	{
	190	timer_cs_enabled = 1;
	191	timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
	192	timer_cs.shift);
	193
	194	return clocksource_register(&timer_cs);
	195	}
	196
	197	#ifdef CONFIG_SMP
	198	static void percpu_ce_setup(enum clock_event_mode mode,
	199	struct clock_event_device *evt)
	200	{
	201	int cpu = __first_cpu(evt->cpumask);
	202
	203	switch (mode) {
	204	case CLOCK_EVT_MODE_PERIODIC:
08c9388f SR	205	sparc_config.load_profile_irq(cpu,
08c9388f SR	206	SBUS_CLOCK_RATE / HZ);
62f08283 TK	207	break;
	208	case CLOCK_EVT_MODE_ONESHOT:
	209	case CLOCK_EVT_MODE_SHUTDOWN:
	210	case CLOCK_EVT_MODE_UNUSED:
08c9388f	211	sparc_config.load_profile_irq(cpu, 0);
62f08283 TK	212	break;
	213	default:
	214	break;
	215	}
	216	}
	217
	218	static int percpu_ce_set_next_event(unsigned long delta,
	219	struct clock_event_device *evt)
	220	{
	221	int cpu = __first_cpu(evt->cpumask);
	222	unsigned int next = (unsigned int)delta;
	223
08c9388f	224	sparc_config.load_profile_irq(cpu, next);
62f08283 TK	225	return 0;
	226	}
	227
	228	void register_percpu_ce(int cpu)
	229	{
	230	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
	231	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
	232
	233	if (sparc_config.features & FEAT_L14_ONESHOT)
	234	features \|= CLOCK_EVT_FEAT_ONESHOT;
	235
	236	ce->name = "percpu_ce";
	237	ce->rating = 200;
	238	ce->features = features;
	239	ce->set_mode = percpu_ce_setup;
	240	ce->set_next_event = percpu_ce_set_next_event;
	241	ce->cpumask = cpumask_of(cpu);
	242	ce->shift = 32;
	243	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	244	ce->shift);
	245	ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
	246	ce->min_delta_ns = clockevent_delta2ns(100, ce);
	247
	248	clockevents_register_device(ce);
	249	}
	250	#endif
	251
c4cbe6f9	252	static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4	253	{
c4cbe6f9 DM	254	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	255	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	256
12a9ee3c KH	257	return readb(pdata->ioaddr + ofs);
1da177e4 LT	258	}
1da177e4 LT	259
c4cbe6f9	260	static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4	261	{
c4cbe6f9 DM	262	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	263	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	264
12a9ee3c KH	265	writeb(val, pdata->ioaddr + ofs);
1da177e4 LT	266	}
1da177e4 LT	267
c4cbe6f9 DM	268	static struct m48t59_plat_data m48t59_data = {
	269	.read_byte = mostek_read_byte,
	270	.write_byte = mostek_write_byte,
	271	};
	272
	273	/* resource is set at runtime */
	274	static struct platform_device m48t59_rtc = {
	275	.name = "rtc-m48t59",
	276	.id = 0,
	277	.num_resources = 1,
	278	.dev = {
	279	.platform_data = &m48t59_data,
	280	},
	281	};
96ba989d	282
7c9503b8	283	static int clock_probe(struct platform_device *op)
1da177e4	284	{
61c7a080	285	struct device_node *dp = op->dev.of_node;
8271f042	286	const char *model = of_get_property(dp, "model", NULL);
1da177e4	287
ee5caf0e DM	288	if (!model)
ee5caf0e DM	289	return -ENODEV;
1da177e4	290
1c833bc3 KO	291	/* Only the primary RTC has an address property */
	292	if (!of_find_property(dp, "address", NULL))
	293	return -ENODEV;
	294
c4cbe6f9	295	m48t59_rtc.resource = &op->resource[0];
ee5caf0e	296	if (!strcmp(model, "mk48t02")) {
1da177e4	297	/* Map the clock register io area read-only */
c4cbe6f9 DM	298	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	299	2048, "rtc-m48t59");
	300	m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e	301	} else if (!strcmp(model, "mk48t08")) {
c4cbe6f9 DM	302	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	303	8192, "rtc-m48t59");
	304	m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e DM	305	} else
ee5caf0e DM	306	return -ENODEV;
1da177e4	307
c4cbe6f9 DM	308	if (platform_device_register(&m48t59_rtc) < 0)
c4cbe6f9 DM	309	printk(KERN_ERR "Registering RTC device failed\n");
96ba989d	310
ee5caf0e DM	311	return 0;
	312	}
	313
505d9147	314	static struct of_device_id clock_match[] = {
ee5caf0e DM	315	{
	316	.name = "eeprom",
	317	},
	318	{},
	319	};
	320
4ebb24f7	321	static struct platform_driver clock_driver = {
ee5caf0e	322	.probe = clock_probe,
4018294b GL	323	.driver = {
	324	.name = "rtc",
	325	.owner = THIS_MODULE,
	326	.of_match_table = clock_match,
a2cd1558	327	},
ee5caf0e DM	328	};
	329
	330
	331	/* Probe for the mostek real time clock chip. */
96ba989d	332	static int __init clock_init(void)
ee5caf0e	333	{
4ebb24f7	334	return platform_driver_register(&clock_driver);
1da177e4	335	}
96ba989d BB	336	/* Must be after subsys_initcall() so that busses are probed. Must
	337	* be before device_initcall() because things like the RTC driver
	338	* need to see the clock registers.
	339	*/
	340	fs_initcall(clock_init);
96ba989d	341
62f08283	342	static void __init sparc32_late_time_init(void)
1da177e4	343	{
62f08283 TK	344	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
	345	setup_timer_ce();
	346	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
	347	setup_timer_cs();
	348	#ifdef CONFIG_SMP
	349	register_percpu_ce(smp_processor_id());
	350	#endif
1da177e4 LT	351	}
1da177e4 LT	352
62f08283	353	static void __init sbus_time_init(void)
1da177e4	354	{
62f08283 TK	355	sparc_config.get_cycles_offset = sbus_cycles_offset;
62f08283 TK	356	sparc_config.init_timers();
1da177e4 LT	357	}
1da177e4 LT	358
62f08283	359	void __init time_init(void)
1da177e4	360	{
62f08283 TK	361	sparc_config.features = 0;
62f08283 TK	362	late_time_init = sparc32_late_time_init;
1da177e4	363
06010fb5	364	if (pcic_present())
0299b137	365	pci_time_init();
06010fb5 SR	366	else
06010fb5 SR	367	sbus_time_init();
1da177e4 LT	368	}
1da177e4 LT	369
0299b137	370
c4cbe6f9	371	static int set_rtc_mmss(unsigned long secs)
1da177e4	372	{
c4cbe6f9	373	struct rtc_device *rtc = rtc_class_open("rtc0");
ab138c03	374	int err = -1;
1da177e4	375
ab138c03 DM	376	if (rtc) {
	377	err = rtc_set_mmss(rtc, secs);
	378	rtc_class_close(rtc);
	379	}
1da177e4	380
ab138c03	381	return err;
1da177e4	382	}