[deliverable/linux.git] / arch / sparc / kernel / time_32.c

/* linux/arch/sparc/kernel/time.c
 *
 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
 *
 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
 * Added support for the intersil on the sun4/4200
 *
 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
 * Support for MicroSPARC-IIep, PCI CPU.
 *
 * This file handles the Sparc specific time handling details.
 *
 * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
 *		"A Kernel Model for Precision Timekeeping" by Dave Mills
 */
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/rtc/m48t59.h>
#include <linux/timex.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/profile.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include <asm/mc146818rtc.h>
#include <asm/oplib.h>
#include <asm/timex.h>
#include <asm/timer.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/idprom.h>
#include <asm/page.h>
#include <asm/pcic.h>
#include <asm/irq_regs.h>
#include <asm/setup.h>

#include "kernel.h"
#include "irq.h"

static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
static __volatile__ u64 timer_cs_internal_counter = 0;
static char timer_cs_enabled = 0;

static struct clock_event_device timer_ce;
static char timer_ce_enabled = 0;

#ifdef CONFIG_SMP
DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
#endif

DEFINE_SPINLOCK(rtc_lock);
EXPORT_SYMBOL(rtc_lock);

unsigned long profile_pc(struct pt_regs *regs)
{
	extern char __copy_user_begin[], __copy_user_end[];
	extern char __bzero_begin[], __bzero_end[];

	unsigned long pc = regs->pc;

	if (in_lock_functions(pc) ||
	    (pc >= (unsigned long) __copy_user_begin &&
	     pc < (unsigned long) __copy_user_end) ||
	    (pc >= (unsigned long) __bzero_begin &&
	     pc < (unsigned long) __bzero_end))
		pc = regs->u_regs[UREG_RETPC];
	return pc;
}

EXPORT_SYMBOL(profile_pc);

volatile u32 __iomem *master_l10_counter;

irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
{
	if (timer_cs_enabled) {
		write_seqlock(&timer_cs_lock);
		timer_cs_internal_counter++;
		sparc_config.clear_clock_irq();
		write_sequnlock(&timer_cs_lock);
	} else {
		sparc_config.clear_clock_irq();
	}

	if (timer_ce_enabled)
		timer_ce.event_handler(&timer_ce);

	return IRQ_HANDLED;
}

static void timer_ce_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
		case CLOCK_EVT_MODE_RESUME:
			timer_ce_enabled = 1;
			break;
		case CLOCK_EVT_MODE_SHUTDOWN:
			timer_ce_enabled = 0;
			break;
		default:
			break;
	}
	smp_mb();
}

static __init void setup_timer_ce(void)
{
	struct clock_event_device *ce = &timer_ce;

	BUG_ON(smp_processor_id() != boot_cpu_id);

	ce->name     = "timer_ce";
	ce->rating   = 100;
	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	ce->set_mode = timer_ce_set_mode;
	ce->cpumask  = cpu_possible_mask;
	ce->shift    = 32;
	ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                      ce->shift);
	clockevents_register_device(ce);
}

static unsigned int sbus_cycles_offset(void)
{
	u32 val, offset;

	val = sbus_readl(master_l10_counter);
	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;

	/* Limit hit? */
	if (val & TIMER_LIMIT_BIT)
		offset += sparc_config.cs_period;

	return offset;
}

static cycle_t timer_cs_read(struct clocksource *cs)
{
	unsigned int seq, offset;
	u64 cycles;

	do {
		seq = read_seqbegin(&timer_cs_lock);

		cycles = timer_cs_internal_counter;
		offset = sparc_config.get_cycles_offset();
	} while (read_seqretry(&timer_cs_lock, seq));

	/* Count absolute cycles */
	cycles *= sparc_config.cs_period;
	cycles += offset;

	return cycles;
}

static struct clocksource timer_cs = {
	.name	= "timer_cs",
	.rating	= 100,
	.read	= timer_cs_read,
	.mask	= CLOCKSOURCE_MASK(64),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static __init int setup_timer_cs(void)
{
	timer_cs_enabled = 1;
	return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
}

#ifdef CONFIG_SMP
static void percpu_ce_setup(enum clock_event_mode mode,
			struct clock_event_device *evt)
{
	int cpu = cpumask_first(evt->cpumask);

	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
			sparc_config.load_profile_irq(cpu,
						      SBUS_CLOCK_RATE / HZ);
			break;
		case CLOCK_EVT_MODE_ONESHOT:
		case CLOCK_EVT_MODE_SHUTDOWN:
		case CLOCK_EVT_MODE_UNUSED:
			sparc_config.load_profile_irq(cpu, 0);
			break;
		default:
			break;
	}
}

static int percpu_ce_set_next_event(unsigned long delta,
				    struct clock_event_device *evt)
{
	int cpu = cpumask_first(evt->cpumask);
	unsigned int next = (unsigned int)delta;

	sparc_config.load_profile_irq(cpu, next);
	return 0;
}

void register_percpu_ce(int cpu)
{
	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;

	if (sparc_config.features & FEAT_L14_ONESHOT)
		features |= CLOCK_EVT_FEAT_ONESHOT;

	ce->name           = "percpu_ce";
	ce->rating         = 200;
	ce->features       = features;
	ce->set_mode       = percpu_ce_setup;
	ce->set_next_event = percpu_ce_set_next_event;
	ce->cpumask        = cpumask_of(cpu);
	ce->shift          = 32;
	ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                            ce->shift);
	ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
	ce->min_delta_ns   = clockevent_delta2ns(100, ce);

	clockevents_register_device(ce);
}
#endif

static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	return readb(pdata->ioaddr + ofs);
}

static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	writeb(val, pdata->ioaddr + ofs);
}

static struct m48t59_plat_data m48t59_data = {
	.read_byte = mostek_read_byte,
	.write_byte = mostek_write_byte,
};

/* resource is set at runtime */
static struct platform_device m48t59_rtc = {
	.name		= "rtc-m48t59",
	.id		= 0,
	.num_resources	= 1,
	.dev	= {
		.platform_data = &m48t59_data,
	},
};

static int clock_probe(struct platform_device *op)
{
	struct device_node *dp = op->dev.of_node;
	const char *model = of_get_property(dp, "model", NULL);

	if (!model)
		return -ENODEV;

	/* Only the primary RTC has an address property */
	if (!of_find_property(dp, "address", NULL))
		return -ENODEV;

	m48t59_rtc.resource = &op->resource[0];
	if (!strcmp(model, "mk48t02")) {
		/* Map the clock register io area read-only */
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						2048, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T02;
	} else if (!strcmp(model, "mk48t08")) {
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						8192, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T08;
	} else
		return -ENODEV;

	if (platform_device_register(&m48t59_rtc) < 0)
		printk(KERN_ERR "Registering RTC device failed\n");

	return 0;
}

static struct of_device_id clock_match[] = {
	{
		.name = "eeprom",
	},
	{},
};

static struct platform_driver clock_driver = {
	.probe		= clock_probe,
	.driver = {
		.name = "rtc",
		.of_match_table = clock_match,
	},
};


/* Probe for the mostek real time clock chip. */
static int __init clock_init(void)
{
	return platform_driver_register(&clock_driver);
}
/* Must be after subsys_initcall() so that busses are probed.  Must
 * be before device_initcall() because things like the RTC driver
 * need to see the clock registers.
 */
fs_initcall(clock_init);

static void __init sparc32_late_time_init(void)
{
	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
		setup_timer_ce();
	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
		setup_timer_cs();
#ifdef CONFIG_SMP
	register_percpu_ce(smp_processor_id());
#endif
}

static void __init sbus_time_init(void)
{
	sparc_config.get_cycles_offset = sbus_cycles_offset;
	sparc_config.init_timers();
}

void __init time_init(void)
{
	sparc_config.features = 0;
	late_time_init = sparc32_late_time_init;

	if (pcic_present())
		pci_time_init();
	else
		sbus_time_init();
}
Commit	Line	Data
64d329ee	1	/* linux/arch/sparc/kernel/time.c
1da177e4	2	*
64d329ee	3	* Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
	5	*
	6	* Chris Davis (cdavis@cois.on.ca) 03/27/1998
	7	* Added support for the intersil on the sun4/4200
	8	*
	9	* Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
	10	* Support for MicroSPARC-IIep, PCI CPU.
	11	*
	12	* This file handles the Sparc specific time handling details.
	13	*
	14	* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
	15	* "A Kernel Model for Precision Timekeeping" by Dave Mills
	16	*/
1da177e4 LT	17	#include <linux/errno.h>
	18	#include <linux/module.h>
	19	#include <linux/sched.h>
	20	#include <linux/kernel.h>
	21	#include <linux/param.h>
	22	#include <linux/string.h>
	23	#include <linux/mm.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/time.h>
c4cbe6f9	26	#include <linux/rtc/m48t59.h>
1da177e4	27	#include <linux/timex.h>
62f08283 TK	28	#include <linux/clocksource.h>
62f08283 TK	29	#include <linux/clockchips.h>
1da177e4 LT	30	#include <linux/init.h>
	31	#include <linux/pci.h>
	32	#include <linux/ioport.h>
	33	#include <linux/profile.h>
454eeb2d	34	#include <linux/of.h>
764f2579	35	#include <linux/of_device.h>
c4cbe6f9	36	#include <linux/platform_device.h>
1da177e4	37
fcea8b27	38	#include <asm/mc146818rtc.h>
1da177e4	39	#include <asm/oplib.h>
0299b137	40	#include <asm/timex.h>
1da177e4	41	#include <asm/timer.h>
1da177e4 LT	42	#include <asm/irq.h>
	43	#include <asm/io.h>
	44	#include <asm/idprom.h>
1da177e4 LT	45	#include <asm/page.h>
1da177e4 LT	46	#include <asm/pcic.h>
0d84438d	47	#include <asm/irq_regs.h>
62f08283	48	#include <asm/setup.h>
1da177e4	49
fcea8b27	50	#include "kernel.h"
32231a66 AV	51	#include "irq.h"
32231a66 AV	52
62f08283 TK	53	static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
	54	static __volatile__ u64 timer_cs_internal_counter = 0;
	55	static char timer_cs_enabled = 0;
	56
	57	static struct clock_event_device timer_ce;
	58	static char timer_ce_enabled = 0;
	59
	60	#ifdef CONFIG_SMP
	61	DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
	62	#endif
	63
1da177e4	64	DEFINE_SPINLOCK(rtc_lock);
6943f3da SR	65	EXPORT_SYMBOL(rtc_lock);
6943f3da SR	66
1da177e4 LT	67	unsigned long profile_pc(struct pt_regs *regs)
	68	{
	69	extern char __copy_user_begin[], __copy_user_end[];
1da177e4	70	extern char __bzero_begin[], __bzero_end[];
1da177e4 LT	71
	72	unsigned long pc = regs->pc;
	73
	74	if (in_lock_functions(pc) \|\|
	75	(pc >= (unsigned long) __copy_user_begin &&
	76	pc < (unsigned long) __copy_user_end) \|\|
1da177e4	77	(pc >= (unsigned long) __bzero_begin &&
8a8b836b	78	pc < (unsigned long) __bzero_end))
1da177e4 LT	79	pc = regs->u_regs[UREG_RETPC];
	80	return pc;
	81	}
	82
9550e59c MH	83	EXPORT_SYMBOL(profile_pc);
9550e59c MH	84
fcea8b27	85	volatile u32 __iomem *master_l10_counter;
1da177e4	86
62f08283 TK	87	irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
	88	{
	89	if (timer_cs_enabled) {
	90	write_seqlock(&timer_cs_lock);
	91	timer_cs_internal_counter++;
08c9388f	92	sparc_config.clear_clock_irq();
62f08283 TK	93	write_sequnlock(&timer_cs_lock);
62f08283 TK	94	} else {
08c9388f	95	sparc_config.clear_clock_irq();
62f08283	96	}
1da177e4	97
62f08283 TK	98	if (timer_ce_enabled)
62f08283 TK	99	timer_ce.event_handler(&timer_ce);
1da177e4	100
62f08283 TK	101	return IRQ_HANDLED;
	102	}
	103
	104	static void timer_ce_set_mode(enum clock_event_mode mode,
	105	struct clock_event_device *evt)
1da177e4	106	{
62f08283 TK	107	switch (mode) {
	108	case CLOCK_EVT_MODE_PERIODIC:
	109	case CLOCK_EVT_MODE_RESUME:
	110	timer_ce_enabled = 1;
	111	break;
	112	case CLOCK_EVT_MODE_SHUTDOWN:
	113	timer_ce_enabled = 0;
	114	break;
	115	default:
	116	break;
	117	}
	118	smp_mb();
	119	}
	120
	121	static __init void setup_timer_ce(void)
	122	{
	123	struct clock_event_device *ce = &timer_ce;
	124
	125	BUG_ON(smp_processor_id() != boot_cpu_id);
	126
	127	ce->name = "timer_ce";
	128	ce->rating = 100;
	129	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	130	ce->set_mode = timer_ce_set_mode;
	131	ce->cpumask = cpu_possible_mask;
	132	ce->shift = 32;
	133	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	134	ce->shift);
	135	clockevents_register_device(ce);
	136	}
1da177e4	137
62f08283 TK	138	static unsigned int sbus_cycles_offset(void)
62f08283 TK	139	{
fcea8b27	140	u32 val, offset;
1da177e4	141
fcea8b27	142	val = sbus_readl(master_l10_counter);
62f08283	143	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
1da177e4	144
62f08283 TK	145	/* Limit hit? */
	146	if (val & TIMER_LIMIT_BIT)
	147	offset += sparc_config.cs_period;
	148
	149	return offset;
1da177e4 LT	150	}
1da177e4 LT	151
62f08283 TK	152	static cycle_t timer_cs_read(struct clocksource *cs)
	153	{
	154	unsigned int seq, offset;
	155	u64 cycles;
	156
	157	do {
	158	seq = read_seqbegin(&timer_cs_lock);
	159
	160	cycles = timer_cs_internal_counter;
	161	offset = sparc_config.get_cycles_offset();
	162	} while (read_seqretry(&timer_cs_lock, seq));
	163
	164	/* Count absolute cycles */
	165	cycles *= sparc_config.cs_period;
	166	cycles += offset;
	167
	168	return cycles;
	169	}
	170
	171	static struct clocksource timer_cs = {
	172	.name = "timer_cs",
	173	.rating = 100,
	174	.read = timer_cs_read,
	175	.mask = CLOCKSOURCE_MASK(64),
62f08283 TK	176	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	177	};
	178
	179	static __init int setup_timer_cs(void)
	180	{
	181	timer_cs_enabled = 1;
3142f760	182	return clocksource_register_hz(&timer_cs, sparc_config.clock_rate);
62f08283 TK	183	}
	184
	185	#ifdef CONFIG_SMP
	186	static void percpu_ce_setup(enum clock_event_mode mode,
	187	struct clock_event_device *evt)
	188	{
e4afa120	189	int cpu = cpumask_first(evt->cpumask);
62f08283 TK	190
	191	switch (mode) {
	192	case CLOCK_EVT_MODE_PERIODIC:
08c9388f SR	193	sparc_config.load_profile_irq(cpu,
08c9388f SR	194	SBUS_CLOCK_RATE / HZ);
62f08283 TK	195	break;
	196	case CLOCK_EVT_MODE_ONESHOT:
	197	case CLOCK_EVT_MODE_SHUTDOWN:
	198	case CLOCK_EVT_MODE_UNUSED:
08c9388f	199	sparc_config.load_profile_irq(cpu, 0);
62f08283 TK	200	break;
	201	default:
	202	break;
	203	}
	204	}
	205
	206	static int percpu_ce_set_next_event(unsigned long delta,
	207	struct clock_event_device *evt)
	208	{
e4afa120	209	int cpu = cpumask_first(evt->cpumask);
62f08283 TK	210	unsigned int next = (unsigned int)delta;
62f08283 TK	211
08c9388f	212	sparc_config.load_profile_irq(cpu, next);
62f08283 TK	213	return 0;
	214	}
	215
	216	void register_percpu_ce(int cpu)
	217	{
	218	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
	219	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
	220
	221	if (sparc_config.features & FEAT_L14_ONESHOT)
	222	features \|= CLOCK_EVT_FEAT_ONESHOT;
	223
	224	ce->name = "percpu_ce";
	225	ce->rating = 200;
	226	ce->features = features;
	227	ce->set_mode = percpu_ce_setup;
	228	ce->set_next_event = percpu_ce_set_next_event;
	229	ce->cpumask = cpumask_of(cpu);
	230	ce->shift = 32;
	231	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	232	ce->shift);
	233	ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
	234	ce->min_delta_ns = clockevent_delta2ns(100, ce);
	235
	236	clockevents_register_device(ce);
	237	}
	238	#endif
	239
c4cbe6f9	240	static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4	241	{
c4cbe6f9 DM	242	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	243	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	244
12a9ee3c KH	245	return readb(pdata->ioaddr + ofs);
1da177e4 LT	246	}
1da177e4 LT	247
c4cbe6f9	248	static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4	249	{
c4cbe6f9 DM	250	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	251	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	252
12a9ee3c KH	253	writeb(val, pdata->ioaddr + ofs);
1da177e4 LT	254	}
1da177e4 LT	255
c4cbe6f9 DM	256	static struct m48t59_plat_data m48t59_data = {
	257	.read_byte = mostek_read_byte,
	258	.write_byte = mostek_write_byte,
	259	};
	260
	261	/* resource is set at runtime */
	262	static struct platform_device m48t59_rtc = {
	263	.name = "rtc-m48t59",
	264	.id = 0,
	265	.num_resources = 1,
	266	.dev = {
	267	.platform_data = &m48t59_data,
	268	},
	269	};
96ba989d	270
7c9503b8	271	static int clock_probe(struct platform_device *op)
1da177e4	272	{
61c7a080	273	struct device_node *dp = op->dev.of_node;
8271f042	274	const char *model = of_get_property(dp, "model", NULL);
1da177e4	275
ee5caf0e DM	276	if (!model)
ee5caf0e DM	277	return -ENODEV;
1da177e4	278
1c833bc3 KO	279	/* Only the primary RTC has an address property */
	280	if (!of_find_property(dp, "address", NULL))
	281	return -ENODEV;
	282
c4cbe6f9	283	m48t59_rtc.resource = &op->resource[0];
ee5caf0e	284	if (!strcmp(model, "mk48t02")) {
1da177e4	285	/* Map the clock register io area read-only */
c4cbe6f9 DM	286	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	287	2048, "rtc-m48t59");
	288	m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e	289	} else if (!strcmp(model, "mk48t08")) {
c4cbe6f9 DM	290	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	291	8192, "rtc-m48t59");
	292	m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e DM	293	} else
ee5caf0e DM	294	return -ENODEV;
1da177e4	295
c4cbe6f9 DM	296	if (platform_device_register(&m48t59_rtc) < 0)
c4cbe6f9 DM	297	printk(KERN_ERR "Registering RTC device failed\n");
96ba989d	298
ee5caf0e DM	299	return 0;
	300	}
	301
505d9147	302	static struct of_device_id clock_match[] = {
ee5caf0e DM	303	{
	304	.name = "eeprom",
	305	},
	306	{},
	307	};
	308
4ebb24f7	309	static struct platform_driver clock_driver = {
ee5caf0e	310	.probe = clock_probe,
4018294b GL	311	.driver = {
4018294b GL	312	.name = "rtc",
4018294b	313	.of_match_table = clock_match,
a2cd1558	314	},
ee5caf0e DM	315	};
	316
	317
	318	/* Probe for the mostek real time clock chip. */
96ba989d	319	static int __init clock_init(void)
ee5caf0e	320	{
4ebb24f7	321	return platform_driver_register(&clock_driver);
1da177e4	322	}
96ba989d BB	323	/* Must be after subsys_initcall() so that busses are probed. Must
	324	* be before device_initcall() because things like the RTC driver
	325	* need to see the clock registers.
	326	*/
	327	fs_initcall(clock_init);
96ba989d	328
62f08283	329	static void __init sparc32_late_time_init(void)
1da177e4	330	{
62f08283 TK	331	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
	332	setup_timer_ce();
	333	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
	334	setup_timer_cs();
	335	#ifdef CONFIG_SMP
	336	register_percpu_ce(smp_processor_id());
	337	#endif
1da177e4 LT	338	}
1da177e4 LT	339
62f08283	340	static void __init sbus_time_init(void)
1da177e4	341	{
62f08283 TK	342	sparc_config.get_cycles_offset = sbus_cycles_offset;
62f08283 TK	343	sparc_config.init_timers();
1da177e4 LT	344	}
1da177e4 LT	345
62f08283	346	void __init time_init(void)
1da177e4	347	{
62f08283 TK	348	sparc_config.features = 0;
62f08283 TK	349	late_time_init = sparc32_late_time_init;
1da177e4	350
06010fb5	351	if (pcic_present())
0299b137	352	pci_time_init();
06010fb5 SR	353	else
06010fb5 SR	354	sbus_time_init();
1da177e4 LT	355	}
1da177e4 LT	356