sparc32: rename sparc_irq_config to sparc_config
[deliverable/linux.git] / arch / sparc / kernel / time_32.c
CommitLineData
64d329ee 1/* linux/arch/sparc/kernel/time.c
1da177e4 2 *
64d329ee 3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4
LT
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 *
6 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
7 * Added support for the intersil on the sun4/4200
8 *
9 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
10 * Support for MicroSPARC-IIep, PCI CPU.
11 *
12 * This file handles the Sparc specific time handling details.
13 *
14 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
15 * "A Kernel Model for Precision Timekeeping" by Dave Mills
16 */
1da177e4
LT
17#include <linux/errno.h>
18#include <linux/module.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/string.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
c4cbe6f9
DM
26#include <linux/rtc.h>
27#include <linux/rtc/m48t59.h>
1da177e4
LT
28#include <linux/timex.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/ioport.h>
32#include <linux/profile.h>
454eeb2d 33#include <linux/of.h>
764f2579 34#include <linux/of_device.h>
c4cbe6f9 35#include <linux/platform_device.h>
1da177e4
LT
36
37#include <asm/oplib.h>
0299b137 38#include <asm/timex.h>
1da177e4 39#include <asm/timer.h>
1da177e4
LT
40#include <asm/irq.h>
41#include <asm/io.h>
42#include <asm/idprom.h>
43#include <asm/machines.h>
1da177e4
LT
44#include <asm/page.h>
45#include <asm/pcic.h>
0d84438d 46#include <asm/irq_regs.h>
1da177e4 47
32231a66
AV
48#include "irq.h"
49
1da177e4 50DEFINE_SPINLOCK(rtc_lock);
6943f3da
SR
51EXPORT_SYMBOL(rtc_lock);
52
1da177e4 53static int set_rtc_mmss(unsigned long);
1da177e4 54
1da177e4
LT
55unsigned long profile_pc(struct pt_regs *regs)
56{
57 extern char __copy_user_begin[], __copy_user_end[];
58 extern char __atomic_begin[], __atomic_end[];
59 extern char __bzero_begin[], __bzero_end[];
1da177e4
LT
60
61 unsigned long pc = regs->pc;
62
63 if (in_lock_functions(pc) ||
64 (pc >= (unsigned long) __copy_user_begin &&
65 pc < (unsigned long) __copy_user_end) ||
66 (pc >= (unsigned long) __atomic_begin &&
67 pc < (unsigned long) __atomic_end) ||
68 (pc >= (unsigned long) __bzero_begin &&
8a8b836b 69 pc < (unsigned long) __bzero_end))
1da177e4
LT
70 pc = regs->u_regs[UREG_RETPC];
71 return pc;
72}
73
9550e59c
MH
74EXPORT_SYMBOL(profile_pc);
75
1da177e4 76__volatile__ unsigned int *master_l10_counter;
1da177e4 77
0299b137
JS
78u32 (*do_arch_gettimeoffset)(void);
79
f5c9c9be
JS
80int update_persistent_clock(struct timespec now)
81{
82 return set_rtc_mmss(now.tv_sec);
83}
84
1da177e4
LT
85/*
86 * timer_interrupt() needs to keep up the real-time clock,
4ea1b725 87 * as well as call the "xtime_update()" routine every clocktick
1da177e4
LT
88 */
89
90#define TICK_SIZE (tick_nsec / 1000)
91
5dc0742b 92static irqreturn_t timer_interrupt(int dummy, void *dev_id)
1da177e4 93{
1da177e4 94#ifndef CONFIG_SMP
0d84438d 95 profile_tick(CPU_PROFILING);
1da177e4
LT
96#endif
97
1da177e4
LT
98 clear_clock_irq();
99
4ea1b725 100 xtime_update(1);
1da177e4 101
aa02cd2d
PZ
102#ifndef CONFIG_SMP
103 update_process_times(user_mode(get_irq_regs()));
104#endif
1da177e4
LT
105 return IRQ_HANDLED;
106}
107
c4cbe6f9 108static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4 109{
c4cbe6f9
DM
110 struct platform_device *pdev = to_platform_device(dev);
111 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c
KH
112
113 return readb(pdata->ioaddr + ofs);
1da177e4
LT
114}
115
c4cbe6f9 116static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4 117{
c4cbe6f9
DM
118 struct platform_device *pdev = to_platform_device(dev);
119 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c
KH
120
121 writeb(val, pdata->ioaddr + ofs);
1da177e4
LT
122}
123
c4cbe6f9
DM
124static struct m48t59_plat_data m48t59_data = {
125 .read_byte = mostek_read_byte,
126 .write_byte = mostek_write_byte,
127};
128
129/* resource is set at runtime */
130static struct platform_device m48t59_rtc = {
131 .name = "rtc-m48t59",
132 .id = 0,
133 .num_resources = 1,
134 .dev = {
135 .platform_data = &m48t59_data,
136 },
137};
96ba989d 138
4ebb24f7 139static int __devinit clock_probe(struct platform_device *op)
1da177e4 140{
61c7a080 141 struct device_node *dp = op->dev.of_node;
8271f042 142 const char *model = of_get_property(dp, "model", NULL);
1da177e4 143
ee5caf0e
DM
144 if (!model)
145 return -ENODEV;
1da177e4 146
1c833bc3
KO
147 /* Only the primary RTC has an address property */
148 if (!of_find_property(dp, "address", NULL))
149 return -ENODEV;
150
c4cbe6f9 151 m48t59_rtc.resource = &op->resource[0];
ee5caf0e 152 if (!strcmp(model, "mk48t02")) {
1da177e4 153 /* Map the clock register io area read-only */
c4cbe6f9
DM
154 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
155 2048, "rtc-m48t59");
156 m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e 157 } else if (!strcmp(model, "mk48t08")) {
c4cbe6f9
DM
158 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
159 8192, "rtc-m48t59");
160 m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e
DM
161 } else
162 return -ENODEV;
1da177e4 163
c4cbe6f9
DM
164 if (platform_device_register(&m48t59_rtc) < 0)
165 printk(KERN_ERR "Registering RTC device failed\n");
96ba989d 166
ee5caf0e
DM
167 return 0;
168}
169
505d9147 170static struct of_device_id clock_match[] = {
ee5caf0e
DM
171 {
172 .name = "eeprom",
173 },
174 {},
175};
176
4ebb24f7 177static struct platform_driver clock_driver = {
ee5caf0e 178 .probe = clock_probe,
4018294b
GL
179 .driver = {
180 .name = "rtc",
181 .owner = THIS_MODULE,
182 .of_match_table = clock_match,
a2cd1558 183 },
ee5caf0e
DM
184};
185
186
187/* Probe for the mostek real time clock chip. */
96ba989d 188static int __init clock_init(void)
ee5caf0e 189{
4ebb24f7 190 return platform_driver_register(&clock_driver);
1da177e4 191}
96ba989d
BB
192/* Must be after subsys_initcall() so that busses are probed. Must
193 * be before device_initcall() because things like the RTC driver
194 * need to see the clock registers.
195 */
196fs_initcall(clock_init);
96ba989d 197
1da177e4 198
0299b137 199u32 sbus_do_gettimeoffset(void)
1da177e4 200{
000775c5
DM
201 unsigned long val = *master_l10_counter;
202 unsigned long usec = (val >> 10) & 0x1fffff;
203
204 /* Limit hit? */
205 if (val & 0x80000000)
206 usec += 1000000 / HZ;
207
0299b137 208 return usec * 1000;
1da177e4
LT
209}
210
1da177e4 211
0299b137 212u32 arch_gettimeoffset(void)
1da177e4 213{
0299b137
JS
214 if (unlikely(!do_arch_gettimeoffset))
215 return 0;
216 return do_arch_gettimeoffset();
1da177e4
LT
217}
218
0299b137 219static void __init sbus_time_init(void)
1da177e4 220{
0299b137 221 do_arch_gettimeoffset = sbus_do_gettimeoffset;
1da177e4 222
0299b137 223 btfixup();
1da177e4 224
472bc4f2 225 sparc_config.init_timers(timer_interrupt);
0299b137 226}
1da177e4 227
0299b137
JS
228void __init time_init(void)
229{
06010fb5 230 if (pcic_present())
0299b137 231 pci_time_init();
06010fb5
SR
232 else
233 sbus_time_init();
1da177e4
LT
234}
235
0299b137 236
c4cbe6f9 237static int set_rtc_mmss(unsigned long secs)
1da177e4 238{
c4cbe6f9 239 struct rtc_device *rtc = rtc_class_open("rtc0");
ab138c03 240 int err = -1;
1da177e4 241
ab138c03
DM
242 if (rtc) {
243 err = rtc_set_mmss(rtc, secs);
244 rtc_class_close(rtc);
245 }
1da177e4 246
ab138c03 247 return err;
1da177e4 248}
This page took 0.551655 seconds and 5 git commands to generate.