[deliverable/linux.git] / arch / sparc / kernel / time_32.c

/* linux/arch/sparc/kernel/time.c
 *
 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
 *
 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
 * Added support for the intersil on the sun4/4200
 *
 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
 * Support for MicroSPARC-IIep, PCI CPU.
 *
 * This file handles the Sparc specific time handling details.
 *
 * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
 *		"A Kernel Model for Precision Timekeeping" by Dave Mills
 */
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/rtc/m48t59.h>
#include <linux/timex.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/profile.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include <asm/oplib.h>
#include <asm/timex.h>
#include <asm/timer.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/idprom.h>
#include <asm/machines.h>
#include <asm/page.h>
#include <asm/pcic.h>
#include <asm/irq_regs.h>
#include <asm/setup.h>

#include "irq.h"

static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
static __volatile__ u64 timer_cs_internal_counter = 0;
static char timer_cs_enabled = 0;

static struct clock_event_device timer_ce;
static char timer_ce_enabled = 0;

#ifdef CONFIG_SMP
DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
#endif

DEFINE_SPINLOCK(rtc_lock);
EXPORT_SYMBOL(rtc_lock);

static int set_rtc_mmss(unsigned long);

unsigned long profile_pc(struct pt_regs *regs)
{
	extern char __copy_user_begin[], __copy_user_end[];
	extern char __atomic_begin[], __atomic_end[];
	extern char __bzero_begin[], __bzero_end[];

	unsigned long pc = regs->pc;

	if (in_lock_functions(pc) ||
	    (pc >= (unsigned long) __copy_user_begin &&
	     pc < (unsigned long) __copy_user_end) ||
	    (pc >= (unsigned long) __atomic_begin &&
	     pc < (unsigned long) __atomic_end) ||
	    (pc >= (unsigned long) __bzero_begin &&
	     pc < (unsigned long) __bzero_end))
		pc = regs->u_regs[UREG_RETPC];
	return pc;
}

EXPORT_SYMBOL(profile_pc);

__volatile__ unsigned int *master_l10_counter;

int update_persistent_clock(struct timespec now)
{
	return set_rtc_mmss(now.tv_sec);
}

irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
{
	if (timer_cs_enabled) {
		write_seqlock(&timer_cs_lock);
		timer_cs_internal_counter++;
		clear_clock_irq();
		write_sequnlock(&timer_cs_lock);
	} else {
		clear_clock_irq();
	}

	if (timer_ce_enabled)
		timer_ce.event_handler(&timer_ce);

	return IRQ_HANDLED;
}

static void timer_ce_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
		case CLOCK_EVT_MODE_RESUME:
			timer_ce_enabled = 1;
			break;
		case CLOCK_EVT_MODE_SHUTDOWN:
			timer_ce_enabled = 0;
			break;
		default:
			break;
	}
	smp_mb();
}

static __init void setup_timer_ce(void)
{
	struct clock_event_device *ce = &timer_ce;

	BUG_ON(smp_processor_id() != boot_cpu_id);

	ce->name     = "timer_ce";
	ce->rating   = 100;
	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	ce->set_mode = timer_ce_set_mode;
	ce->cpumask  = cpu_possible_mask;
	ce->shift    = 32;
	ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                      ce->shift);
	clockevents_register_device(ce);
}

static unsigned int sbus_cycles_offset(void)
{
	unsigned int val, offset;

	val = *master_l10_counter;
	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;

	/* Limit hit? */
	if (val & TIMER_LIMIT_BIT)
		offset += sparc_config.cs_period;

	return offset;
}

static cycle_t timer_cs_read(struct clocksource *cs)
{
	unsigned int seq, offset;
	u64 cycles;

	do {
		seq = read_seqbegin(&timer_cs_lock);

		cycles = timer_cs_internal_counter;
		offset = sparc_config.get_cycles_offset();
	} while (read_seqretry(&timer_cs_lock, seq));

	/* Count absolute cycles */
	cycles *= sparc_config.cs_period;
	cycles += offset;

	return cycles;
}

static struct clocksource timer_cs = {
	.name	= "timer_cs",
	.rating	= 100,
	.read	= timer_cs_read,
	.mask	= CLOCKSOURCE_MASK(64),
	.shift	= 2,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static __init int setup_timer_cs(void)
{
	timer_cs_enabled = 1;
	timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
	                                    timer_cs.shift);

	return clocksource_register(&timer_cs);
}

#ifdef CONFIG_SMP
static void percpu_ce_setup(enum clock_event_mode mode,
			struct clock_event_device *evt)
{
	int cpu = __first_cpu(evt->cpumask);

	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
			load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
			break;
		case CLOCK_EVT_MODE_ONESHOT:
		case CLOCK_EVT_MODE_SHUTDOWN:
		case CLOCK_EVT_MODE_UNUSED:
			load_profile_irq(cpu, 0);
			break;
		default:
			break;
	}
}

static int percpu_ce_set_next_event(unsigned long delta,
				    struct clock_event_device *evt)
{
	int cpu = __first_cpu(evt->cpumask);
	unsigned int next = (unsigned int)delta;

	load_profile_irq(cpu, next);
	return 0;
}

void register_percpu_ce(int cpu)
{
	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;

	if (sparc_config.features & FEAT_L14_ONESHOT)
		features |= CLOCK_EVT_FEAT_ONESHOT;

	ce->name           = "percpu_ce";
	ce->rating         = 200;
	ce->features       = features;
	ce->set_mode       = percpu_ce_setup;
	ce->set_next_event = percpu_ce_set_next_event;
	ce->cpumask        = cpumask_of(cpu);
	ce->shift          = 32;
	ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                            ce->shift);
	ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
	ce->min_delta_ns   = clockevent_delta2ns(100, ce);

	clockevents_register_device(ce);
}
#endif

static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	return readb(pdata->ioaddr + ofs);
}

static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	writeb(val, pdata->ioaddr + ofs);
}

static struct m48t59_plat_data m48t59_data = {
	.read_byte = mostek_read_byte,
	.write_byte = mostek_write_byte,
};

/* resource is set at runtime */
static struct platform_device m48t59_rtc = {
	.name		= "rtc-m48t59",
	.id		= 0,
	.num_resources	= 1,
	.dev	= {
		.platform_data = &m48t59_data,
	},
};

static int __devinit clock_probe(struct platform_device *op)
{
	struct device_node *dp = op->dev.of_node;
	const char *model = of_get_property(dp, "model", NULL);

	if (!model)
		return -ENODEV;

	/* Only the primary RTC has an address property */
	if (!of_find_property(dp, "address", NULL))
		return -ENODEV;

	m48t59_rtc.resource = &op->resource[0];
	if (!strcmp(model, "mk48t02")) {
		/* Map the clock register io area read-only */
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						2048, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T02;
	} else if (!strcmp(model, "mk48t08")) {
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						8192, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T08;
	} else
		return -ENODEV;

	if (platform_device_register(&m48t59_rtc) < 0)
		printk(KERN_ERR "Registering RTC device failed\n");

	return 0;
}

static struct of_device_id clock_match[] = {
	{
		.name = "eeprom",
	},
	{},
};

static struct platform_driver clock_driver = {
	.probe		= clock_probe,
	.driver = {
		.name = "rtc",
		.owner = THIS_MODULE,
		.of_match_table = clock_match,
	},
};


/* Probe for the mostek real time clock chip. */
static int __init clock_init(void)
{
	return platform_driver_register(&clock_driver);
}
/* Must be after subsys_initcall() so that busses are probed.  Must
 * be before device_initcall() because things like the RTC driver
 * need to see the clock registers.
 */
fs_initcall(clock_init);

static void __init sparc32_late_time_init(void)
{
	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
		setup_timer_ce();
	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
		setup_timer_cs();
#ifdef CONFIG_SMP
	register_percpu_ce(smp_processor_id());
#endif
}

static void __init sbus_time_init(void)
{
	sparc_config.get_cycles_offset = sbus_cycles_offset;
	sparc_config.init_timers();
}

void __init time_init(void)
{
	btfixup();

	sparc_config.features = 0;
	late_time_init = sparc32_late_time_init;

	if (pcic_present())
		pci_time_init();
	else
		sbus_time_init();
}


static int set_rtc_mmss(unsigned long secs)
{
	struct rtc_device *rtc = rtc_class_open("rtc0");
	int err = -1;

	if (rtc) {
		err = rtc_set_mmss(rtc, secs);
		rtc_class_close(rtc);
	}

	return err;
}
Commit	Line	Data
64d329ee	1	/* linux/arch/sparc/kernel/time.c
1da177e4	2	*
64d329ee	3	* Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
	5	*
	6	* Chris Davis (cdavis@cois.on.ca) 03/27/1998
	7	* Added support for the intersil on the sun4/4200
	8	*
	9	* Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
	10	* Support for MicroSPARC-IIep, PCI CPU.
	11	*
	12	* This file handles the Sparc specific time handling details.
	13	*
	14	* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
	15	* "A Kernel Model for Precision Timekeeping" by Dave Mills
	16	*/
1da177e4 LT	17	#include <linux/errno.h>
	18	#include <linux/module.h>
	19	#include <linux/sched.h>
	20	#include <linux/kernel.h>
	21	#include <linux/param.h>
	22	#include <linux/string.h>
	23	#include <linux/mm.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/time.h>
c4cbe6f9 DM	26	#include <linux/rtc.h>
c4cbe6f9 DM	27	#include <linux/rtc/m48t59.h>
1da177e4	28	#include <linux/timex.h>
62f08283 TK	29	#include <linux/clocksource.h>
62f08283 TK	30	#include <linux/clockchips.h>
1da177e4 LT	31	#include <linux/init.h>
	32	#include <linux/pci.h>
	33	#include <linux/ioport.h>
	34	#include <linux/profile.h>
454eeb2d	35	#include <linux/of.h>
764f2579	36	#include <linux/of_device.h>
c4cbe6f9	37	#include <linux/platform_device.h>
1da177e4 LT	38
1da177e4 LT	39	#include <asm/oplib.h>
0299b137	40	#include <asm/timex.h>
1da177e4	41	#include <asm/timer.h>
1da177e4 LT	42	#include <asm/irq.h>
	43	#include <asm/io.h>
	44	#include <asm/idprom.h>
	45	#include <asm/machines.h>
1da177e4 LT	46	#include <asm/page.h>
1da177e4 LT	47	#include <asm/pcic.h>
0d84438d	48	#include <asm/irq_regs.h>
62f08283	49	#include <asm/setup.h>
1da177e4	50
32231a66 AV	51	#include "irq.h"
32231a66 AV	52
62f08283 TK	53	static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
	54	static __volatile__ u64 timer_cs_internal_counter = 0;
	55	static char timer_cs_enabled = 0;
	56
	57	static struct clock_event_device timer_ce;
	58	static char timer_ce_enabled = 0;
	59
	60	#ifdef CONFIG_SMP
	61	DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
	62	#endif
	63
1da177e4	64	DEFINE_SPINLOCK(rtc_lock);
6943f3da SR	65	EXPORT_SYMBOL(rtc_lock);
6943f3da SR	66
1da177e4	67	static int set_rtc_mmss(unsigned long);
1da177e4	68
1da177e4 LT	69	unsigned long profile_pc(struct pt_regs *regs)
	70	{
	71	extern char __copy_user_begin[], __copy_user_end[];
	72	extern char __atomic_begin[], __atomic_end[];
	73	extern char __bzero_begin[], __bzero_end[];
1da177e4 LT	74
	75	unsigned long pc = regs->pc;
	76
	77	if (in_lock_functions(pc) \|\|
	78	(pc >= (unsigned long) __copy_user_begin &&
	79	pc < (unsigned long) __copy_user_end) \|\|
	80	(pc >= (unsigned long) __atomic_begin &&
	81	pc < (unsigned long) __atomic_end) \|\|
	82	(pc >= (unsigned long) __bzero_begin &&
8a8b836b	83	pc < (unsigned long) __bzero_end))
1da177e4 LT	84	pc = regs->u_regs[UREG_RETPC];
	85	return pc;
	86	}
	87
9550e59c MH	88	EXPORT_SYMBOL(profile_pc);
9550e59c MH	89
1da177e4	90	__volatile__ unsigned int *master_l10_counter;
1da177e4	91
f5c9c9be JS	92	int update_persistent_clock(struct timespec now)
	93	{
	94	return set_rtc_mmss(now.tv_sec);
	95	}
	96
62f08283 TK	97	irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
	98	{
	99	if (timer_cs_enabled) {
	100	write_seqlock(&timer_cs_lock);
	101	timer_cs_internal_counter++;
	102	clear_clock_irq();
	103	write_sequnlock(&timer_cs_lock);
	104	} else {
	105	clear_clock_irq();
	106	}
1da177e4	107
62f08283 TK	108	if (timer_ce_enabled)
62f08283 TK	109	timer_ce.event_handler(&timer_ce);
1da177e4	110
62f08283 TK	111	return IRQ_HANDLED;
	112	}
	113
	114	static void timer_ce_set_mode(enum clock_event_mode mode,
	115	struct clock_event_device *evt)
1da177e4	116	{
62f08283 TK	117	switch (mode) {
	118	case CLOCK_EVT_MODE_PERIODIC:
	119	case CLOCK_EVT_MODE_RESUME:
	120	timer_ce_enabled = 1;
	121	break;
	122	case CLOCK_EVT_MODE_SHUTDOWN:
	123	timer_ce_enabled = 0;
	124	break;
	125	default:
	126	break;
	127	}
	128	smp_mb();
	129	}
	130
	131	static __init void setup_timer_ce(void)
	132	{
	133	struct clock_event_device *ce = &timer_ce;
	134
	135	BUG_ON(smp_processor_id() != boot_cpu_id);
	136
	137	ce->name = "timer_ce";
	138	ce->rating = 100;
	139	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	140	ce->set_mode = timer_ce_set_mode;
	141	ce->cpumask = cpu_possible_mask;
	142	ce->shift = 32;
	143	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	144	ce->shift);
	145	clockevents_register_device(ce);
	146	}
1da177e4	147
62f08283 TK	148	static unsigned int sbus_cycles_offset(void)
	149	{
	150	unsigned int val, offset;
1da177e4	151
62f08283 TK	152	val = *master_l10_counter;
62f08283 TK	153	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
1da177e4	154
62f08283 TK	155	/* Limit hit? */
	156	if (val & TIMER_LIMIT_BIT)
	157	offset += sparc_config.cs_period;
	158
	159	return offset;
1da177e4 LT	160	}
1da177e4 LT	161
62f08283 TK	162	static cycle_t timer_cs_read(struct clocksource *cs)
	163	{
	164	unsigned int seq, offset;
	165	u64 cycles;
	166
	167	do {
	168	seq = read_seqbegin(&timer_cs_lock);
	169
	170	cycles = timer_cs_internal_counter;
	171	offset = sparc_config.get_cycles_offset();
	172	} while (read_seqretry(&timer_cs_lock, seq));
	173
	174	/* Count absolute cycles */
	175	cycles *= sparc_config.cs_period;
	176	cycles += offset;
	177
	178	return cycles;
	179	}
	180
	181	static struct clocksource timer_cs = {
	182	.name = "timer_cs",
	183	.rating = 100,
	184	.read = timer_cs_read,
	185	.mask = CLOCKSOURCE_MASK(64),
	186	.shift = 2,
	187	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	188	};
	189
	190	static __init int setup_timer_cs(void)
	191	{
	192	timer_cs_enabled = 1;
	193	timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
	194	timer_cs.shift);
	195
	196	return clocksource_register(&timer_cs);
	197	}
	198
	199	#ifdef CONFIG_SMP
	200	static void percpu_ce_setup(enum clock_event_mode mode,
	201	struct clock_event_device *evt)
	202	{
	203	int cpu = __first_cpu(evt->cpumask);
	204
	205	switch (mode) {
	206	case CLOCK_EVT_MODE_PERIODIC:
	207	load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
	208	break;
	209	case CLOCK_EVT_MODE_ONESHOT:
	210	case CLOCK_EVT_MODE_SHUTDOWN:
	211	case CLOCK_EVT_MODE_UNUSED:
	212	load_profile_irq(cpu, 0);
	213	break;
	214	default:
	215	break;
	216	}
	217	}
	218
	219	static int percpu_ce_set_next_event(unsigned long delta,
	220	struct clock_event_device *evt)
	221	{
	222	int cpu = __first_cpu(evt->cpumask);
	223	unsigned int next = (unsigned int)delta;
	224
	225	load_profile_irq(cpu, next);
226	return 0;
227	}
228
229	void register_percpu_ce(int cpu)
230	{
231	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
232	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
233
234	if (sparc_config.features & FEAT_L14_ONESHOT)
235	features \|= CLOCK_EVT_FEAT_ONESHOT;
236
237	ce->name = "percpu_ce";
238	ce->rating = 200;
239	ce->features = features;
240	ce->set_mode = percpu_ce_setup;
241	ce->set_next_event = percpu_ce_set_next_event;
242	ce->cpumask = cpumask_of(cpu);
243	ce->shift = 32;
244	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
245	ce->shift);
246	ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
247	ce->min_delta_ns = clockevent_delta2ns(100, ce);
248
249	clockevents_register_device(ce);
250	}
251	#endif
252
c4cbe6f9	253	static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4	254	{
c4cbe6f9 DM	255	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	256	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	257
12a9ee3c KH	258	return readb(pdata->ioaddr + ofs);
1da177e4 LT	259	}
1da177e4 LT	260
c4cbe6f9	261	static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4	262	{
c4cbe6f9 DM	263	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	264	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	265
12a9ee3c KH	266	writeb(val, pdata->ioaddr + ofs);
1da177e4 LT	267	}
1da177e4 LT	268
c4cbe6f9 DM	269	static struct m48t59_plat_data m48t59_data = {
	270	.read_byte = mostek_read_byte,
	271	.write_byte = mostek_write_byte,
	272	};
	273
	274	/* resource is set at runtime */
	275	static struct platform_device m48t59_rtc = {
	276	.name = "rtc-m48t59",
	277	.id = 0,
	278	.num_resources = 1,
	279	.dev = {
	280	.platform_data = &m48t59_data,
	281	},
	282	};
96ba989d	283
4ebb24f7	284	static int __devinit clock_probe(struct platform_device *op)
1da177e4	285	{
61c7a080	286	struct device_node *dp = op->dev.of_node;
8271f042	287	const char *model = of_get_property(dp, "model", NULL);
1da177e4	288
ee5caf0e DM	289	if (!model)
ee5caf0e DM	290	return -ENODEV;
1da177e4	291
1c833bc3 KO	292	/* Only the primary RTC has an address property */
	293	if (!of_find_property(dp, "address", NULL))
	294	return -ENODEV;
	295
c4cbe6f9	296	m48t59_rtc.resource = &op->resource[0];
ee5caf0e	297	if (!strcmp(model, "mk48t02")) {
1da177e4	298	/* Map the clock register io area read-only */
c4cbe6f9 DM	299	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	300	2048, "rtc-m48t59");
	301	m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e	302	} else if (!strcmp(model, "mk48t08")) {
c4cbe6f9 DM	303	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	304	8192, "rtc-m48t59");
	305	m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e DM	306	} else
ee5caf0e DM	307	return -ENODEV;
1da177e4	308
c4cbe6f9 DM	309	if (platform_device_register(&m48t59_rtc) < 0)
c4cbe6f9 DM	310	printk(KERN_ERR "Registering RTC device failed\n");
96ba989d	311
ee5caf0e DM	312	return 0;
	313	}
	314
505d9147	315	static struct of_device_id clock_match[] = {
ee5caf0e DM	316	{
	317	.name = "eeprom",
	318	},
	319	{},
	320	};
	321
4ebb24f7	322	static struct platform_driver clock_driver = {
ee5caf0e	323	.probe = clock_probe,
4018294b GL	324	.driver = {
	325	.name = "rtc",
	326	.owner = THIS_MODULE,
	327	.of_match_table = clock_match,
a2cd1558	328	},
ee5caf0e DM	329	};
	330
	331
	332	/* Probe for the mostek real time clock chip. */
96ba989d	333	static int __init clock_init(void)
ee5caf0e	334	{
4ebb24f7	335	return platform_driver_register(&clock_driver);
1da177e4	336	}
96ba989d BB	337	/* Must be after subsys_initcall() so that busses are probed. Must
	338	* be before device_initcall() because things like the RTC driver
	339	* need to see the clock registers.
	340	*/
	341	fs_initcall(clock_init);
96ba989d	342
62f08283	343	static void __init sparc32_late_time_init(void)
1da177e4	344	{
62f08283 TK	345	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
	346	setup_timer_ce();
	347	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
	348	setup_timer_cs();
	349	#ifdef CONFIG_SMP
	350	register_percpu_ce(smp_processor_id());
	351	#endif
1da177e4 LT	352	}
1da177e4 LT	353
62f08283	354	static void __init sbus_time_init(void)
1da177e4	355	{
62f08283 TK	356	sparc_config.get_cycles_offset = sbus_cycles_offset;
62f08283 TK	357	sparc_config.init_timers();
1da177e4 LT	358	}
1da177e4 LT	359
62f08283	360	void __init time_init(void)
1da177e4	361	{
0299b137	362	btfixup();
1da177e4	363
62f08283 TK	364	sparc_config.features = 0;
62f08283 TK	365	late_time_init = sparc32_late_time_init;
1da177e4	366
06010fb5	367	if (pcic_present())
0299b137	368	pci_time_init();
06010fb5 SR	369	else
06010fb5 SR	370	sbus_time_init();
1da177e4 LT	371	}
1da177e4 LT	372
0299b137	373
c4cbe6f9	374	static int set_rtc_mmss(unsigned long secs)
1da177e4	375	{
c4cbe6f9	376	struct rtc_device *rtc = rtc_class_open("rtc0");
ab138c03	377	int err = -1;
1da177e4	378
ab138c03 DM	379	if (rtc) {
	380	err = rtc_set_mmss(rtc, secs);
	381	rtc_class_close(rtc);
	382	}
1da177e4	383
ab138c03	384	return err;
1da177e4	385	}