sparc: Add {open_by,name_to}_handle_at and clock_adjtime syscalls.
[deliverable/linux.git] / arch / sparc / kernel / time_32.c
CommitLineData
64d329ee 1/* linux/arch/sparc/kernel/time.c
1da177e4 2 *
64d329ee 3 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4
LT
4 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
5 *
6 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
7 * Added support for the intersil on the sun4/4200
8 *
9 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
10 * Support for MicroSPARC-IIep, PCI CPU.
11 *
12 * This file handles the Sparc specific time handling details.
13 *
14 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
15 * "A Kernel Model for Precision Timekeeping" by Dave Mills
16 */
1da177e4
LT
17#include <linux/errno.h>
18#include <linux/module.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/string.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
c4cbe6f9
DM
26#include <linux/rtc.h>
27#include <linux/rtc/m48t59.h>
1da177e4
LT
28#include <linux/timex.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/ioport.h>
32#include <linux/profile.h>
454eeb2d 33#include <linux/of.h>
764f2579 34#include <linux/of_device.h>
c4cbe6f9 35#include <linux/platform_device.h>
1da177e4
LT
36
37#include <asm/oplib.h>
0299b137 38#include <asm/timex.h>
1da177e4 39#include <asm/timer.h>
1da177e4
LT
40#include <asm/system.h>
41#include <asm/irq.h>
42#include <asm/io.h>
43#include <asm/idprom.h>
44#include <asm/machines.h>
1da177e4
LT
45#include <asm/page.h>
46#include <asm/pcic.h>
0d84438d 47#include <asm/irq_regs.h>
1da177e4 48
32231a66
AV
49#include "irq.h"
50
1da177e4 51DEFINE_SPINLOCK(rtc_lock);
6943f3da
SR
52EXPORT_SYMBOL(rtc_lock);
53
1da177e4 54static int set_rtc_mmss(unsigned long);
1da177e4 55
1da177e4
LT
56unsigned long profile_pc(struct pt_regs *regs)
57{
58 extern char __copy_user_begin[], __copy_user_end[];
59 extern char __atomic_begin[], __atomic_end[];
60 extern char __bzero_begin[], __bzero_end[];
1da177e4
LT
61
62 unsigned long pc = regs->pc;
63
64 if (in_lock_functions(pc) ||
65 (pc >= (unsigned long) __copy_user_begin &&
66 pc < (unsigned long) __copy_user_end) ||
67 (pc >= (unsigned long) __atomic_begin &&
68 pc < (unsigned long) __atomic_end) ||
69 (pc >= (unsigned long) __bzero_begin &&
8a8b836b 70 pc < (unsigned long) __bzero_end))
1da177e4
LT
71 pc = regs->u_regs[UREG_RETPC];
72 return pc;
73}
74
9550e59c
MH
75EXPORT_SYMBOL(profile_pc);
76
1da177e4 77__volatile__ unsigned int *master_l10_counter;
1da177e4 78
0299b137
JS
79u32 (*do_arch_gettimeoffset)(void);
80
f5c9c9be
JS
81int update_persistent_clock(struct timespec now)
82{
83 return set_rtc_mmss(now.tv_sec);
84}
85
1da177e4
LT
86/*
87 * timer_interrupt() needs to keep up the real-time clock,
4ea1b725 88 * as well as call the "xtime_update()" routine every clocktick
1da177e4
LT
89 */
90
91#define TICK_SIZE (tick_nsec / 1000)
92
5dc0742b 93static irqreturn_t timer_interrupt(int dummy, void *dev_id)
1da177e4 94{
1da177e4 95#ifndef CONFIG_SMP
0d84438d 96 profile_tick(CPU_PROFILING);
1da177e4
LT
97#endif
98
1da177e4
LT
99 clear_clock_irq();
100
4ea1b725 101 xtime_update(1);
1da177e4 102
aa02cd2d
PZ
103#ifndef CONFIG_SMP
104 update_process_times(user_mode(get_irq_regs()));
105#endif
1da177e4
LT
106 return IRQ_HANDLED;
107}
108
c4cbe6f9 109static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4 110{
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DM
111 struct platform_device *pdev = to_platform_device(dev);
112 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c
KH
113
114 return readb(pdata->ioaddr + ofs);
1da177e4
LT
115}
116
c4cbe6f9 117static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4 118{
c4cbe6f9
DM
119 struct platform_device *pdev = to_platform_device(dev);
120 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
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KH
121
122 writeb(val, pdata->ioaddr + ofs);
1da177e4
LT
123}
124
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DM
125static struct m48t59_plat_data m48t59_data = {
126 .read_byte = mostek_read_byte,
127 .write_byte = mostek_write_byte,
128};
129
130/* resource is set at runtime */
131static struct platform_device m48t59_rtc = {
132 .name = "rtc-m48t59",
133 .id = 0,
134 .num_resources = 1,
135 .dev = {
136 .platform_data = &m48t59_data,
137 },
138};
96ba989d 139
4ebb24f7 140static int __devinit clock_probe(struct platform_device *op)
1da177e4 141{
61c7a080 142 struct device_node *dp = op->dev.of_node;
8271f042 143 const char *model = of_get_property(dp, "model", NULL);
1da177e4 144
ee5caf0e
DM
145 if (!model)
146 return -ENODEV;
1da177e4 147
c4cbe6f9 148 m48t59_rtc.resource = &op->resource[0];
ee5caf0e 149 if (!strcmp(model, "mk48t02")) {
1da177e4 150 /* Map the clock register io area read-only */
c4cbe6f9
DM
151 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
152 2048, "rtc-m48t59");
153 m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e 154 } else if (!strcmp(model, "mk48t08")) {
c4cbe6f9
DM
155 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
156 8192, "rtc-m48t59");
157 m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e
DM
158 } else
159 return -ENODEV;
1da177e4 160
c4cbe6f9
DM
161 if (platform_device_register(&m48t59_rtc) < 0)
162 printk(KERN_ERR "Registering RTC device failed\n");
96ba989d 163
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DM
164 return 0;
165}
166
fd098316 167static struct of_device_id __initdata clock_match[] = {
ee5caf0e
DM
168 {
169 .name = "eeprom",
170 },
171 {},
172};
173
4ebb24f7 174static struct platform_driver clock_driver = {
ee5caf0e 175 .probe = clock_probe,
4018294b
GL
176 .driver = {
177 .name = "rtc",
178 .owner = THIS_MODULE,
179 .of_match_table = clock_match,
a2cd1558 180 },
ee5caf0e
DM
181};
182
183
184/* Probe for the mostek real time clock chip. */
96ba989d 185static int __init clock_init(void)
ee5caf0e 186{
4ebb24f7 187 return platform_driver_register(&clock_driver);
1da177e4 188}
96ba989d
BB
189/* Must be after subsys_initcall() so that busses are probed. Must
190 * be before device_initcall() because things like the RTC driver
191 * need to see the clock registers.
192 */
193fs_initcall(clock_init);
96ba989d 194
1da177e4 195
0299b137 196u32 sbus_do_gettimeoffset(void)
1da177e4 197{
000775c5
DM
198 unsigned long val = *master_l10_counter;
199 unsigned long usec = (val >> 10) & 0x1fffff;
200
201 /* Limit hit? */
202 if (val & 0x80000000)
203 usec += 1000000 / HZ;
204
0299b137 205 return usec * 1000;
1da177e4
LT
206}
207
1da177e4 208
0299b137 209u32 arch_gettimeoffset(void)
1da177e4 210{
0299b137
JS
211 if (unlikely(!do_arch_gettimeoffset))
212 return 0;
213 return do_arch_gettimeoffset();
1da177e4
LT
214}
215
0299b137 216static void __init sbus_time_init(void)
1da177e4 217{
0299b137 218 do_arch_gettimeoffset = sbus_do_gettimeoffset;
1da177e4 219
0299b137 220 btfixup();
1da177e4 221
bbdc2661 222 sparc_irq_config.init_timers(timer_interrupt);
0299b137 223}
1da177e4 224
0299b137
JS
225void __init time_init(void)
226{
227#ifdef CONFIG_PCI
228 extern void pci_time_init(void);
229 if (pcic_present()) {
230 pci_time_init();
231 return;
232 }
233#endif
234 sbus_time_init();
1da177e4
LT
235}
236
0299b137 237
c4cbe6f9 238static int set_rtc_mmss(unsigned long secs)
1da177e4 239{
c4cbe6f9 240 struct rtc_device *rtc = rtc_class_open("rtc0");
ab138c03 241 int err = -1;
1da177e4 242
ab138c03
DM
243 if (rtc) {
244 err = rtc_set_mmss(rtc, secs);
245 rtc_class_close(rtc);
246 }
1da177e4 247
ab138c03 248 return err;
1da177e4 249}
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