[deliverable/linux.git] / arch / sparc / kernel / unaligned_64.c

/*
 * unaligned.c: Unaligned load/store trap handling with special
 *              cases for the kernel to do them more quickly.
 *
 * Copyright (C) 1996,2008 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */


#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <asm/asi.h>
#include <asm/ptrace.h>
#include <asm/pstate.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <linux/smp.h>
#include <linux/bitops.h>
#include <linux/perf_event.h>
#include <linux/ratelimit.h>
#include <linux/context_tracking.h>
#include <asm/fpumacro.h>
#include <asm/cacheflush.h>
#include <asm/setup.h>

#include "entry.h"
#include "kernel.h"

enum direction {
	load,    /* ld, ldd, ldh, ldsh */
	store,   /* st, std, sth, stsh */
	both,    /* Swap, ldstub, cas, ... */
	fpld,
	fpst,
	invalid,
};

static inline enum direction decode_direction(unsigned int insn)
{
	unsigned long tmp = (insn >> 21) & 1;

	if (!tmp)
		return load;
	else {
		switch ((insn>>19)&0xf) {
		case 15: /* swap* */
			return both;
		default:
			return store;
		}
	}
}

/* 16 = double-word, 8 = extra-word, 4 = word, 2 = half-word */
static inline int decode_access_size(struct pt_regs *regs, unsigned int insn)
{
	unsigned int tmp;

	tmp = ((insn >> 19) & 0xf);
	if (tmp == 11 || tmp == 14) /* ldx/stx */
		return 8;
	tmp &= 3;
	if (!tmp)
		return 4;
	else if (tmp == 3)
		return 16;	/* ldd/std - Although it is actually 8 */
	else if (tmp == 2)
		return 2;
	else {
		printk("Impossible unaligned trap. insn=%08x\n", insn);
		die_if_kernel("Byte sized unaligned access?!?!", regs);

		/* GCC should never warn that control reaches the end
		 * of this function without returning a value because
		 * die_if_kernel() is marked with attribute 'noreturn'.
		 * Alas, some versions do...
		 */

		return 0;
	}
}

static inline int decode_asi(unsigned int insn, struct pt_regs *regs)
{
	if (insn & 0x800000) {
		if (insn & 0x2000)
			return (unsigned char)(regs->tstate >> 24);	/* %asi */
		else
			return (unsigned char)(insn >> 5);		/* imm_asi */
	} else
		return ASI_P;
}

/* 0x400000 = signed, 0 = unsigned */
static inline int decode_signedness(unsigned int insn)
{
	return (insn & 0x400000);
}

static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
				       unsigned int rd, int from_kernel)
{
	if (rs2 >= 16 || rs1 >= 16 || rd >= 16) {
		if (from_kernel != 0)
			__asm__ __volatile__("flushw");
		else
			flushw_user();
	}
}

static inline long sign_extend_imm13(long imm)
{
	return imm << 51 >> 51;
}

static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
{
	unsigned long value, fp;
	
	if (reg < 16)
		return (!reg ? 0 : regs->u_regs[reg]);

	fp = regs->u_regs[UREG_FP];

	if (regs->tstate & TSTATE_PRIV) {
		struct reg_window *win;
		win = (struct reg_window *)(fp + STACK_BIAS);
		value = win->locals[reg - 16];
	} else if (!test_thread_64bit_stack(fp)) {
		struct reg_window32 __user *win32;
		win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
		get_user(value, &win32->locals[reg - 16]);
	} else {
		struct reg_window __user *win;
		win = (struct reg_window __user *)(fp + STACK_BIAS);
		get_user(value, &win->locals[reg - 16]);
	}
	return value;
}

static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs)
{
	unsigned long fp;

	if (reg < 16)
		return &regs->u_regs[reg];

	fp = regs->u_regs[UREG_FP];

	if (regs->tstate & TSTATE_PRIV) {
		struct reg_window *win;
		win = (struct reg_window *)(fp + STACK_BIAS);
		return &win->locals[reg - 16];
	} else if (!test_thread_64bit_stack(fp)) {
		struct reg_window32 *win32;
		win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
		return (unsigned long *)&win32->locals[reg - 16];
	} else {
		struct reg_window *win;
		win = (struct reg_window *)(fp + STACK_BIAS);
		return &win->locals[reg - 16];
	}
}

unsigned long compute_effective_address(struct pt_regs *regs,
					unsigned int insn, unsigned int rd)
{
	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	unsigned int rs1 = (insn >> 14) & 0x1f;
	unsigned int rs2 = insn & 0x1f;
	unsigned long addr;

	if (insn & 0x2000) {
		maybe_flush_windows(rs1, 0, rd, from_kernel);
		addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn));
	} else {
		maybe_flush_windows(rs1, rs2, rd, from_kernel);
		addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));
	}

	if (!from_kernel && test_thread_flag(TIF_32BIT))
		addr &= 0xffffffff;

	return addr;
}

/* This is just to make gcc think die_if_kernel does return... */
static void __used unaligned_panic(char *str, struct pt_regs *regs)
{
	die_if_kernel(str, regs);
}

extern int do_int_load(unsigned long *dest_reg, int size,
		       unsigned long *saddr, int is_signed, int asi);
	
extern int __do_int_store(unsigned long *dst_addr, int size,
			  unsigned long src_val, int asi);

static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
			       struct pt_regs *regs, int asi, int orig_asi)
{
	unsigned long zero = 0;
	unsigned long *src_val_p = &zero;
	unsigned long src_val;

	if (size == 16) {
		size = 8;
		zero = (((long)(reg_num ?
		        (unsigned)fetch_reg(reg_num, regs) : 0)) << 32) |
			(unsigned)fetch_reg(reg_num + 1, regs);
	} else if (reg_num) {
		src_val_p = fetch_reg_addr(reg_num, regs);
	}
	src_val = *src_val_p;
	if (unlikely(asi != orig_asi)) {
		switch (size) {
		case 2:
			src_val = swab16(src_val);
			break;
		case 4:
			src_val = swab32(src_val);
			break;
		case 8:
			src_val = swab64(src_val);
			break;
		case 16:
		default:
			BUG();
			break;
		}
	}
	return __do_int_store(dst_addr, size, src_val, asi);
}

static inline void advance(struct pt_regs *regs)
{
	regs->tpc   = regs->tnpc;
	regs->tnpc += 4;
	if (test_thread_flag(TIF_32BIT)) {
		regs->tpc &= 0xffffffff;
		regs->tnpc &= 0xffffffff;
	}
}

static inline int floating_point_load_or_store_p(unsigned int insn)
{
	return (insn >> 24) & 1;
}

static inline int ok_for_kernel(unsigned int insn)
{
	return !floating_point_load_or_store_p(insn);
}

static void kernel_mna_trap_fault(int fixup_tstate_asi)
{
	struct pt_regs *regs = current_thread_info()->kern_una_regs;
	unsigned int insn = current_thread_info()->kern_una_insn;
	const struct exception_table_entry *entry;

	entry = search_exception_tables(regs->tpc);
	if (!entry) {
		unsigned long address;

		address = compute_effective_address(regs, insn,
						    ((insn >> 25) & 0x1f));
        	if (address < PAGE_SIZE) {
                	printk(KERN_ALERT "Unable to handle kernel NULL "
			       "pointer dereference in mna handler");
        	} else
                	printk(KERN_ALERT "Unable to handle kernel paging "
			       "request in mna handler");
	        printk(KERN_ALERT " at virtual address %016lx\n",address);
		printk(KERN_ALERT "current->{active_,}mm->context = %016lx\n",
			(current->mm ? CTX_HWBITS(current->mm->context) :
			CTX_HWBITS(current->active_mm->context)));
		printk(KERN_ALERT "current->{active_,}mm->pgd = %016lx\n",
			(current->mm ? (unsigned long) current->mm->pgd :
			(unsigned long) current->active_mm->pgd));
	        die_if_kernel("Oops", regs);
		/* Not reached */
	}
	regs->tpc = entry->fixup;
	regs->tnpc = regs->tpc + 4;

	if (fixup_tstate_asi) {
		regs->tstate &= ~TSTATE_ASI;
		regs->tstate |= (ASI_AIUS << 24UL);
	}
}

static void log_unaligned(struct pt_regs *regs)
{
	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);

	if (__ratelimit(&ratelimit)) {
		printk("Kernel unaligned access at TPC[%lx] %pS\n",
		       regs->tpc, (void *) regs->tpc);
	}
}

asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
{
	enum direction dir = decode_direction(insn);
	int size = decode_access_size(regs, insn);
	int orig_asi, asi;

	current_thread_info()->kern_una_regs = regs;
	current_thread_info()->kern_una_insn = insn;

	orig_asi = asi = decode_asi(insn, regs);

	/* If this is a {get,put}_user() on an unaligned userspace pointer,
	 * just signal a fault and do not log the event.
	 */
	if (asi == ASI_AIUS) {
		kernel_mna_trap_fault(0);
		return;
	}

	log_unaligned(regs);

	if (!ok_for_kernel(insn) || dir == both) {
		printk("Unsupported unaligned load/store trap for kernel "
		       "at <%016lx>.\n", regs->tpc);
		unaligned_panic("Kernel does fpu/atomic "
				"unaligned load/store.", regs);

		kernel_mna_trap_fault(0);
	} else {
		unsigned long addr, *reg_addr;
		int err;

		addr = compute_effective_address(regs, insn,
						 ((insn >> 25) & 0x1f));
		perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
		switch (asi) {
		case ASI_NL:
		case ASI_AIUPL:
		case ASI_AIUSL:
		case ASI_PL:
		case ASI_SL:
		case ASI_PNFL:
		case ASI_SNFL:
			asi &= ~0x08;
			break;
		}
		switch (dir) {
		case load:
			reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
			err = do_int_load(reg_addr, size,
					  (unsigned long *) addr,
					  decode_signedness(insn), asi);
			if (likely(!err) && unlikely(asi != orig_asi)) {
				unsigned long val_in = *reg_addr;
				switch (size) {
				case 2:
					val_in = swab16(val_in);
					break;
				case 4:
					val_in = swab32(val_in);
					break;
				case 8:
					val_in = swab64(val_in);
					break;
				case 16:
				default:
					BUG();
					break;
				}
				*reg_addr = val_in;
			}
			break;

		case store:
			err = do_int_store(((insn>>25)&0x1f), size,
					   (unsigned long *) addr, regs,
					   asi, orig_asi);
			break;

		default:
			panic("Impossible kernel unaligned trap.");
			/* Not reached... */
		}
		if (unlikely(err))
			kernel_mna_trap_fault(1);
		else
			advance(regs);
	}
}

int handle_popc(u32 insn, struct pt_regs *regs)
{
	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	int ret, rd = ((insn >> 25) & 0x1f);
	u64 value;
	                        
	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
	if (insn & 0x2000) {
		maybe_flush_windows(0, 0, rd, from_kernel);
		value = sign_extend_imm13(insn);
	} else {
		maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
		value = fetch_reg(insn & 0x1f, regs);
	}
	ret = hweight64(value);
	if (rd < 16) {
		if (rd)
			regs->u_regs[rd] = ret;
	} else {
		unsigned long fp = regs->u_regs[UREG_FP];

		if (!test_thread_64bit_stack(fp)) {
			struct reg_window32 __user *win32;
			win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
			put_user(ret, &win32->locals[rd - 16]);
		} else {
			struct reg_window __user *win;
			win = (struct reg_window __user *)(fp + STACK_BIAS);
			put_user(ret, &win->locals[rd - 16]);
		}
	}
	advance(regs);
	return 1;
}

extern void do_fpother(struct pt_regs *regs);
extern void do_privact(struct pt_regs *regs);
extern void sun4v_data_access_exception(struct pt_regs *regs,
					unsigned long addr,
					unsigned long type_ctx);

int handle_ldf_stq(u32 insn, struct pt_regs *regs)
{
	unsigned long addr = compute_effective_address(regs, insn, 0);
	int freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
	struct fpustate *f = FPUSTATE;
	int asi = decode_asi(insn, regs);
	int flag = (freg < 32) ? FPRS_DL : FPRS_DU;

	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);

	save_and_clear_fpu();
	current_thread_info()->xfsr[0] &= ~0x1c000;
	if (freg & 3) {
		current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
		do_fpother(regs);
		return 0;
	}
	if (insn & 0x200000) {
		/* STQ */
		u64 first = 0, second = 0;
		
		if (current_thread_info()->fpsaved[0] & flag) {
			first = *(u64 *)&f->regs[freg];
			second = *(u64 *)&f->regs[freg+2];
		}
		if (asi < 0x80) {
			do_privact(regs);
			return 1;
		}
		switch (asi) {
		case ASI_P:
		case ASI_S: break;
		case ASI_PL:
		case ASI_SL: 
			{
				/* Need to convert endians */
				u64 tmp = __swab64p(&first);
				
				first = __swab64p(&second);
				second = tmp;
				break;
			}
		default:
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
			return 1;
		}
		if (put_user (first >> 32, (u32 __user *)addr) ||
		    __put_user ((u32)first, (u32 __user *)(addr + 4)) ||
		    __put_user (second >> 32, (u32 __user *)(addr + 8)) ||
		    __put_user ((u32)second, (u32 __user *)(addr + 12))) {
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
		    	return 1;
		}
	} else {
		/* LDF, LDDF, LDQF */
		u32 data[4] __attribute__ ((aligned(8)));
		int size, i;
		int err;

		if (asi < 0x80) {
			do_privact(regs);
			return 1;
		} else if (asi > ASI_SNFL) {
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
			return 1;
		}
		switch (insn & 0x180000) {
		case 0x000000: size = 1; break;
		case 0x100000: size = 4; break;
		default: size = 2; break;
		}
		for (i = 0; i < size; i++)
			data[i] = 0;
		
		err = get_user (data[0], (u32 __user *) addr);
		if (!err) {
			for (i = 1; i < size; i++)
				err |= __get_user (data[i], (u32 __user *)(addr + 4*i));
		}
		if (err && !(asi & 0x2 /* NF */)) {
			if (tlb_type == hypervisor)
				sun4v_data_access_exception(regs, addr, 0);
			else
				spitfire_data_access_exception(regs, 0, addr);
			return 1;
		}
		if (asi & 0x8) /* Little */ {
			u64 tmp;

			switch (size) {
			case 1: data[0] = le32_to_cpup(data + 0); break;
			default:*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 0));
				break;
			case 4: tmp = le64_to_cpup((u64 *)(data + 0));
				*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 2));
				*(u64 *)(data + 2) = tmp;
				break;
			}
		}
		if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
			current_thread_info()->fpsaved[0] = FPRS_FEF;
			current_thread_info()->gsr[0] = 0;
		}
		if (!(current_thread_info()->fpsaved[0] & flag)) {
			if (freg < 32)
				memset(f->regs, 0, 32*sizeof(u32));
			else
				memset(f->regs+32, 0, 32*sizeof(u32));
		}
		memcpy(f->regs + freg, data, size * 4);
		current_thread_info()->fpsaved[0] |= flag;
	}
	advance(regs);
	return 1;
}

void handle_ld_nf(u32 insn, struct pt_regs *regs)
{
	int rd = ((insn >> 25) & 0x1f);
	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	unsigned long *reg;
	                        
	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);

	maybe_flush_windows(0, 0, rd, from_kernel);
	reg = fetch_reg_addr(rd, regs);
	if (from_kernel || rd < 16) {
		reg[0] = 0;
		if ((insn & 0x780000) == 0x180000)
			reg[1] = 0;
	} else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
		put_user(0, (int __user *) reg);
		if ((insn & 0x780000) == 0x180000)
			put_user(0, ((int __user *) reg) + 1);
	} else {
		put_user(0, (unsigned long __user *) reg);
		if ((insn & 0x780000) == 0x180000)
			put_user(0, (unsigned long __user *) reg + 1);
	}
	advance(regs);
}

void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
{
	enum ctx_state prev_state = exception_enter();
	unsigned long pc = regs->tpc;
	unsigned long tstate = regs->tstate;
	u32 insn;
	u64 value;
	u8 freg;
	int flag;
	struct fpustate *f = FPUSTATE;

	if (tstate & TSTATE_PRIV)
		die_if_kernel("lddfmna from kernel", regs);
	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
	if (test_thread_flag(TIF_32BIT))
		pc = (u32)pc;
	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
		int asi = decode_asi(insn, regs);
		u32 first, second;
		int err;

		if ((asi > ASI_SNFL) ||
		    (asi < ASI_P))
			goto daex;
		first = second = 0;
		err = get_user(first, (u32 __user *)sfar);
		if (!err)
			err = get_user(second, (u32 __user *)(sfar + 4));
		if (err) {
			if (!(asi & 0x2))
				goto daex;
			first = second = 0;
		}
		save_and_clear_fpu();
		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
		value = (((u64)first) << 32) | second;
		if (asi & 0x8) /* Little */
			value = __swab64p(&value);
		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
		if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
			current_thread_info()->fpsaved[0] = FPRS_FEF;
			current_thread_info()->gsr[0] = 0;
		}
		if (!(current_thread_info()->fpsaved[0] & flag)) {
			if (freg < 32)
				memset(f->regs, 0, 32*sizeof(u32));
			else
				memset(f->regs+32, 0, 32*sizeof(u32));
		}
		*(u64 *)(f->regs + freg) = value;
		current_thread_info()->fpsaved[0] |= flag;
	} else {
daex:
		if (tlb_type == hypervisor)
			sun4v_data_access_exception(regs, sfar, sfsr);
		else
			spitfire_data_access_exception(regs, sfsr, sfar);
		goto out;
	}
	advance(regs);
out:
	exception_exit(prev_state);
}

void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
{
	enum ctx_state prev_state = exception_enter();
	unsigned long pc = regs->tpc;
	unsigned long tstate = regs->tstate;
	u32 insn;
	u64 value;
	u8 freg;
	int flag;
	struct fpustate *f = FPUSTATE;

	if (tstate & TSTATE_PRIV)
		die_if_kernel("stdfmna from kernel", regs);
	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
	if (test_thread_flag(TIF_32BIT))
		pc = (u32)pc;
	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
		int asi = decode_asi(insn, regs);
		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
		value = 0;
		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
		if ((asi > ASI_SNFL) ||
		    (asi < ASI_P))
			goto daex;
		save_and_clear_fpu();
		if (current_thread_info()->fpsaved[0] & flag)
			value = *(u64 *)&f->regs[freg];
		switch (asi) {
		case ASI_P:
		case ASI_S: break;
		case ASI_PL:
		case ASI_SL: 
			value = __swab64p(&value); break;
		default: goto daex;
		}
		if (put_user (value >> 32, (u32 __user *) sfar) ||
		    __put_user ((u32)value, (u32 __user *)(sfar + 4)))
			goto daex;
	} else {
daex:
		if (tlb_type == hypervisor)
			sun4v_data_access_exception(regs, sfar, sfsr);
		else
			spitfire_data_access_exception(regs, sfsr, sfar);
		goto out;
	}
	advance(regs);
out:
	exception_exit(prev_state);
}
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* unaligned.c: Unaligned load/store trap handling with special
	3	* cases for the kernel to do them more quickly.
	4	*
4fe3ebec	5	* Copyright (C) 1996,2008 David S. Miller (davem@davemloft.net)
1da177e4 LT	6	* Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	7	*/
	8
	9
cbc9fc5d	10	#include <linux/jiffies.h>
1da177e4 LT	11	#include <linux/kernel.h>
	12	#include <linux/sched.h>
	13	#include <linux/mm.h>
	14	#include <linux/module.h>
	15	#include <asm/asi.h>
	16	#include <asm/ptrace.h>
	17	#include <asm/pstate.h>
	18	#include <asm/processor.h>
1da177e4 LT	19	#include <asm/uaccess.h>
1da177e4 LT	20	#include <linux/smp.h>
1da177e4	21	#include <linux/bitops.h>
121dd5f2	22	#include <linux/perf_event.h>
c7ec2b58	23	#include <linux/ratelimit.h>
812cb83a	24	#include <linux/context_tracking.h>
1da177e4	25	#include <asm/fpumacro.h>
d550bbd4	26	#include <asm/cacheflush.h>
8df52620	27	#include <asm/setup.h>
1da177e4	28
812cb83a	29	#include "entry.h"
8df52620	30	#include "kernel.h"
812cb83a	31
1da177e4 LT	32	enum direction {
	33	load, /* ld, ldd, ldh, ldsh */
	34	store, /* st, std, sth, stsh */
	35	both, /* Swap, ldstub, cas, ... */
	36	fpld,
	37	fpst,
	38	invalid,
	39	};
	40
1da177e4 LT	41	static inline enum direction decode_direction(unsigned int insn)
	42	{
	43	unsigned long tmp = (insn >> 21) & 1;
	44
	45	if (!tmp)
	46	return load;
	47	else {
	48	switch ((insn>>19)&0xf) {
	49	case 15: /* swap* */
	50	return both;
	51	default:
	52	return store;
	53	}
	54	}
	55	}
	56
	57	/* 16 = double-word, 8 = extra-word, 4 = word, 2 = half-word */
baa06775	58	static inline int decode_access_size(struct pt_regs *regs, unsigned int insn)
1da177e4 LT	59	{
	60	unsigned int tmp;
	61
	62	tmp = ((insn >> 19) & 0xf);
	63	if (tmp == 11 \|\| tmp == 14) /* ldx/stx */
	64	return 8;
	65	tmp &= 3;
	66	if (!tmp)
	67	return 4;
	68	else if (tmp == 3)
	69	return 16; /* ldd/std - Although it is actually 8 */
	70	else if (tmp == 2)
	71	return 2;
	72	else {
	73	printk("Impossible unaligned trap. insn=%08x\n", insn);
baa06775	74	die_if_kernel("Byte sized unaligned access?!?!", regs);
1da177e4 LT	75
	76	/* GCC should never warn that control reaches the end
	77	* of this function without returning a value because
	78	* die_if_kernel() is marked with attribute 'noreturn'.
	79	* Alas, some versions do...
	80	*/
	81
	82	return 0;
	83	}
	84	}
	85
	86	static inline int decode_asi(unsigned int insn, struct pt_regs *regs)
	87	{
	88	if (insn & 0x800000) {
	89	if (insn & 0x2000)
	90	return (unsigned char)(regs->tstate >> 24); /* %asi */
	91	else
	92	return (unsigned char)(insn >> 5); /* imm_asi */
	93	} else
	94	return ASI_P;
	95	}
	96
	97	/* 0x400000 = signed, 0 = unsigned */
	98	static inline int decode_signedness(unsigned int insn)
	99	{
	100	return (insn & 0x400000);
	101	}
	102
	103	static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
	104	unsigned int rd, int from_kernel)
	105	{
	106	if (rs2 >= 16 \|\| rs1 >= 16 \|\| rd >= 16) {
	107	if (from_kernel != 0)
	108	__asm__ __volatile__("flushw");
	109	else
	110	flushw_user();
	111	}
	112	}
	113
	114	static inline long sign_extend_imm13(long imm)
	115	{
	116	return imm << 51 >> 51;
	117	}
	118
	119	static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
	120	{
517ffce4	121	unsigned long value, fp;
1da177e4 LT	122
	123	if (reg < 16)
	124	return (!reg ? 0 : regs->u_regs[reg]);
517ffce4 DM	125
	126	fp = regs->u_regs[UREG_FP];
	127
1da177e4 LT	128	if (regs->tstate & TSTATE_PRIV) {
1da177e4 LT	129	struct reg_window *win;
517ffce4	130	win = (struct reg_window *)(fp + STACK_BIAS);
1da177e4	131	value = win->locals[reg - 16];
517ffce4	132	} else if (!test_thread_64bit_stack(fp)) {
1da177e4	133	struct reg_window32 __user *win32;
517ffce4	134	win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
1da177e4 LT	135	get_user(value, &win32->locals[reg - 16]);
	136	} else {
	137	struct reg_window __user *win;
517ffce4	138	win = (struct reg_window __user *)(fp + STACK_BIAS);
1da177e4 LT	139	get_user(value, &win->locals[reg - 16]);
	140	}
	141	return value;
	142	}
	143
	144	static unsigned long fetch_reg_addr(unsigned int reg, struct pt_regs regs)
	145	{
517ffce4 DM	146	unsigned long fp;
517ffce4 DM	147
1da177e4 LT	148	if (reg < 16)
1da177e4 LT	149	return &regs->u_regs[reg];
517ffce4 DM	150
	151	fp = regs->u_regs[UREG_FP];
	152
1da177e4 LT	153	if (regs->tstate & TSTATE_PRIV) {
1da177e4 LT	154	struct reg_window *win;
517ffce4	155	win = (struct reg_window *)(fp + STACK_BIAS);
1da177e4	156	return &win->locals[reg - 16];
517ffce4	157	} else if (!test_thread_64bit_stack(fp)) {
1da177e4	158	struct reg_window32 *win32;
517ffce4	159	win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
1da177e4 LT	160	return (unsigned long *)&win32->locals[reg - 16];
	161	} else {
	162	struct reg_window *win;
517ffce4	163	win = (struct reg_window *)(fp + STACK_BIAS);
1da177e4 LT	164	return &win->locals[reg - 16];
	165	}
	166	}
	167
	168	unsigned long compute_effective_address(struct pt_regs *regs,
	169	unsigned int insn, unsigned int rd)
	170	{
d037d163	171	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
1da177e4 LT	172	unsigned int rs1 = (insn >> 14) & 0x1f;
1da177e4 LT	173	unsigned int rs2 = insn & 0x1f;
d037d163	174	unsigned long addr;
1da177e4 LT	175
	176	if (insn & 0x2000) {
	177	maybe_flush_windows(rs1, 0, rd, from_kernel);
d037d163	178	addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn));
1da177e4 LT	179	} else {
1da177e4 LT	180	maybe_flush_windows(rs1, rs2, rd, from_kernel);
d037d163	181	addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));
1da177e4	182	}
d037d163 DM	183
	184	if (!from_kernel && test_thread_flag(TIF_32BIT))
	185	addr &= 0xffffffff;
	186
	187	return addr;
1da177e4 LT	188	}
	189
	190	/* This is just to make gcc think die_if_kernel does return... */
3ff6eecc	191	static void __used unaligned_panic(char str, struct pt_regs regs)
1da177e4 LT	192	{
	193	die_if_kernel(str, regs);
	194	}
	195
5fd29752 DM	196	extern int do_int_load(unsigned long *dest_reg, int size,
5fd29752 DM	197	unsigned long *saddr, int is_signed, int asi);
1da177e4	198
5fd29752 DM	199	extern int __do_int_store(unsigned long *dst_addr, int size,
5fd29752 DM	200	unsigned long src_val, int asi);
a3f99858	201
5fd29752 DM	202	static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
5fd29752 DM	203	struct pt_regs *regs, int asi, int orig_asi)
a3f99858 DM	204	{
a3f99858 DM	205	unsigned long zero = 0;
ff171d8f DM	206	unsigned long *src_val_p = &zero;
ff171d8f DM	207	unsigned long src_val;
a3f99858 DM	208
	209	if (size == 16) {
	210	size = 8;
	211	zero = (((long)(reg_num ?
	212	(unsigned)fetch_reg(reg_num, regs) : 0)) << 32) \|
	213	(unsigned)fetch_reg(reg_num + 1, regs);
	214	} else if (reg_num) {
ff171d8f DM	215	src_val_p = fetch_reg_addr(reg_num, regs);
	216	}
	217	src_val = *src_val_p;
	218	if (unlikely(asi != orig_asi)) {
	219	switch (size) {
	220	case 2:
	221	src_val = swab16(src_val);
	222	break;
	223	case 4:
	224	src_val = swab32(src_val);
	225	break;
	226	case 8:
	227	src_val = swab64(src_val);
	228	break;
	229	case 16:
	230	default:
	231	BUG();
	232	break;
6cb79b3f	233	}
a3f99858	234	}
5fd29752	235	return __do_int_store(dst_addr, size, src_val, asi);
a3f99858	236	}
1da177e4 LT	237
	238	static inline void advance(struct pt_regs *regs)
	239	{
	240	regs->tpc = regs->tnpc;
	241	regs->tnpc += 4;
	242	if (test_thread_flag(TIF_32BIT)) {
	243	regs->tpc &= 0xffffffff;
	244	regs->tnpc &= 0xffffffff;
	245	}
	246	}
	247
	248	static inline int floating_point_load_or_store_p(unsigned int insn)
	249	{
	250	return (insn >> 24) & 1;
	251	}
	252
	253	static inline int ok_for_kernel(unsigned int insn)
	254	{
	255	return !floating_point_load_or_store_p(insn);
	256	}
	257
c449c38b	258	static void kernel_mna_trap_fault(int fixup_tstate_asi)
1da177e4	259	{
a3f99858 DM	260	struct pt_regs *regs = current_thread_info()->kern_una_regs;
a3f99858 DM	261	unsigned int insn = current_thread_info()->kern_una_insn;
8cf14af0	262	const struct exception_table_entry *entry;
1da177e4	263
8cf14af0 DM	264	entry = search_exception_tables(regs->tpc);
8cf14af0 DM	265	if (!entry) {
a3f99858 DM	266	unsigned long address;
	267
	268	address = compute_effective_address(regs, insn,
	269	((insn >> 25) & 0x1f));
1da177e4	270	if (address < PAGE_SIZE) {
a3f99858 DM	271	printk(KERN_ALERT "Unable to handle kernel NULL "
a3f99858 DM	272	"pointer dereference in mna handler");
1da177e4	273	} else
a3f99858 DM	274	printk(KERN_ALERT "Unable to handle kernel paging "
a3f99858 DM	275	"request in mna handler");
1da177e4	276	printk(KERN_ALERT " at virtual address %016lx\n",address);
a3f99858	277	printk(KERN_ALERT "current->{active_,}mm->context = %016lx\n",
1da177e4 LT	278	(current->mm ? CTX_HWBITS(current->mm->context) :
1da177e4 LT	279	CTX_HWBITS(current->active_mm->context)));
a3f99858	280	printk(KERN_ALERT "current->{active_,}mm->pgd = %016lx\n",
1da177e4 LT	281	(current->mm ? (unsigned long) current->mm->pgd :
	282	(unsigned long) current->active_mm->pgd));
	283	die_if_kernel("Oops", regs);
	284	/* Not reached */
	285	}
8cf14af0	286	regs->tpc = entry->fixup;
1da177e4	287	regs->tnpc = regs->tpc + 4;
1da177e4	288
c449c38b DM	289	if (fixup_tstate_asi) {
	290	regs->tstate &= ~TSTATE_ASI;
	291	regs->tstate \|= (ASI_AIUS << 24UL);
	292	}
1da177e4 LT	293	}
1da177e4 LT	294
c449c38b	295	static void log_unaligned(struct pt_regs *regs)
1da177e4	296	{
c7ec2b58	297	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
a3f99858	298
c7ec2b58	299	if (__ratelimit(&ratelimit)) {
4fe3ebec DM	300	printk("Kernel unaligned access at TPC[%lx] %pS\n",
4fe3ebec DM	301	regs->tpc, (void *) regs->tpc);
27cc64c7	302	}
c449c38b DM	303	}
	304
	305	asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
	306	{
	307	enum direction dir = decode_direction(insn);
baa06775	308	int size = decode_access_size(regs, insn);
c449c38b DM	309	int orig_asi, asi;
	310
	311	current_thread_info()->kern_una_regs = regs;
	312	current_thread_info()->kern_una_insn = insn;
	313
	314	orig_asi = asi = decode_asi(insn, regs);
	315
	316	/* If this is a {get,put}_user() on an unaligned userspace pointer,
	317	* just signal a fault and do not log the event.
	318	*/
	319	if (asi == ASI_AIUS) {
	320	kernel_mna_trap_fault(0);
	321	return;
	322	}
	323
	324	log_unaligned(regs);
27cc64c7	325
1da177e4	326	if (!ok_for_kernel(insn) \|\| dir == both) {
a3f99858 DM	327	printk("Unsupported unaligned load/store trap for kernel "
	328	"at <%016lx>.\n", regs->tpc);
	329	unaligned_panic("Kernel does fpu/atomic "
	330	"unaligned load/store.", regs);
	331
c449c38b	332	kernel_mna_trap_fault(0);
1da177e4	333	} else {
705747ab	334	unsigned long addr, *reg_addr;
c449c38b	335	int err;
1da177e4	336
a3f99858 DM	337	addr = compute_effective_address(regs, insn,
a3f99858 DM	338	((insn >> 25) & 0x1f));
a8b0ca17	339	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
ff171d8f DM	340	switch (asi) {
	341	case ASI_NL:
	342	case ASI_AIUPL:
	343	case ASI_AIUSL:
	344	case ASI_PL:
	345	case ASI_SL:
	346	case ASI_PNFL:
	347	case ASI_SNFL:
	348	asi &= ~0x08;
	349	break;
6cb79b3f	350	}
1da177e4 LT	351	switch (dir) {
1da177e4 LT	352	case load:
705747ab	353	reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
5fd29752 DM	354	err = do_int_load(reg_addr, size,
	355	(unsigned long *) addr,
	356	decode_signedness(insn), asi);
	357	if (likely(!err) && unlikely(asi != orig_asi)) {
705747ab	358	unsigned long val_in = *reg_addr;
ff171d8f DM	359	switch (size) {
	360	case 2:
	361	val_in = swab16(val_in);
	362	break;
	363	case 4:
	364	val_in = swab32(val_in);
	365	break;
	366	case 8:
	367	val_in = swab64(val_in);
	368	break;
	369	case 16:
	370	default:
	371	BUG();
	372	break;
6cb79b3f	373	}
705747ab	374	*reg_addr = val_in;
ff171d8f	375	}
1da177e4 LT	376	break;
	377
	378	case store:
5fd29752 DM	379	err = do_int_store(((insn>>25)&0x1f), size,
	380	(unsigned long *) addr, regs,
	381	asi, orig_asi);
1da177e4	382	break;
a3f99858	383
1da177e4 LT	384	default:
	385	panic("Impossible kernel unaligned trap.");
	386	/* Not reached... */
	387	}
5fd29752	388	if (unlikely(err))
c449c38b	389	kernel_mna_trap_fault(1);
5fd29752 DM	390	else
5fd29752 DM	391	advance(regs);
1da177e4 LT	392	}
	393	}
	394
1da177e4 LT	395	int handle_popc(u32 insn, struct pt_regs *regs)
1da177e4 LT	396	{
1da177e4	397	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
d600cbed DM	398	int ret, rd = ((insn >> 25) & 0x1f);
d600cbed DM	399	u64 value;
1da177e4	400
a8b0ca17	401	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
1da177e4 LT	402	if (insn & 0x2000) {
	403	maybe_flush_windows(0, 0, rd, from_kernel);
	404	value = sign_extend_imm13(insn);
	405	} else {
	406	maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
	407	value = fetch_reg(insn & 0x1f, regs);
	408	}
d600cbed	409	ret = hweight64(value);
1da177e4 LT	410	if (rd < 16) {
	411	if (rd)
	412	regs->u_regs[rd] = ret;
	413	} else {
517ffce4 DM	414	unsigned long fp = regs->u_regs[UREG_FP];
	415
	416	if (!test_thread_64bit_stack(fp)) {
1da177e4	417	struct reg_window32 __user *win32;
517ffce4	418	win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
1da177e4 LT	419	put_user(ret, &win32->locals[rd - 16]);
	420	} else {
	421	struct reg_window __user *win;
517ffce4	422	win = (struct reg_window __user *)(fp + STACK_BIAS);
1da177e4 LT	423	put_user(ret, &win->locals[rd - 16]);
	424	}
	425	}
	426	advance(regs);
	427	return 1;
	428	}
	429
	430	extern void do_fpother(struct pt_regs *regs);
	431	extern void do_privact(struct pt_regs *regs);
ed6b0b45 DM	432	extern void sun4v_data_access_exception(struct pt_regs *regs,
	433	unsigned long addr,
	434	unsigned long type_ctx);
1da177e4 LT	435
	436	int handle_ldf_stq(u32 insn, struct pt_regs *regs)
	437	{
	438	unsigned long addr = compute_effective_address(regs, insn, 0);
	439	int freg = ((insn >> 25) & 0x1e) \| ((insn >> 20) & 0x20);
	440	struct fpustate *f = FPUSTATE;
	441	int asi = decode_asi(insn, regs);
	442	int flag = (freg < 32) ? FPRS_DL : FPRS_DU;
	443
a8b0ca17	444	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
121dd5f2	445
1da177e4 LT	446	save_and_clear_fpu();
	447	current_thread_info()->xfsr[0] &= ~0x1c000;
	448	if (freg & 3) {
	449	current_thread_info()->xfsr[0] \|= (6 << 14) /* invalid_fp_register */;
	450	do_fpother(regs);
	451	return 0;
	452	}
	453	if (insn & 0x200000) {
	454	/* STQ */
	455	u64 first = 0, second = 0;
	456
	457	if (current_thread_info()->fpsaved[0] & flag) {
	458	first = (u64 )&f->regs[freg];
	459	second = (u64 )&f->regs[freg+2];
	460	}
	461	if (asi < 0x80) {
	462	do_privact(regs);
	463	return 1;
	464	}
	465	switch (asi) {
	466	case ASI_P:
	467	case ASI_S: break;
	468	case ASI_PL:
	469	case ASI_SL:
	470	{
	471	/* Need to convert endians */
	472	u64 tmp = __swab64p(&first);
	473
	474	first = __swab64p(&second);
	475	second = tmp;
	476	break;
	477	}
	478	default:
ed6b0b45 DM	479	if (tlb_type == hypervisor)
	480	sun4v_data_access_exception(regs, addr, 0);
	481	else
	482	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	483	return 1;
	484	}
	485	if (put_user (first >> 32, (u32 __user *)addr) \|\|
	486	__put_user ((u32)first, (u32 __user *)(addr + 4)) \|\|
	487	__put_user (second >> 32, (u32 __user *)(addr + 8)) \|\|
	488	__put_user ((u32)second, (u32 __user *)(addr + 12))) {
ed6b0b45 DM	489	if (tlb_type == hypervisor)
	490	sun4v_data_access_exception(regs, addr, 0);
	491	else
	492	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	493	return 1;
	494	}
	495	} else {
	496	/* LDF, LDDF, LDQF */
	497	u32 data[4] __attribute__ ((aligned(8)));
	498	int size, i;
	499	int err;
	500
	501	if (asi < 0x80) {
	502	do_privact(regs);
	503	return 1;
	504	} else if (asi > ASI_SNFL) {
ed6b0b45 DM	505	if (tlb_type == hypervisor)
	506	sun4v_data_access_exception(regs, addr, 0);
	507	else
	508	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	509	return 1;
	510	}
	511	switch (insn & 0x180000) {
	512	case 0x000000: size = 1; break;
	513	case 0x100000: size = 4; break;
	514	default: size = 2; break;
	515	}
	516	for (i = 0; i < size; i++)
	517	data[i] = 0;
	518
	519	err = get_user (data[0], (u32 __user *) addr);
	520	if (!err) {
	521	for (i = 1; i < size; i++)
	522	err \|= __get_user (data[i], (u32 __user )(addr + 4i));
	523	}
	524	if (err && !(asi & 0x2 /* NF */)) {
ed6b0b45 DM	525	if (tlb_type == hypervisor)
	526	sun4v_data_access_exception(regs, addr, 0);
	527	else
	528	spitfire_data_access_exception(regs, 0, addr);
1da177e4 LT	529	return 1;
	530	}
	531	if (asi & 0x8) /* Little */ {
	532	u64 tmp;
	533
	534	switch (size) {
	535	case 1: data[0] = le32_to_cpup(data + 0); break;
	536	default:(u64 )(data + 0) = le64_to_cpup((u64 *)(data + 0));
	537	break;
	538	case 4: tmp = le64_to_cpup((u64 *)(data + 0));
	539	(u64 )(data + 0) = le64_to_cpup((u64 *)(data + 2));
	540	(u64 )(data + 2) = tmp;
	541	break;
	542	}
	543	}
	544	if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
	545	current_thread_info()->fpsaved[0] = FPRS_FEF;
	546	current_thread_info()->gsr[0] = 0;
	547	}
	548	if (!(current_thread_info()->fpsaved[0] & flag)) {
	549	if (freg < 32)
	550	memset(f->regs, 0, 32*sizeof(u32));
	551	else
	552	memset(f->regs+32, 0, 32*sizeof(u32));
	553	}
	554	memcpy(f->regs + freg, data, size * 4);
	555	current_thread_info()->fpsaved[0] \|= flag;
	556	}
	557	advance(regs);
	558	return 1;
	559	}
	560
	561	void handle_ld_nf(u32 insn, struct pt_regs *regs)
	562	{
	563	int rd = ((insn >> 25) & 0x1f);
	564	int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
	565	unsigned long *reg;
	566
a8b0ca17	567	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
121dd5f2	568
1da177e4 LT	569	maybe_flush_windows(0, 0, rd, from_kernel);
	570	reg = fetch_reg_addr(rd, regs);
	571	if (from_kernel \|\| rd < 16) {
	572	reg[0] = 0;
	573	if ((insn & 0x780000) == 0x180000)
	574	reg[1] = 0;
517ffce4	575	} else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
1da177e4 LT	576	put_user(0, (int __user *) reg);
	577	if ((insn & 0x780000) == 0x180000)
	578	put_user(0, ((int __user *) reg) + 1);
	579	} else {
	580	put_user(0, (unsigned long __user *) reg);
	581	if ((insn & 0x780000) == 0x180000)
	582	put_user(0, (unsigned long __user *) reg + 1);
	583	}
	584	advance(regs);
	585	}
	586
	587	void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
	588	{
812cb83a	589	enum ctx_state prev_state = exception_enter();
1da177e4 LT	590	unsigned long pc = regs->tpc;
	591	unsigned long tstate = regs->tstate;
	592	u32 insn;
1da177e4	593	u64 value;
ed6b0b45	594	u8 freg;
1da177e4 LT	595	int flag;
	596	struct fpustate *f = FPUSTATE;
	597
	598	if (tstate & TSTATE_PRIV)
	599	die_if_kernel("lddfmna from kernel", regs);
a8b0ca17	600	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
1da177e4 LT	601	if (test_thread_flag(TIF_32BIT))
	602	pc = (u32)pc;
	603	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
ed6b0b45	604	int asi = decode_asi(insn, regs);
b41418f4	605	u32 first, second;
18b8e08e DM	606	int err;
18b8e08e DM	607
1da177e4 LT	608	if ((asi > ASI_SNFL) \|\|
	609	(asi < ASI_P))
	610	goto daex;
b41418f4	611	first = second = 0;
18b8e08e DM	612	err = get_user(first, (u32 __user *)sfar);
	613	if (!err)
	614	err = get_user(second, (u32 __user *)(sfar + 4));
	615	if (err) {
b41418f4	616	if (!(asi & 0x2))
1da177e4	617	goto daex;
b41418f4	618	first = second = 0;
1da177e4 LT	619	}
	620	save_and_clear_fpu();
	621	freg = ((insn >> 25) & 0x1e) \| ((insn >> 20) & 0x20);
	622	value = (((u64)first) << 32) \| second;
	623	if (asi & 0x8) /* Little */
	624	value = __swab64p(&value);
	625	flag = (freg < 32) ? FPRS_DL : FPRS_DU;
	626	if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
	627	current_thread_info()->fpsaved[0] = FPRS_FEF;
	628	current_thread_info()->gsr[0] = 0;
	629	}
	630	if (!(current_thread_info()->fpsaved[0] & flag)) {
	631	if (freg < 32)
	632	memset(f->regs, 0, 32*sizeof(u32));
	633	else
	634	memset(f->regs+32, 0, 32*sizeof(u32));
	635	}
	636	(u64 )(f->regs + freg) = value;
	637	current_thread_info()->fpsaved[0] \|= flag;
	638	} else {
ed6b0b45 DM	639	daex:
	640	if (tlb_type == hypervisor)
	641	sun4v_data_access_exception(regs, sfar, sfsr);
	642	else
	643	spitfire_data_access_exception(regs, sfsr, sfar);
812cb83a	644	goto out;
1da177e4 LT	645	}
1da177e4 LT	646	advance(regs);
812cb83a KT	647	out:
812cb83a KT	648	exception_exit(prev_state);
1da177e4 LT	649	}
	650
	651	void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
	652	{
812cb83a	653	enum ctx_state prev_state = exception_enter();
1da177e4 LT	654	unsigned long pc = regs->tpc;
	655	unsigned long tstate = regs->tstate;
	656	u32 insn;
	657	u64 value;
ed6b0b45	658	u8 freg;
1da177e4 LT	659	int flag;
	660	struct fpustate *f = FPUSTATE;
	661
	662	if (tstate & TSTATE_PRIV)
	663	die_if_kernel("stdfmna from kernel", regs);
a8b0ca17	664	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
1da177e4 LT	665	if (test_thread_flag(TIF_32BIT))
	666	pc = (u32)pc;
	667	if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
ed6b0b45	668	int asi = decode_asi(insn, regs);
1da177e4	669	freg = ((insn >> 25) & 0x1e) \| ((insn >> 20) & 0x20);
1da177e4 LT	670	value = 0;
	671	flag = (freg < 32) ? FPRS_DL : FPRS_DU;
	672	if ((asi > ASI_SNFL) \|\|
	673	(asi < ASI_P))
	674	goto daex;
	675	save_and_clear_fpu();
	676	if (current_thread_info()->fpsaved[0] & flag)
	677	value = (u64 )&f->regs[freg];
	678	switch (asi) {
	679	case ASI_P:
	680	case ASI_S: break;
	681	case ASI_PL:
	682	case ASI_SL:
	683	value = __swab64p(&value); break;
	684	default: goto daex;
	685	}
	686	if (put_user (value >> 32, (u32 __user *) sfar) \|\|
	687	__put_user ((u32)value, (u32 __user *)(sfar + 4)))
	688	goto daex;
	689	} else {
ed6b0b45 DM	690	daex:
	691	if (tlb_type == hypervisor)
	692	sun4v_data_access_exception(regs, sfar, sfsr);
	693	else
	694	spitfire_data_access_exception(regs, sfsr, sfar);
812cb83a	695	goto out;
1da177e4 LT	696	}
1da177e4 LT	697	advance(regs);
812cb83a KT	698	out:
812cb83a KT	699	exception_exit(prev_state);
1da177e4	700	}