projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1b1fbbca | 1 | /* ld script for sparc32/sparc64 kernel */ |
| 1da177e4 LT |
2 | |
| 3 | #include <asm-generic/vmlinux.lds.h> | |
| b74e34db | 4 | |
| bcbe40eb | 5 | #include <asm/page.h> |
| b74e34db | 6 | #include <asm/thread_info.h> |
| 1da177e4 | 7 | |
| 1b1fbbca SR |
8 | #ifdef CONFIG_SPARC32 |
| 9 | #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEADERS | |
| 10 | #define TEXTSTART 0xf0004000 | |
| 11 | ||
| 12 | #define SMP_CACHE_BYTES_SHIFT 5 | |
| 13 | ||
| 14 | #else | |
| 15 | #define SMP_CACHE_BYTES_SHIFT 6 | |
| 16 | #define INITIAL_ADDRESS 0x4000 | |
| 17 | #define TEXTSTART 0x0000000000404000 | |
| 18 | ||
| 19 | #endif | |
| 20 | ||
| 21 | #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) | |
| 22 | ||
| 23 | #ifdef CONFIG_SPARC32 | |
| 1da177e4 LT |
24 | OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") |
| 25 | OUTPUT_ARCH(sparc) | |
| 26 | ENTRY(_start) | |
| 27 | jiffies = jiffies_64 + 4; | |
| 1b1fbbca SR |
28 | #else |
| 29 | /* sparc64 */ | |
| 30 | OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc") | |
| 31 | OUTPUT_ARCH(sparc:v9a) | |
| 32 | ENTRY(_start) | |
| 33 | jiffies = jiffies_64; | |
| 34 | #endif | |
| 35 | ||
| 1da177e4 LT |
36 | SECTIONS |
| 37 | { | |
| 1b1fbbca SR |
38 | /* swapper_low_pmd_dir is sparc64 only */ |
| 39 | swapper_low_pmd_dir = 0x0000000000402000; | |
| 40 | . = INITIAL_ADDRESS; | |
| 41 | .text TEXTSTART : | |
| bcbe40eb SR |
42 | { |
| 43 | _text = .; | |
| ce8a7424 | 44 | HEAD_TEXT |
| bcbe40eb SR |
45 | TEXT_TEXT |
| 46 | SCHED_TEXT | |
| 47 | LOCK_TEXT | |
| 1b1fbbca | 48 | KPROBES_TEXT |
| 9960e9e8 | 49 | IRQENTRY_TEXT |
| bcbe40eb SR |
50 | *(.gnu.warning) |
| 51 | } = 0 | |
| 52 | _etext = .; | |
| 1b1fbbca SR |
53 | |
| 54 | RO_DATA(PAGE_SIZE) | |
| 8b8d8e28 DM |
55 | |
| 56 | /* Start of data section */ | |
| 57 | _sdata = .; | |
| 58 | ||
| bcbe40eb SR |
59 | .data1 : { |
| 60 | *(.data1) | |
| 61 | } | |
| 3240a77b GT |
62 | RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE) |
| 63 | ||
| b74e34db | 64 | /* End of data section */ |
| bcbe40eb | 65 | _edata = .; |
| b74e34db | 66 | |
| bcbe40eb SR |
67 | .fixup : { |
| 68 | __start___fixup = .; | |
| 69 | *(.fixup) | |
| 70 | __stop___fixup = .; | |
| 71 | } | |
| 3240a77b | 72 | EXCEPTION_TABLE(16) |
| bcbe40eb SR |
73 | NOTES |
| 74 | ||
| 75 | . = ALIGN(PAGE_SIZE); | |
| 3240a77b GT |
76 | __init_begin = ALIGN(PAGE_SIZE); |
| 77 | INIT_TEXT_SECTION(PAGE_SIZE) | |
| bcbe40eb | 78 | __init_text_end = .; |
| 3240a77b | 79 | INIT_DATA_SECTION(16) |
| 67d38229 | 80 | |
| 1b1fbbca SR |
81 | . = ALIGN(4); |
| 82 | .tsb_ldquad_phys_patch : { | |
| 83 | __tsb_ldquad_phys_patch = .; | |
| 84 | *(.tsb_ldquad_phys_patch) | |
| 85 | __tsb_ldquad_phys_patch_end = .; | |
| 86 | } | |
| 87 | ||
| 88 | .tsb_phys_patch : { | |
| 89 | __tsb_phys_patch = .; | |
| 90 | *(.tsb_phys_patch) | |
| 91 | __tsb_phys_patch_end = .; | |
| 92 | } | |
| 93 | ||
| 94 | .cpuid_patch : { | |
| 95 | __cpuid_patch = .; | |
| 96 | *(.cpuid_patch) | |
| 97 | __cpuid_patch_end = .; | |
| 98 | } | |
| 99 | ||
| 100 | .sun4v_1insn_patch : { | |
| 101 | __sun4v_1insn_patch = .; | |
| 102 | *(.sun4v_1insn_patch) | |
| 103 | __sun4v_1insn_patch_end = .; | |
| 104 | } | |
| 105 | .sun4v_2insn_patch : { | |
| 106 | __sun4v_2insn_patch = .; | |
| 107 | *(.sun4v_2insn_patch) | |
| 108 | __sun4v_2insn_patch_end = .; | |
| 109 | } | |
| 5b8b93c4 SR |
110 | .leon_1insn_patch : { |
| 111 | __leon_1insn_patch = .; | |
| 112 | *(.leon_1insn_patch) | |
| 113 | __leon_1insn_patch_end = .; | |
| 114 | } | |
| 9076d0e7 DM |
115 | .swapper_tsb_phys_patch : { |
| 116 | __swapper_tsb_phys_patch = .; | |
| 117 | *(.swapper_tsb_phys_patch) | |
| 118 | __swapper_tsb_phys_patch_end = .; | |
| 119 | } | |
| 120 | .swapper_4m_tsb_phys_patch : { | |
| 121 | __swapper_4m_tsb_phys_patch = .; | |
| 122 | *(.swapper_4m_tsb_phys_patch) | |
| 123 | __swapper_4m_tsb_phys_patch_end = .; | |
| 124 | } | |
| b2d43834 DM |
125 | .page_offset_shift_patch : { |
| 126 | __page_offset_shift_patch = .; | |
| 127 | *(.page_offset_shift_patch) | |
| 128 | __page_offset_shift_patch_end = .; | |
| 129 | } | |
| ef7c4d46 DM |
130 | .popc_3insn_patch : { |
| 131 | __popc_3insn_patch = .; | |
| 132 | *(.popc_3insn_patch) | |
| 133 | __popc_3insn_patch_end = .; | |
| 134 | } | |
| 56d205cc DM |
135 | .popc_6insn_patch : { |
| 136 | __popc_6insn_patch = .; | |
| 137 | *(.popc_6insn_patch) | |
| 138 | __popc_6insn_patch_end = .; | |
| 139 | } | |
| 187818cd DM |
140 | .pause_3insn_patch : { |
| 141 | __pause_3insn_patch = .; | |
| 142 | *(.pause_3insn_patch) | |
| 143 | __pause_3insn_patch_end = .; | |
| e9b9eb59 | 144 | } |
| 0415b00d | 145 | PERCPU_SECTION(SMP_CACHE_BYTES) |
| 1b1fbbca | 146 | |
| bcbe40eb SR |
147 | . = ALIGN(PAGE_SIZE); |
| 148 | __init_end = .; | |
| 3240a77b | 149 | BSS_SECTION(0, 0, 0) |
| bcbe40eb | 150 | _end = . ; |
| 1b1fbbca | 151 | |
| bcbe40eb SR |
152 | STABS_DEBUG |
| 153 | DWARF_DEBUG | |
| 023bf6f1 TH |
154 | |
| 155 | DISCARDS | |
| 1da177e4 | 156 | } |