Commit | Line | Data |
---|---|---|
b00dc837 | 1 | /* |
1da177e4 LT |
2 | * arch/sparc64/mm/init.c |
3 | * | |
4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
c4bce90e | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/string.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/hugetlb.h> | |
1da177e4 LT |
16 | #include <linux/initrd.h> |
17 | #include <linux/swap.h> | |
18 | #include <linux/pagemap.h> | |
c9cf5528 | 19 | #include <linux/poison.h> |
1da177e4 LT |
20 | #include <linux/fs.h> |
21 | #include <linux/seq_file.h> | |
05e14cb3 | 22 | #include <linux/kprobes.h> |
1ac4f5eb | 23 | #include <linux/cache.h> |
13edad7a | 24 | #include <linux/sort.h> |
f6d4fb5c | 25 | #include <linux/ioport.h> |
5cbc3073 | 26 | #include <linux/percpu.h> |
95f72d1e | 27 | #include <linux/memblock.h> |
919ee677 | 28 | #include <linux/mmzone.h> |
5a0e3ad6 | 29 | #include <linux/gfp.h> |
1da177e4 LT |
30 | |
31 | #include <asm/head.h> | |
1da177e4 LT |
32 | #include <asm/page.h> |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/tlbflush.h> | |
41 | #include <asm/dma.h> | |
42 | #include <asm/starfire.h> | |
43 | #include <asm/tlb.h> | |
44 | #include <asm/spitfire.h> | |
45 | #include <asm/sections.h> | |
517af332 | 46 | #include <asm/tsb.h> |
481295f9 | 47 | #include <asm/hypervisor.h> |
372b07bb | 48 | #include <asm/prom.h> |
5cbc3073 | 49 | #include <asm/mdesc.h> |
3d5ae6b6 | 50 | #include <asm/cpudata.h> |
59dec13b | 51 | #include <asm/setup.h> |
4f70f7a9 | 52 | #include <asm/irq.h> |
1da177e4 | 53 | |
27137e52 | 54 | #include "init_64.h" |
9cc3a1ac | 55 | |
4f93d21d | 56 | unsigned long kern_linear_pte_xor[4] __read_mostly; |
9cc3a1ac | 57 | |
4f93d21d DM |
58 | /* A bitmap, two bits for every 256MB of physical memory. These two |
59 | * bits determine what page size we use for kernel linear | |
60 | * translations. They form an index into kern_linear_pte_xor[]. The | |
61 | * value in the indexed slot is XOR'd with the TLB miss virtual | |
62 | * address to form the resulting TTE. The mapping is: | |
63 | * | |
64 | * 0 ==> 4MB | |
65 | * 1 ==> 256MB | |
66 | * 2 ==> 2GB | |
67 | * 3 ==> 16GB | |
68 | * | |
69 | * All sun4v chips support 256MB pages. Only SPARC-T4 and later | |
70 | * support 2GB pages, and hopefully future cpus will support the 16GB | |
71 | * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there | |
72 | * if these larger page sizes are not supported by the cpu. | |
73 | * | |
74 | * It would be nice to determine this from the machine description | |
75 | * 'cpu' properties, but we need to have this table setup before the | |
76 | * MDESC is initialized. | |
9cc3a1ac DM |
77 | */ |
78 | unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)]; | |
79 | ||
d1acb421 | 80 | #ifndef CONFIG_DEBUG_PAGEALLOC |
4f93d21d DM |
81 | /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. |
82 | * Space is allocated for this right after the trap table in | |
83 | * arch/sparc64/kernel/head.S | |
2d9e2763 DM |
84 | */ |
85 | extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 86 | #endif |
d7744a09 | 87 | |
ce33fdc5 DM |
88 | static unsigned long cpu_pgsz_mask; |
89 | ||
13edad7a DM |
90 | #define MAX_BANKS 32 |
91 | ||
7c9503b8 GKH |
92 | static struct linux_prom64_registers pavail[MAX_BANKS]; |
93 | static int pavail_ents; | |
13edad7a DM |
94 | |
95 | static int cmp_p64(const void *a, const void *b) | |
96 | { | |
97 | const struct linux_prom64_registers *x = a, *y = b; | |
98 | ||
99 | if (x->phys_addr > y->phys_addr) | |
100 | return 1; | |
101 | if (x->phys_addr < y->phys_addr) | |
102 | return -1; | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static void __init read_obp_memory(const char *property, | |
107 | struct linux_prom64_registers *regs, | |
108 | int *num_ents) | |
109 | { | |
8d125562 | 110 | phandle node = prom_finddevice("/memory"); |
13edad7a DM |
111 | int prop_size = prom_getproplen(node, property); |
112 | int ents, ret, i; | |
113 | ||
114 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
115 | if (ents > MAX_BANKS) { | |
116 | prom_printf("The machine has more %s property entries than " | |
117 | "this kernel can support (%d).\n", | |
118 | property, MAX_BANKS); | |
119 | prom_halt(); | |
120 | } | |
121 | ||
122 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
123 | if (ret == -1) { | |
5da444aa AM |
124 | prom_printf("Couldn't get %s property from /memory.\n", |
125 | property); | |
13edad7a DM |
126 | prom_halt(); |
127 | } | |
128 | ||
13edad7a DM |
129 | /* Sanitize what we got from the firmware, by page aligning |
130 | * everything. | |
131 | */ | |
132 | for (i = 0; i < ents; i++) { | |
133 | unsigned long base, size; | |
134 | ||
135 | base = regs[i].phys_addr; | |
136 | size = regs[i].reg_size; | |
10147570 | 137 | |
13edad7a DM |
138 | size &= PAGE_MASK; |
139 | if (base & ~PAGE_MASK) { | |
140 | unsigned long new_base = PAGE_ALIGN(base); | |
141 | ||
142 | size -= new_base - base; | |
143 | if ((long) size < 0L) | |
144 | size = 0UL; | |
145 | base = new_base; | |
146 | } | |
0015d3d6 DM |
147 | if (size == 0UL) { |
148 | /* If it is empty, simply get rid of it. | |
149 | * This simplifies the logic of the other | |
150 | * functions that process these arrays. | |
151 | */ | |
152 | memmove(®s[i], ®s[i + 1], | |
153 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 154 | i--; |
0015d3d6 DM |
155 | ents--; |
156 | continue; | |
486ad10a | 157 | } |
0015d3d6 DM |
158 | regs[i].phys_addr = base; |
159 | regs[i].reg_size = size; | |
486ad10a DM |
160 | } |
161 | ||
162 | *num_ents = ents; | |
163 | ||
c9c10830 | 164 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
165 | cmp_p64, NULL); |
166 | } | |
1da177e4 | 167 | |
d8ed1d43 DM |
168 | unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES / |
169 | sizeof(unsigned long)]; | |
917c3660 | 170 | EXPORT_SYMBOL(sparc64_valid_addr_bitmap); |
1da177e4 | 171 | |
d1112018 | 172 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
173 | unsigned long kern_base __read_mostly; |
174 | unsigned long kern_size __read_mostly; | |
1da177e4 | 175 | |
1da177e4 LT |
176 | /* Initial ramdisk setup */ |
177 | extern unsigned long sparc_ramdisk_image64; | |
178 | extern unsigned int sparc_ramdisk_image; | |
179 | extern unsigned int sparc_ramdisk_size; | |
180 | ||
1ac4f5eb | 181 | struct page *mem_map_zero __read_mostly; |
35802c0b | 182 | EXPORT_SYMBOL(mem_map_zero); |
1da177e4 | 183 | |
0835ae0f DM |
184 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
185 | ||
186 | unsigned long sparc64_kern_pri_context __read_mostly; | |
187 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
188 | unsigned long sparc64_kern_sec_context __read_mostly; | |
189 | ||
64658743 | 190 | int num_kernel_image_mappings; |
1da177e4 | 191 | |
1da177e4 LT |
192 | #ifdef CONFIG_DEBUG_DCFLUSH |
193 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
194 | #ifdef CONFIG_SMP | |
195 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
196 | #endif | |
197 | #endif | |
198 | ||
7a591cfe | 199 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 200 | { |
7a591cfe | 201 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
202 | #ifdef CONFIG_DEBUG_DCFLUSH |
203 | atomic_inc(&dcpage_flushes); | |
204 | #endif | |
205 | ||
206 | #ifdef DCACHE_ALIASING_POSSIBLE | |
207 | __flush_dcache_page(page_address(page), | |
208 | ((tlb_type == spitfire) && | |
209 | page_mapping(page) != NULL)); | |
210 | #else | |
211 | if (page_mapping(page) != NULL && | |
212 | tlb_type == spitfire) | |
213 | __flush_icache_page(__pa(page_address(page))); | |
214 | #endif | |
215 | } | |
216 | ||
217 | #define PG_dcache_dirty PG_arch_1 | |
22adb358 DM |
218 | #define PG_dcache_cpu_shift 32UL |
219 | #define PG_dcache_cpu_mask \ | |
220 | ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) | |
1da177e4 LT |
221 | |
222 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 223 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 | 224 | |
d979f179 | 225 | static inline void set_dcache_dirty(struct page *page, int this_cpu) |
1da177e4 LT |
226 | { |
227 | unsigned long mask = this_cpu; | |
48b0e548 DM |
228 | unsigned long non_cpu_bits; |
229 | ||
230 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
231 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
232 | ||
1da177e4 LT |
233 | __asm__ __volatile__("1:\n\t" |
234 | "ldx [%2], %%g7\n\t" | |
235 | "and %%g7, %1, %%g1\n\t" | |
236 | "or %%g1, %0, %%g1\n\t" | |
237 | "casx [%2], %%g7, %%g1\n\t" | |
238 | "cmp %%g7, %%g1\n\t" | |
239 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 240 | " nop" |
1da177e4 LT |
241 | : /* no outputs */ |
242 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
243 | : "g1", "g7"); | |
244 | } | |
245 | ||
d979f179 | 246 | static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
1da177e4 LT |
247 | { |
248 | unsigned long mask = (1UL << PG_dcache_dirty); | |
249 | ||
250 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
251 | "1:\n\t" | |
252 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 253 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
254 | "and %%g1, %3, %%g1\n\t" |
255 | "cmp %%g1, %0\n\t" | |
256 | "bne,pn %%icc, 2f\n\t" | |
257 | " andn %%g7, %1, %%g1\n\t" | |
258 | "casx [%2], %%g7, %%g1\n\t" | |
259 | "cmp %%g7, %%g1\n\t" | |
260 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 261 | " nop\n" |
1da177e4 LT |
262 | "2:" |
263 | : /* no outputs */ | |
264 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
265 | "i" (PG_dcache_cpu_mask), |
266 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
267 | : "g1", "g7"); |
268 | } | |
269 | ||
517af332 DM |
270 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
271 | { | |
272 | unsigned long tsb_addr = (unsigned long) ent; | |
273 | ||
3b3ab2eb | 274 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
275 | tsb_addr = __pa(tsb_addr); |
276 | ||
277 | __tsb_insert(tsb_addr, tag, pte); | |
278 | } | |
279 | ||
c4bce90e | 280 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
c4bce90e | 281 | |
ff9aefbf | 282 | static void flush_dcache(unsigned long pfn) |
1da177e4 | 283 | { |
ff9aefbf | 284 | struct page *page; |
7a591cfe | 285 | |
ff9aefbf | 286 | page = pfn_to_page(pfn); |
1a78cedb | 287 | if (page) { |
7a591cfe | 288 | unsigned long pg_flags; |
7a591cfe | 289 | |
ff9aefbf SR |
290 | pg_flags = page->flags; |
291 | if (pg_flags & (1UL << PG_dcache_dirty)) { | |
7a591cfe DM |
292 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & |
293 | PG_dcache_cpu_mask); | |
294 | int this_cpu = get_cpu(); | |
295 | ||
296 | /* This is just to optimize away some function calls | |
297 | * in the SMP case. | |
298 | */ | |
299 | if (cpu == this_cpu) | |
300 | flush_dcache_page_impl(page); | |
301 | else | |
302 | smp_flush_dcache_page_impl(page, cpu); | |
303 | ||
304 | clear_dcache_dirty_cpu(page, cpu); | |
305 | ||
306 | put_cpu(); | |
307 | } | |
1da177e4 | 308 | } |
ff9aefbf SR |
309 | } |
310 | ||
9e695d2e DM |
311 | /* mm->context.lock must be held */ |
312 | static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, | |
313 | unsigned long tsb_hash_shift, unsigned long address, | |
314 | unsigned long tte) | |
315 | { | |
316 | struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; | |
317 | unsigned long tag; | |
318 | ||
bcd896ba DM |
319 | if (unlikely(!tsb)) |
320 | return; | |
321 | ||
9e695d2e DM |
322 | tsb += ((address >> tsb_hash_shift) & |
323 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
324 | tag = (address >> 22UL); | |
325 | tsb_insert(tsb, tag, tte); | |
326 | } | |
327 | ||
bcd896ba DM |
328 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
329 | static inline bool is_hugetlb_pte(pte_t pte) | |
330 | { | |
331 | if ((tlb_type == hypervisor && | |
332 | (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) || | |
333 | (tlb_type != hypervisor && | |
334 | (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) | |
335 | return true; | |
336 | return false; | |
337 | } | |
338 | #endif | |
339 | ||
4b3073e1 | 340 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
ff9aefbf SR |
341 | { |
342 | struct mm_struct *mm; | |
bcd896ba | 343 | unsigned long flags; |
4b3073e1 | 344 | pte_t pte = *ptep; |
ff9aefbf SR |
345 | |
346 | if (tlb_type != hypervisor) { | |
347 | unsigned long pfn = pte_pfn(pte); | |
348 | ||
349 | if (pfn_valid(pfn)) | |
350 | flush_dcache(pfn); | |
351 | } | |
bd40791e DM |
352 | |
353 | mm = vma->vm_mm; | |
7a1ac526 | 354 | |
18f38132 DM |
355 | /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ |
356 | if (!pte_accessible(mm, pte)) | |
357 | return; | |
358 | ||
7a1ac526 DM |
359 | spin_lock_irqsave(&mm->context.lock, flags); |
360 | ||
9e695d2e | 361 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
bcd896ba | 362 | if (mm->context.huge_pte_count && is_hugetlb_pte(pte)) |
37b3a8ff | 363 | __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, |
bcd896ba DM |
364 | address, pte_val(pte)); |
365 | else | |
dcc1e8dd | 366 | #endif |
bcd896ba DM |
367 | __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, |
368 | address, pte_val(pte)); | |
7a1ac526 DM |
369 | |
370 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
371 | } |
372 | ||
373 | void flush_dcache_page(struct page *page) | |
374 | { | |
a9546f59 DM |
375 | struct address_space *mapping; |
376 | int this_cpu; | |
1da177e4 | 377 | |
7a591cfe DM |
378 | if (tlb_type == hypervisor) |
379 | return; | |
380 | ||
a9546f59 DM |
381 | /* Do not bother with the expensive D-cache flush if it |
382 | * is merely the zero page. The 'bigcore' testcase in GDB | |
383 | * causes this case to run millions of times. | |
384 | */ | |
385 | if (page == ZERO_PAGE(0)) | |
386 | return; | |
387 | ||
388 | this_cpu = get_cpu(); | |
389 | ||
390 | mapping = page_mapping(page); | |
1da177e4 | 391 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 392 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 393 | if (dirty) { |
a9546f59 DM |
394 | int dirty_cpu = dcache_dirty_cpu(page); |
395 | ||
1da177e4 LT |
396 | if (dirty_cpu == this_cpu) |
397 | goto out; | |
398 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
399 | } | |
400 | set_dcache_dirty(page, this_cpu); | |
401 | } else { | |
402 | /* We could delay the flush for the !page_mapping | |
403 | * case too. But that case is for exec env/arg | |
404 | * pages and those are %99 certainly going to get | |
405 | * faulted into the tlb (and thus flushed) anyways. | |
406 | */ | |
407 | flush_dcache_page_impl(page); | |
408 | } | |
409 | ||
410 | out: | |
411 | put_cpu(); | |
412 | } | |
917c3660 | 413 | EXPORT_SYMBOL(flush_dcache_page); |
1da177e4 | 414 | |
05e14cb3 | 415 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 416 | { |
a43fe0e7 | 417 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
418 | if (tlb_type == spitfire) { |
419 | unsigned long kaddr; | |
420 | ||
a94aa253 DM |
421 | /* This code only runs on Spitfire cpus so this is |
422 | * why we can assume _PAGE_PADDR_4U. | |
423 | */ | |
424 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
425 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
426 | ||
427 | if (kaddr >= PAGE_OFFSET) | |
428 | paddr = kaddr & mask; | |
429 | else { | |
430 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
431 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
432 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
433 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
434 | ||
435 | paddr = pte_val(*ptep) & mask; | |
436 | } | |
437 | __flush_icache_page(paddr); | |
438 | } | |
1da177e4 LT |
439 | } |
440 | } | |
917c3660 | 441 | EXPORT_SYMBOL(flush_icache_range); |
1da177e4 | 442 | |
1da177e4 LT |
443 | void mmu_info(struct seq_file *m) |
444 | { | |
ce33fdc5 DM |
445 | static const char *pgsz_strings[] = { |
446 | "8K", "64K", "512K", "4MB", "32MB", | |
447 | "256MB", "2GB", "16GB", | |
448 | }; | |
449 | int i, printed; | |
450 | ||
1da177e4 LT |
451 | if (tlb_type == cheetah) |
452 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
453 | else if (tlb_type == cheetah_plus) | |
454 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
455 | else if (tlb_type == spitfire) | |
456 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
457 | else if (tlb_type == hypervisor) |
458 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
459 | else |
460 | seq_printf(m, "MMU Type\t: ???\n"); | |
461 | ||
ce33fdc5 DM |
462 | seq_printf(m, "MMU PGSZs\t: "); |
463 | printed = 0; | |
464 | for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { | |
465 | if (cpu_pgsz_mask & (1UL << i)) { | |
466 | seq_printf(m, "%s%s", | |
467 | printed ? "," : "", pgsz_strings[i]); | |
468 | printed++; | |
469 | } | |
470 | } | |
471 | seq_putc(m, '\n'); | |
472 | ||
1da177e4 LT |
473 | #ifdef CONFIG_DEBUG_DCFLUSH |
474 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
475 | atomic_read(&dcpage_flushes)); | |
476 | #ifdef CONFIG_SMP | |
477 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
478 | atomic_read(&dcpage_flushes_xcall)); | |
479 | #endif /* CONFIG_SMP */ | |
480 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
481 | } | |
482 | ||
a94aa253 DM |
483 | struct linux_prom_translation prom_trans[512] __read_mostly; |
484 | unsigned int prom_trans_ents __read_mostly; | |
485 | ||
1da177e4 LT |
486 | unsigned long kern_locked_tte_data; |
487 | ||
c9c10830 DM |
488 | /* The obp translations are saved based on 8k pagesize, since obp can |
489 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 490 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 491 | */ |
5085b4a5 DM |
492 | static inline int in_obp_range(unsigned long vaddr) |
493 | { | |
494 | return (vaddr >= LOW_OBP_ADDRESS && | |
495 | vaddr < HI_OBP_ADDRESS); | |
496 | } | |
497 | ||
c9c10830 | 498 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 499 | { |
c9c10830 | 500 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 501 | |
c9c10830 DM |
502 | if (x->virt > y->virt) |
503 | return 1; | |
504 | if (x->virt < y->virt) | |
505 | return -1; | |
506 | return 0; | |
405599bd DM |
507 | } |
508 | ||
c9c10830 | 509 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 510 | static void __init read_obp_translations(void) |
405599bd | 511 | { |
c9c10830 | 512 | int n, node, ents, first, last, i; |
1da177e4 LT |
513 | |
514 | node = prom_finddevice("/virtual-memory"); | |
515 | n = prom_getproplen(node, "translations"); | |
405599bd | 516 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 517 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
518 | prom_halt(); |
519 | } | |
405599bd | 520 | if (unlikely(n > sizeof(prom_trans))) { |
5da444aa | 521 | prom_printf("prom_mappings: Size %d is too big.\n", n); |
1da177e4 LT |
522 | prom_halt(); |
523 | } | |
405599bd | 524 | |
b206fc4c | 525 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
526 | (char *)&prom_trans[0], |
527 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 528 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
529 | prom_halt(); |
530 | } | |
9ad98c5b | 531 | |
b206fc4c | 532 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 533 | |
c9c10830 DM |
534 | ents = n; |
535 | ||
536 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
537 | cmp_ptrans, NULL); | |
538 | ||
539 | /* Now kick out all the non-OBP entries. */ | |
540 | for (i = 0; i < ents; i++) { | |
541 | if (in_obp_range(prom_trans[i].virt)) | |
542 | break; | |
543 | } | |
544 | first = i; | |
545 | for (; i < ents; i++) { | |
546 | if (!in_obp_range(prom_trans[i].virt)) | |
547 | break; | |
548 | } | |
549 | last = i; | |
550 | ||
551 | for (i = 0; i < (last - first); i++) { | |
552 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
553 | struct linux_prom_translation *dest = &prom_trans[i]; | |
554 | ||
555 | *dest = *src; | |
556 | } | |
557 | for (; i < ents; i++) { | |
558 | struct linux_prom_translation *dest = &prom_trans[i]; | |
559 | dest->virt = dest->size = dest->data = 0x0UL; | |
560 | } | |
561 | ||
562 | prom_trans_ents = last - first; | |
563 | ||
564 | if (tlb_type == spitfire) { | |
565 | /* Clear diag TTE bits. */ | |
566 | for (i = 0; i < prom_trans_ents; i++) | |
567 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
568 | } | |
f4142cba DM |
569 | |
570 | /* Force execute bit on. */ | |
571 | for (i = 0; i < prom_trans_ents; i++) | |
572 | prom_trans[i].data |= (tlb_type == hypervisor ? | |
573 | _PAGE_EXEC_4V : _PAGE_EXEC_4U); | |
405599bd | 574 | } |
1da177e4 | 575 | |
d82ace7d DM |
576 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
577 | unsigned long pte, | |
578 | unsigned long mmu) | |
579 | { | |
7db35f31 DM |
580 | unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); |
581 | ||
582 | if (ret != 0) { | |
5da444aa | 583 | prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " |
7db35f31 | 584 | "errors with %lx\n", vaddr, 0, pte, mmu, ret); |
12e126ad DM |
585 | prom_halt(); |
586 | } | |
d82ace7d DM |
587 | } |
588 | ||
c4bce90e DM |
589 | static unsigned long kern_large_tte(unsigned long paddr); |
590 | ||
898cf0ec | 591 | static void __init remap_kernel(void) |
405599bd DM |
592 | { |
593 | unsigned long phys_page, tte_vaddr, tte_data; | |
64658743 | 594 | int i, tlb_ent = sparc64_highest_locked_tlbent(); |
405599bd | 595 | |
1da177e4 | 596 | tte_vaddr = (unsigned long) KERNBASE; |
0eef331a | 597 | phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; |
c4bce90e | 598 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
599 | |
600 | kern_locked_tte_data = tte_data; | |
601 | ||
d82ace7d DM |
602 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
603 | if (tlb_type == hypervisor) { | |
64658743 | 604 | for (i = 0; i < num_kernel_image_mappings; i++) { |
d82ace7d DM |
605 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); |
606 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
64658743 DM |
607 | tte_vaddr += 0x400000; |
608 | tte_data += 0x400000; | |
d82ace7d DM |
609 | } |
610 | } else { | |
64658743 DM |
611 | for (i = 0; i < num_kernel_image_mappings; i++) { |
612 | prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
613 | prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
614 | tte_vaddr += 0x400000; | |
615 | tte_data += 0x400000; | |
d82ace7d | 616 | } |
64658743 | 617 | sparc64_highest_unlocked_tlb_ent = tlb_ent - i; |
1da177e4 | 618 | } |
0835ae0f DM |
619 | if (tlb_type == cheetah_plus) { |
620 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
621 | CTX_CHEETAH_PLUS_NUC); | |
622 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
623 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
624 | } | |
405599bd | 625 | } |
1da177e4 | 626 | |
405599bd | 627 | |
c9c10830 | 628 | static void __init inherit_prom_mappings(void) |
9ad98c5b | 629 | { |
405599bd | 630 | /* Now fixup OBP's idea about where we really are mapped. */ |
3c62a2d3 | 631 | printk("Remapping the kernel... "); |
405599bd | 632 | remap_kernel(); |
3c62a2d3 | 633 | printk("done.\n"); |
1da177e4 LT |
634 | } |
635 | ||
1da177e4 LT |
636 | void prom_world(int enter) |
637 | { | |
1da177e4 | 638 | if (!enter) |
dff933da | 639 | set_fs(get_fs()); |
1da177e4 | 640 | |
3487d1d4 | 641 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
642 | } |
643 | ||
1da177e4 LT |
644 | void __flush_dcache_range(unsigned long start, unsigned long end) |
645 | { | |
646 | unsigned long va; | |
647 | ||
648 | if (tlb_type == spitfire) { | |
649 | int n = 0; | |
650 | ||
651 | for (va = start; va < end; va += 32) { | |
652 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
653 | if (++n >= 512) | |
654 | break; | |
655 | } | |
a43fe0e7 | 656 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
657 | start = __pa(start); |
658 | end = __pa(end); | |
659 | for (va = start; va < end; va += 32) | |
660 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
661 | "membar #Sync" | |
662 | : /* no outputs */ | |
663 | : "r" (va), | |
664 | "i" (ASI_DCACHE_INVALIDATE)); | |
665 | } | |
666 | } | |
917c3660 | 667 | EXPORT_SYMBOL(__flush_dcache_range); |
1da177e4 | 668 | |
85f1e1f6 DM |
669 | /* get_new_mmu_context() uses "cache + 1". */ |
670 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
671 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; | |
672 | #define MAX_CTX_NR (1UL << CTX_NR_BITS) | |
673 | #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) | |
674 | DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); | |
675 | ||
1da177e4 LT |
676 | /* Caller does TLB context flushing on local CPU if necessary. |
677 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
678 | * | |
679 | * We must be careful about boundary cases so that we never | |
680 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
681 | * version of zero (and thus NO_CONTEXT would not be caught | |
682 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
683 | * |
684 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
685 | */ |
686 | void get_new_mmu_context(struct mm_struct *mm) | |
687 | { | |
688 | unsigned long ctx, new_ctx; | |
689 | unsigned long orig_pgsz_bits; | |
a0663a79 | 690 | int new_version; |
1da177e4 | 691 | |
07df8418 | 692 | spin_lock(&ctx_alloc_lock); |
1da177e4 LT |
693 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
694 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
695 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
a0663a79 | 696 | new_version = 0; |
1da177e4 LT |
697 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
698 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
699 | if (new_ctx >= ctx) { | |
700 | int i; | |
701 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + | |
702 | CTX_FIRST_VERSION; | |
703 | if (new_ctx == 1) | |
704 | new_ctx = CTX_FIRST_VERSION; | |
705 | ||
706 | /* Don't call memset, for 16 entries that's just | |
707 | * plain silly... | |
708 | */ | |
709 | mmu_context_bmap[0] = 3; | |
710 | mmu_context_bmap[1] = 0; | |
711 | mmu_context_bmap[2] = 0; | |
712 | mmu_context_bmap[3] = 0; | |
713 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { | |
714 | mmu_context_bmap[i + 0] = 0; | |
715 | mmu_context_bmap[i + 1] = 0; | |
716 | mmu_context_bmap[i + 2] = 0; | |
717 | mmu_context_bmap[i + 3] = 0; | |
718 | } | |
a0663a79 | 719 | new_version = 1; |
1da177e4 LT |
720 | goto out; |
721 | } | |
722 | } | |
723 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); | |
724 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
725 | out: | |
726 | tlb_context_cache = new_ctx; | |
727 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
07df8418 | 728 | spin_unlock(&ctx_alloc_lock); |
a0663a79 DM |
729 | |
730 | if (unlikely(new_version)) | |
731 | smp_new_mmu_context_version(); | |
1da177e4 LT |
732 | } |
733 | ||
919ee677 DM |
734 | static int numa_enabled = 1; |
735 | static int numa_debug; | |
736 | ||
737 | static int __init early_numa(char *p) | |
1da177e4 | 738 | { |
919ee677 DM |
739 | if (!p) |
740 | return 0; | |
741 | ||
742 | if (strstr(p, "off")) | |
743 | numa_enabled = 0; | |
d1112018 | 744 | |
919ee677 DM |
745 | if (strstr(p, "debug")) |
746 | numa_debug = 1; | |
d1112018 | 747 | |
919ee677 | 748 | return 0; |
d1112018 | 749 | } |
919ee677 DM |
750 | early_param("numa", early_numa); |
751 | ||
752 | #define numadbg(f, a...) \ | |
753 | do { if (numa_debug) \ | |
754 | printk(KERN_INFO f, ## a); \ | |
755 | } while (0) | |
d1112018 | 756 | |
4e82c9a6 DM |
757 | static void __init find_ramdisk(unsigned long phys_base) |
758 | { | |
759 | #ifdef CONFIG_BLK_DEV_INITRD | |
760 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
761 | unsigned long ramdisk_image; | |
762 | ||
763 | /* Older versions of the bootloader only supported a | |
764 | * 32-bit physical address for the ramdisk image | |
765 | * location, stored at sparc_ramdisk_image. Newer | |
766 | * SILO versions set sparc_ramdisk_image to zero and | |
767 | * provide a full 64-bit physical address at | |
768 | * sparc_ramdisk_image64. | |
769 | */ | |
770 | ramdisk_image = sparc_ramdisk_image; | |
771 | if (!ramdisk_image) | |
772 | ramdisk_image = sparc_ramdisk_image64; | |
773 | ||
774 | /* Another bootloader quirk. The bootloader normalizes | |
775 | * the physical address to KERNBASE, so we have to | |
776 | * factor that back out and add in the lowest valid | |
777 | * physical page address to get the true physical address. | |
778 | */ | |
779 | ramdisk_image -= KERNBASE; | |
780 | ramdisk_image += phys_base; | |
781 | ||
919ee677 DM |
782 | numadbg("Found ramdisk at physical address 0x%lx, size %u\n", |
783 | ramdisk_image, sparc_ramdisk_size); | |
784 | ||
4e82c9a6 DM |
785 | initrd_start = ramdisk_image; |
786 | initrd_end = ramdisk_image + sparc_ramdisk_size; | |
3b2a7e23 | 787 | |
95f72d1e | 788 | memblock_reserve(initrd_start, sparc_ramdisk_size); |
d45100f7 DM |
789 | |
790 | initrd_start += PAGE_OFFSET; | |
791 | initrd_end += PAGE_OFFSET; | |
4e82c9a6 DM |
792 | } |
793 | #endif | |
794 | } | |
795 | ||
919ee677 DM |
796 | struct node_mem_mask { |
797 | unsigned long mask; | |
798 | unsigned long val; | |
919ee677 DM |
799 | }; |
800 | static struct node_mem_mask node_masks[MAX_NUMNODES]; | |
801 | static int num_node_masks; | |
802 | ||
48d37216 SR |
803 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
804 | ||
919ee677 DM |
805 | int numa_cpu_lookup_table[NR_CPUS]; |
806 | cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; | |
807 | ||
919ee677 DM |
808 | struct mdesc_mblock { |
809 | u64 base; | |
810 | u64 size; | |
811 | u64 offset; /* RA-to-PA */ | |
812 | }; | |
813 | static struct mdesc_mblock *mblocks; | |
814 | static int num_mblocks; | |
815 | ||
816 | static unsigned long ra_to_pa(unsigned long addr) | |
817 | { | |
818 | int i; | |
819 | ||
820 | for (i = 0; i < num_mblocks; i++) { | |
821 | struct mdesc_mblock *m = &mblocks[i]; | |
822 | ||
823 | if (addr >= m->base && | |
824 | addr < (m->base + m->size)) { | |
825 | addr += m->offset; | |
826 | break; | |
827 | } | |
828 | } | |
829 | return addr; | |
830 | } | |
831 | ||
832 | static int find_node(unsigned long addr) | |
833 | { | |
834 | int i; | |
835 | ||
836 | addr = ra_to_pa(addr); | |
837 | for (i = 0; i < num_node_masks; i++) { | |
838 | struct node_mem_mask *p = &node_masks[i]; | |
839 | ||
840 | if ((addr & p->mask) == p->val) | |
841 | return i; | |
842 | } | |
3dee9df5 | 843 | /* The following condition has been observed on LDOM guests.*/ |
844 | WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node" | |
845 | " rule. Some physical memory will be owned by node 0."); | |
846 | return 0; | |
919ee677 DM |
847 | } |
848 | ||
f9b18db3 | 849 | static u64 memblock_nid_range(u64 start, u64 end, int *nid) |
919ee677 DM |
850 | { |
851 | *nid = find_node(start); | |
852 | start += PAGE_SIZE; | |
853 | while (start < end) { | |
854 | int n = find_node(start); | |
855 | ||
856 | if (n != *nid) | |
857 | break; | |
858 | start += PAGE_SIZE; | |
859 | } | |
860 | ||
c918dcce DM |
861 | if (start > end) |
862 | start = end; | |
863 | ||
919ee677 DM |
864 | return start; |
865 | } | |
919ee677 DM |
866 | #endif |
867 | ||
868 | /* This must be invoked after performing all of the necessary | |
2a4814df | 869 | * memblock_set_node() calls for 'nid'. We need to be able to get |
919ee677 | 870 | * correct data from get_pfn_range_for_nid(). |
f1cfdb55 | 871 | */ |
919ee677 DM |
872 | static void __init allocate_node_data(int nid) |
873 | { | |
919ee677 | 874 | struct pglist_data *p; |
aa6f0790 | 875 | unsigned long start_pfn, end_pfn; |
919ee677 | 876 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
aa6f0790 PG |
877 | unsigned long paddr; |
878 | ||
9d1e2492 | 879 | paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); |
919ee677 DM |
880 | if (!paddr) { |
881 | prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); | |
882 | prom_halt(); | |
883 | } | |
884 | NODE_DATA(nid) = __va(paddr); | |
885 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | |
886 | ||
625d693e | 887 | NODE_DATA(nid)->node_id = nid; |
919ee677 DM |
888 | #endif |
889 | ||
890 | p = NODE_DATA(nid); | |
891 | ||
892 | get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); | |
893 | p->node_start_pfn = start_pfn; | |
894 | p->node_spanned_pages = end_pfn - start_pfn; | |
919ee677 DM |
895 | } |
896 | ||
897 | static void init_node_masks_nonnuma(void) | |
d1112018 | 898 | { |
48d37216 | 899 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
1da177e4 | 900 | int i; |
48d37216 | 901 | #endif |
1da177e4 | 902 | |
919ee677 | 903 | numadbg("Initializing tables for non-numa.\n"); |
6fc5bae7 | 904 | |
919ee677 DM |
905 | node_masks[0].mask = node_masks[0].val = 0; |
906 | num_node_masks = 1; | |
d1112018 | 907 | |
48d37216 | 908 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
919ee677 DM |
909 | for (i = 0; i < NR_CPUS; i++) |
910 | numa_cpu_lookup_table[i] = 0; | |
1da177e4 | 911 | |
fb1fece5 | 912 | cpumask_setall(&numa_cpumask_lookup_table[0]); |
48d37216 | 913 | #endif |
919ee677 DM |
914 | } |
915 | ||
916 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
917 | struct pglist_data *node_data[MAX_NUMNODES]; | |
918 | ||
919 | EXPORT_SYMBOL(numa_cpu_lookup_table); | |
920 | EXPORT_SYMBOL(numa_cpumask_lookup_table); | |
921 | EXPORT_SYMBOL(node_data); | |
922 | ||
923 | struct mdesc_mlgroup { | |
924 | u64 node; | |
925 | u64 latency; | |
926 | u64 match; | |
927 | u64 mask; | |
928 | }; | |
929 | static struct mdesc_mlgroup *mlgroups; | |
930 | static int num_mlgroups; | |
931 | ||
932 | static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, | |
933 | u32 cfg_handle) | |
934 | { | |
935 | u64 arc; | |
936 | ||
937 | mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { | |
938 | u64 target = mdesc_arc_target(md, arc); | |
939 | const u64 *val; | |
940 | ||
941 | val = mdesc_get_property(md, target, | |
942 | "cfg-handle", NULL); | |
943 | if (val && *val == cfg_handle) | |
944 | return 0; | |
945 | } | |
946 | return -ENODEV; | |
947 | } | |
948 | ||
949 | static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, | |
950 | u32 cfg_handle) | |
951 | { | |
952 | u64 arc, candidate, best_latency = ~(u64)0; | |
953 | ||
954 | candidate = MDESC_NODE_NULL; | |
955 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
956 | u64 target = mdesc_arc_target(md, arc); | |
957 | const char *name = mdesc_node_name(md, target); | |
958 | const u64 *val; | |
959 | ||
960 | if (strcmp(name, "pio-latency-group")) | |
961 | continue; | |
962 | ||
963 | val = mdesc_get_property(md, target, "latency", NULL); | |
964 | if (!val) | |
965 | continue; | |
966 | ||
967 | if (*val < best_latency) { | |
968 | candidate = target; | |
969 | best_latency = *val; | |
970 | } | |
971 | } | |
972 | ||
973 | if (candidate == MDESC_NODE_NULL) | |
974 | return -ENODEV; | |
975 | ||
976 | return scan_pio_for_cfg_handle(md, candidate, cfg_handle); | |
977 | } | |
978 | ||
979 | int of_node_to_nid(struct device_node *dp) | |
980 | { | |
981 | const struct linux_prom64_registers *regs; | |
982 | struct mdesc_handle *md; | |
983 | u32 cfg_handle; | |
984 | int count, nid; | |
985 | u64 grp; | |
986 | ||
072bd413 DM |
987 | /* This is the right thing to do on currently supported |
988 | * SUN4U NUMA platforms as well, as the PCI controller does | |
989 | * not sit behind any particular memory controller. | |
990 | */ | |
919ee677 DM |
991 | if (!mlgroups) |
992 | return -1; | |
993 | ||
994 | regs = of_get_property(dp, "reg", NULL); | |
995 | if (!regs) | |
996 | return -1; | |
997 | ||
998 | cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
999 | ||
1000 | md = mdesc_grab(); | |
1001 | ||
1002 | count = 0; | |
1003 | nid = -1; | |
1004 | mdesc_for_each_node_by_name(md, grp, "group") { | |
1005 | if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { | |
1006 | nid = count; | |
1007 | break; | |
1008 | } | |
1009 | count++; | |
1010 | } | |
1011 | ||
1012 | mdesc_release(md); | |
1013 | ||
1014 | return nid; | |
1015 | } | |
1016 | ||
01c45381 | 1017 | static void __init add_node_ranges(void) |
919ee677 | 1018 | { |
08b84798 | 1019 | struct memblock_region *reg; |
919ee677 | 1020 | |
08b84798 BH |
1021 | for_each_memblock(memory, reg) { |
1022 | unsigned long size = reg->size; | |
919ee677 DM |
1023 | unsigned long start, end; |
1024 | ||
08b84798 | 1025 | start = reg->base; |
919ee677 DM |
1026 | end = start + size; |
1027 | while (start < end) { | |
1028 | unsigned long this_end; | |
1029 | int nid; | |
1030 | ||
35a1f0bd | 1031 | this_end = memblock_nid_range(start, end, &nid); |
919ee677 | 1032 | |
2a4814df | 1033 | numadbg("Setting memblock NUMA node nid[%d] " |
919ee677 DM |
1034 | "start[%lx] end[%lx]\n", |
1035 | nid, start, this_end); | |
1036 | ||
e7e8de59 TC |
1037 | memblock_set_node(start, this_end - start, |
1038 | &memblock.memory, nid); | |
919ee677 DM |
1039 | start = this_end; |
1040 | } | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | static int __init grab_mlgroups(struct mdesc_handle *md) | |
1045 | { | |
1046 | unsigned long paddr; | |
1047 | int count = 0; | |
1048 | u64 node; | |
1049 | ||
1050 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") | |
1051 | count++; | |
1052 | if (!count) | |
1053 | return -ENOENT; | |
1054 | ||
95f72d1e | 1055 | paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup), |
919ee677 DM |
1056 | SMP_CACHE_BYTES); |
1057 | if (!paddr) | |
1058 | return -ENOMEM; | |
1059 | ||
1060 | mlgroups = __va(paddr); | |
1061 | num_mlgroups = count; | |
1062 | ||
1063 | count = 0; | |
1064 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") { | |
1065 | struct mdesc_mlgroup *m = &mlgroups[count++]; | |
1066 | const u64 *val; | |
1067 | ||
1068 | m->node = node; | |
1069 | ||
1070 | val = mdesc_get_property(md, node, "latency", NULL); | |
1071 | m->latency = *val; | |
1072 | val = mdesc_get_property(md, node, "address-match", NULL); | |
1073 | m->match = *val; | |
1074 | val = mdesc_get_property(md, node, "address-mask", NULL); | |
1075 | m->mask = *val; | |
1076 | ||
90181136 SR |
1077 | numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " |
1078 | "match[%llx] mask[%llx]\n", | |
919ee677 DM |
1079 | count - 1, m->node, m->latency, m->match, m->mask); |
1080 | } | |
1081 | ||
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | static int __init grab_mblocks(struct mdesc_handle *md) | |
1086 | { | |
1087 | unsigned long paddr; | |
1088 | int count = 0; | |
1089 | u64 node; | |
1090 | ||
1091 | mdesc_for_each_node_by_name(md, node, "mblock") | |
1092 | count++; | |
1093 | if (!count) | |
1094 | return -ENOENT; | |
1095 | ||
95f72d1e | 1096 | paddr = memblock_alloc(count * sizeof(struct mdesc_mblock), |
919ee677 DM |
1097 | SMP_CACHE_BYTES); |
1098 | if (!paddr) | |
1099 | return -ENOMEM; | |
1100 | ||
1101 | mblocks = __va(paddr); | |
1102 | num_mblocks = count; | |
1103 | ||
1104 | count = 0; | |
1105 | mdesc_for_each_node_by_name(md, node, "mblock") { | |
1106 | struct mdesc_mblock *m = &mblocks[count++]; | |
1107 | const u64 *val; | |
1108 | ||
1109 | val = mdesc_get_property(md, node, "base", NULL); | |
1110 | m->base = *val; | |
1111 | val = mdesc_get_property(md, node, "size", NULL); | |
1112 | m->size = *val; | |
1113 | val = mdesc_get_property(md, node, | |
1114 | "address-congruence-offset", NULL); | |
771a37ff | 1115 | |
1116 | /* The address-congruence-offset property is optional. | |
1117 | * Explicity zero it be identifty this. | |
1118 | */ | |
1119 | if (val) | |
1120 | m->offset = *val; | |
1121 | else | |
1122 | m->offset = 0UL; | |
919ee677 | 1123 | |
90181136 | 1124 | numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", |
919ee677 DM |
1125 | count - 1, m->base, m->size, m->offset); |
1126 | } | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
1131 | static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, | |
1132 | u64 grp, cpumask_t *mask) | |
1133 | { | |
1134 | u64 arc; | |
1135 | ||
fb1fece5 | 1136 | cpumask_clear(mask); |
919ee677 DM |
1137 | |
1138 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { | |
1139 | u64 target = mdesc_arc_target(md, arc); | |
1140 | const char *name = mdesc_node_name(md, target); | |
1141 | const u64 *id; | |
1142 | ||
1143 | if (strcmp(name, "cpu")) | |
1144 | continue; | |
1145 | id = mdesc_get_property(md, target, "id", NULL); | |
e305cb8f | 1146 | if (*id < nr_cpu_ids) |
fb1fece5 | 1147 | cpumask_set_cpu(*id, mask); |
919ee677 DM |
1148 | } |
1149 | } | |
1150 | ||
1151 | static struct mdesc_mlgroup * __init find_mlgroup(u64 node) | |
1152 | { | |
1153 | int i; | |
1154 | ||
1155 | for (i = 0; i < num_mlgroups; i++) { | |
1156 | struct mdesc_mlgroup *m = &mlgroups[i]; | |
1157 | if (m->node == node) | |
1158 | return m; | |
1159 | } | |
1160 | return NULL; | |
1161 | } | |
1162 | ||
1163 | static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, | |
1164 | int index) | |
1165 | { | |
1166 | struct mdesc_mlgroup *candidate = NULL; | |
1167 | u64 arc, best_latency = ~(u64)0; | |
1168 | struct node_mem_mask *n; | |
1169 | ||
1170 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1171 | u64 target = mdesc_arc_target(md, arc); | |
1172 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1173 | if (!m) | |
1174 | continue; | |
1175 | if (m->latency < best_latency) { | |
1176 | candidate = m; | |
1177 | best_latency = m->latency; | |
1178 | } | |
1179 | } | |
1180 | if (!candidate) | |
1181 | return -ENOENT; | |
1182 | ||
1183 | if (num_node_masks != index) { | |
1184 | printk(KERN_ERR "Inconsistent NUMA state, " | |
1185 | "index[%d] != num_node_masks[%d]\n", | |
1186 | index, num_node_masks); | |
1187 | return -EINVAL; | |
1188 | } | |
1189 | ||
1190 | n = &node_masks[num_node_masks++]; | |
1191 | ||
1192 | n->mask = candidate->mask; | |
1193 | n->val = candidate->match; | |
1da177e4 | 1194 | |
90181136 | 1195 | numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n", |
919ee677 | 1196 | index, n->mask, n->val, candidate->latency); |
1da177e4 | 1197 | |
919ee677 DM |
1198 | return 0; |
1199 | } | |
1200 | ||
1201 | static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, | |
1202 | int index) | |
1203 | { | |
1204 | cpumask_t mask; | |
1205 | int cpu; | |
1206 | ||
1207 | numa_parse_mdesc_group_cpus(md, grp, &mask); | |
1208 | ||
fb1fece5 | 1209 | for_each_cpu(cpu, &mask) |
919ee677 | 1210 | numa_cpu_lookup_table[cpu] = index; |
fb1fece5 | 1211 | cpumask_copy(&numa_cpumask_lookup_table[index], &mask); |
919ee677 DM |
1212 | |
1213 | if (numa_debug) { | |
1214 | printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); | |
fb1fece5 | 1215 | for_each_cpu(cpu, &mask) |
919ee677 DM |
1216 | printk("%d ", cpu); |
1217 | printk("]\n"); | |
1218 | } | |
1219 | ||
1220 | return numa_attach_mlgroup(md, grp, index); | |
1221 | } | |
1222 | ||
1223 | static int __init numa_parse_mdesc(void) | |
1224 | { | |
1225 | struct mdesc_handle *md = mdesc_grab(); | |
1226 | int i, err, count; | |
1227 | u64 node; | |
1228 | ||
1229 | node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); | |
1230 | if (node == MDESC_NODE_NULL) { | |
1231 | mdesc_release(md); | |
1232 | return -ENOENT; | |
1233 | } | |
1234 | ||
1235 | err = grab_mblocks(md); | |
1236 | if (err < 0) | |
1237 | goto out; | |
1238 | ||
1239 | err = grab_mlgroups(md); | |
1240 | if (err < 0) | |
1241 | goto out; | |
1242 | ||
1243 | count = 0; | |
1244 | mdesc_for_each_node_by_name(md, node, "group") { | |
1245 | err = numa_parse_mdesc_group(md, node, count); | |
1246 | if (err < 0) | |
1247 | break; | |
1248 | count++; | |
1249 | } | |
1250 | ||
1251 | add_node_ranges(); | |
1252 | ||
1253 | for (i = 0; i < num_node_masks; i++) { | |
1254 | allocate_node_data(i); | |
1255 | node_set_online(i); | |
1256 | } | |
1257 | ||
1258 | err = 0; | |
1259 | out: | |
1260 | mdesc_release(md); | |
1261 | return err; | |
1262 | } | |
1263 | ||
072bd413 DM |
1264 | static int __init numa_parse_jbus(void) |
1265 | { | |
1266 | unsigned long cpu, index; | |
1267 | ||
1268 | /* NUMA node id is encoded in bits 36 and higher, and there is | |
1269 | * a 1-to-1 mapping from CPU ID to NUMA node ID. | |
1270 | */ | |
1271 | index = 0; | |
1272 | for_each_present_cpu(cpu) { | |
1273 | numa_cpu_lookup_table[cpu] = index; | |
fb1fece5 | 1274 | cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); |
072bd413 DM |
1275 | node_masks[index].mask = ~((1UL << 36UL) - 1UL); |
1276 | node_masks[index].val = cpu << 36UL; | |
1277 | ||
1278 | index++; | |
1279 | } | |
1280 | num_node_masks = index; | |
1281 | ||
1282 | add_node_ranges(); | |
1283 | ||
1284 | for (index = 0; index < num_node_masks; index++) { | |
1285 | allocate_node_data(index); | |
1286 | node_set_online(index); | |
1287 | } | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
919ee677 DM |
1292 | static int __init numa_parse_sun4u(void) |
1293 | { | |
072bd413 DM |
1294 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1295 | unsigned long ver; | |
1296 | ||
1297 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
1298 | if ((ver >> 32UL) == __JALAPENO_ID || | |
1299 | (ver >> 32UL) == __SERRANO_ID) | |
1300 | return numa_parse_jbus(); | |
1301 | } | |
919ee677 DM |
1302 | return -1; |
1303 | } | |
1304 | ||
1305 | static int __init bootmem_init_numa(void) | |
1306 | { | |
1307 | int err = -1; | |
1308 | ||
1309 | numadbg("bootmem_init_numa()\n"); | |
1310 | ||
1311 | if (numa_enabled) { | |
1312 | if (tlb_type == hypervisor) | |
1313 | err = numa_parse_mdesc(); | |
1314 | else | |
1315 | err = numa_parse_sun4u(); | |
1316 | } | |
1317 | return err; | |
1318 | } | |
1319 | ||
1320 | #else | |
1da177e4 | 1321 | |
919ee677 DM |
1322 | static int bootmem_init_numa(void) |
1323 | { | |
1324 | return -1; | |
1325 | } | |
1326 | ||
1327 | #endif | |
1328 | ||
1329 | static void __init bootmem_init_nonnuma(void) | |
1330 | { | |
95f72d1e YL |
1331 | unsigned long top_of_ram = memblock_end_of_DRAM(); |
1332 | unsigned long total_ram = memblock_phys_mem_size(); | |
919ee677 DM |
1333 | |
1334 | numadbg("bootmem_init_nonnuma()\n"); | |
1335 | ||
1336 | printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", | |
1337 | top_of_ram, total_ram); | |
1338 | printk(KERN_INFO "Memory hole size: %ldMB\n", | |
1339 | (top_of_ram - total_ram) >> 20); | |
1340 | ||
1341 | init_node_masks_nonnuma(); | |
e7e8de59 | 1342 | memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0); |
919ee677 | 1343 | allocate_node_data(0); |
919ee677 DM |
1344 | node_set_online(0); |
1345 | } | |
1346 | ||
919ee677 DM |
1347 | static unsigned long __init bootmem_init(unsigned long phys_base) |
1348 | { | |
1349 | unsigned long end_pfn; | |
919ee677 | 1350 | |
95f72d1e | 1351 | end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; |
919ee677 DM |
1352 | max_pfn = max_low_pfn = end_pfn; |
1353 | min_low_pfn = (phys_base >> PAGE_SHIFT); | |
1354 | ||
1355 | if (bootmem_init_numa() < 0) | |
1356 | bootmem_init_nonnuma(); | |
1357 | ||
625d693e DM |
1358 | /* Dump memblock with node info. */ |
1359 | memblock_dump_all(); | |
919ee677 | 1360 | |
625d693e | 1361 | /* XXX cpu notifier XXX */ |
d1112018 | 1362 | |
625d693e | 1363 | sparse_memory_present_with_active_regions(MAX_NUMNODES); |
d1112018 DM |
1364 | sparse_init(); |
1365 | ||
1da177e4 LT |
1366 | return end_pfn; |
1367 | } | |
1368 | ||
9cc3a1ac DM |
1369 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1370 | static int pall_ents __initdata; | |
1371 | ||
56425306 | 1372 | #ifdef CONFIG_DEBUG_PAGEALLOC |
896aef43 SR |
1373 | static unsigned long __ref kernel_map_range(unsigned long pstart, |
1374 | unsigned long pend, pgprot_t prot) | |
56425306 DM |
1375 | { |
1376 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1377 | unsigned long vend = PAGE_OFFSET + pend; | |
1378 | unsigned long alloc_bytes = 0UL; | |
1379 | ||
1380 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1381 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1382 | vstart, vend); |
1383 | prom_halt(); | |
1384 | } | |
1385 | ||
1386 | while (vstart < vend) { | |
1387 | unsigned long this_end, paddr = __pa(vstart); | |
1388 | pgd_t *pgd = pgd_offset_k(vstart); | |
1389 | pud_t *pud; | |
1390 | pmd_t *pmd; | |
1391 | pte_t *pte; | |
1392 | ||
1393 | pud = pud_offset(pgd, vstart); | |
1394 | if (pud_none(*pud)) { | |
1395 | pmd_t *new; | |
1396 | ||
1397 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1398 | alloc_bytes += PAGE_SIZE; | |
1399 | pud_populate(&init_mm, pud, new); | |
1400 | } | |
1401 | ||
1402 | pmd = pmd_offset(pud, vstart); | |
1403 | if (!pmd_present(*pmd)) { | |
1404 | pte_t *new; | |
1405 | ||
1406 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1407 | alloc_bytes += PAGE_SIZE; | |
1408 | pmd_populate_kernel(&init_mm, pmd, new); | |
1409 | } | |
1410 | ||
1411 | pte = pte_offset_kernel(pmd, vstart); | |
1412 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1413 | if (this_end > vend) | |
1414 | this_end = vend; | |
1415 | ||
1416 | while (vstart < this_end) { | |
1417 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1418 | ||
1419 | vstart += PAGE_SIZE; | |
1420 | paddr += PAGE_SIZE; | |
1421 | pte++; | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | return alloc_bytes; | |
1426 | } | |
1427 | ||
56425306 | 1428 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac DM |
1429 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1430 | ||
4f93d21d | 1431 | static void __init kpte_set_val(unsigned long index, unsigned long val) |
9cc3a1ac | 1432 | { |
4f93d21d | 1433 | unsigned long *ptr = kpte_linear_bitmap; |
9cc3a1ac | 1434 | |
4f93d21d DM |
1435 | val <<= ((index % (BITS_PER_LONG / 2)) * 2); |
1436 | ptr += (index / (BITS_PER_LONG / 2)); | |
9cc3a1ac | 1437 | |
4f93d21d DM |
1438 | *ptr |= val; |
1439 | } | |
f7c00338 | 1440 | |
4f93d21d DM |
1441 | static const unsigned long kpte_shift_min = 28; /* 256MB */ |
1442 | static const unsigned long kpte_shift_max = 34; /* 16GB */ | |
1443 | static const unsigned long kpte_shift_incr = 3; | |
9cc3a1ac | 1444 | |
4f93d21d DM |
1445 | static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end, |
1446 | unsigned long shift) | |
1447 | { | |
1448 | unsigned long size = (1UL << shift); | |
1449 | unsigned long mask = (size - 1UL); | |
1450 | unsigned long remains = end - start; | |
1451 | unsigned long val; | |
9cc3a1ac | 1452 | |
4f93d21d DM |
1453 | if (remains < size || (start & mask)) |
1454 | return start; | |
9cc3a1ac | 1455 | |
4f93d21d DM |
1456 | /* VAL maps: |
1457 | * | |
1458 | * shift 28 --> kern_linear_pte_xor index 1 | |
1459 | * shift 31 --> kern_linear_pte_xor index 2 | |
1460 | * shift 34 --> kern_linear_pte_xor index 3 | |
1461 | */ | |
1462 | val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1; | |
1463 | ||
1464 | remains &= ~mask; | |
1465 | if (shift != kpte_shift_max) | |
1466 | remains = size; | |
1467 | ||
1468 | while (remains) { | |
1469 | unsigned long index = start >> kpte_shift_min; | |
1470 | ||
1471 | kpte_set_val(index, val); | |
1472 | ||
1473 | start += 1UL << kpte_shift_min; | |
1474 | remains -= 1UL << kpte_shift_min; | |
1475 | } | |
1476 | ||
1477 | return start; | |
1478 | } | |
1479 | ||
1480 | static void __init mark_kpte_bitmap(unsigned long start, unsigned long end) | |
1481 | { | |
1482 | unsigned long smallest_size, smallest_mask; | |
1483 | unsigned long s; | |
1484 | ||
1485 | smallest_size = (1UL << kpte_shift_min); | |
1486 | smallest_mask = (smallest_size - 1UL); | |
1487 | ||
1488 | while (start < end) { | |
1489 | unsigned long orig_start = start; | |
1490 | ||
1491 | for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) { | |
1492 | start = kpte_mark_using_shift(start, end, s); | |
1493 | ||
1494 | if (start != orig_start) | |
1495 | break; | |
9cc3a1ac | 1496 | } |
4f93d21d DM |
1497 | |
1498 | if (start == orig_start) | |
1499 | start = (start + smallest_size) & ~smallest_mask; | |
9cc3a1ac DM |
1500 | } |
1501 | } | |
56425306 | 1502 | |
8f361453 | 1503 | static void __init init_kpte_bitmap(void) |
56425306 | 1504 | { |
9cc3a1ac | 1505 | unsigned long i; |
13edad7a DM |
1506 | |
1507 | for (i = 0; i < pall_ents; i++) { | |
56425306 DM |
1508 | unsigned long phys_start, phys_end; |
1509 | ||
13edad7a DM |
1510 | phys_start = pall[i].phys_addr; |
1511 | phys_end = phys_start + pall[i].reg_size; | |
9cc3a1ac DM |
1512 | |
1513 | mark_kpte_bitmap(phys_start, phys_end); | |
8f361453 DM |
1514 | } |
1515 | } | |
9cc3a1ac | 1516 | |
8f361453 DM |
1517 | static void __init kernel_physical_mapping_init(void) |
1518 | { | |
9cc3a1ac | 1519 | #ifdef CONFIG_DEBUG_PAGEALLOC |
8f361453 DM |
1520 | unsigned long i, mem_alloced = 0UL; |
1521 | ||
1522 | for (i = 0; i < pall_ents; i++) { | |
1523 | unsigned long phys_start, phys_end; | |
1524 | ||
1525 | phys_start = pall[i].phys_addr; | |
1526 | phys_end = phys_start + pall[i].reg_size; | |
1527 | ||
56425306 DM |
1528 | mem_alloced += kernel_map_range(phys_start, phys_end, |
1529 | PAGE_KERNEL); | |
56425306 DM |
1530 | } |
1531 | ||
1532 | printk("Allocated %ld bytes for kernel page tables.\n", | |
1533 | mem_alloced); | |
1534 | ||
1535 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1536 | flushi(&kvmap_linear_patch[0]); | |
1537 | ||
1538 | __flush_tlb_all(); | |
9cc3a1ac | 1539 | #endif |
56425306 DM |
1540 | } |
1541 | ||
9cc3a1ac | 1542 | #ifdef CONFIG_DEBUG_PAGEALLOC |
56425306 DM |
1543 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1544 | { | |
1545 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1546 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1547 | ||
1548 | kernel_map_range(phys_start, phys_end, | |
1549 | (enable ? PAGE_KERNEL : __pgprot(0))); | |
1550 | ||
74bf4312 DM |
1551 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1552 | PAGE_OFFSET + phys_end); | |
1553 | ||
56425306 DM |
1554 | /* we should perform an IPI and flush all tlbs, |
1555 | * but that can deadlock->flush only current cpu. | |
1556 | */ | |
1557 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1558 | PAGE_OFFSET + phys_end); | |
1559 | } | |
1560 | #endif | |
1561 | ||
10147570 DM |
1562 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1563 | { | |
0836a0eb DM |
1564 | int i; |
1565 | ||
13edad7a DM |
1566 | for (i = 0; i < pavail_ents; i++) { |
1567 | if (pavail[i].reg_size >= size) | |
1568 | return pavail[i].phys_addr; | |
0836a0eb DM |
1569 | } |
1570 | ||
13edad7a | 1571 | return ~0UL; |
0836a0eb DM |
1572 | } |
1573 | ||
b2d43834 DM |
1574 | unsigned long PAGE_OFFSET; |
1575 | EXPORT_SYMBOL(PAGE_OFFSET); | |
1576 | ||
1577 | static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits) | |
1578 | { | |
1579 | unsigned long final_shift; | |
1580 | unsigned int val = *insn; | |
1581 | unsigned int cnt; | |
1582 | ||
1583 | /* We are patching in ilog2(max_supported_phys_address), and | |
1584 | * we are doing so in a manner similar to a relocation addend. | |
1585 | * That is, we are adding the shift value to whatever value | |
1586 | * is in the shift instruction count field already. | |
1587 | */ | |
1588 | cnt = (val & 0x3f); | |
1589 | val &= ~0x3f; | |
1590 | ||
1591 | /* If we are trying to shift >= 64 bits, clear the destination | |
1592 | * register. This can happen when phys_bits ends up being equal | |
1593 | * to MAX_PHYS_ADDRESS_BITS. | |
1594 | */ | |
1595 | final_shift = (cnt + (64 - phys_bits)); | |
1596 | if (final_shift >= 64) { | |
1597 | unsigned int rd = (val >> 25) & 0x1f; | |
1598 | ||
1599 | val = 0x80100000 | (rd << 25); | |
1600 | } else { | |
1601 | val |= final_shift; | |
1602 | } | |
1603 | *insn = val; | |
1604 | ||
1605 | __asm__ __volatile__("flush %0" | |
1606 | : /* no outputs */ | |
1607 | : "r" (insn)); | |
1608 | } | |
1609 | ||
1610 | static void __init page_offset_shift_patch(unsigned long phys_bits) | |
1611 | { | |
1612 | extern unsigned int __page_offset_shift_patch; | |
1613 | extern unsigned int __page_offset_shift_patch_end; | |
1614 | unsigned int *p; | |
1615 | ||
1616 | p = &__page_offset_shift_patch; | |
1617 | while (p < &__page_offset_shift_patch_end) { | |
1618 | unsigned int *insn = (unsigned int *)(unsigned long)*p; | |
1619 | ||
1620 | page_offset_shift_patch_one(insn, phys_bits); | |
1621 | ||
1622 | p++; | |
1623 | } | |
1624 | } | |
1625 | ||
1626 | static void __init setup_page_offset(void) | |
1627 | { | |
1628 | unsigned long max_phys_bits = 40; | |
1629 | ||
1630 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
1631 | max_phys_bits = 42; | |
1632 | } else if (tlb_type == hypervisor) { | |
1633 | switch (sun4v_chip_type) { | |
1634 | case SUN4V_CHIP_NIAGARA1: | |
1635 | case SUN4V_CHIP_NIAGARA2: | |
1636 | max_phys_bits = 39; | |
1637 | break; | |
1638 | case SUN4V_CHIP_NIAGARA3: | |
1639 | max_phys_bits = 43; | |
1640 | break; | |
1641 | case SUN4V_CHIP_NIAGARA4: | |
1642 | case SUN4V_CHIP_NIAGARA5: | |
1643 | case SUN4V_CHIP_SPARC64X: | |
1644 | default: | |
1645 | max_phys_bits = 47; | |
1646 | break; | |
1647 | } | |
1648 | } | |
1649 | ||
1650 | if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { | |
1651 | prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", | |
1652 | max_phys_bits); | |
1653 | prom_halt(); | |
1654 | } | |
1655 | ||
1656 | PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits); | |
1657 | ||
1658 | pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", | |
1659 | PAGE_OFFSET, max_phys_bits); | |
1660 | ||
1661 | page_offset_shift_patch(max_phys_bits); | |
1662 | } | |
1663 | ||
517af332 DM |
1664 | static void __init tsb_phys_patch(void) |
1665 | { | |
d257d5da | 1666 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
1667 | struct tsb_phys_patch_entry *p; |
1668 | ||
d257d5da DM |
1669 | pquad = &__tsb_ldquad_phys_patch; |
1670 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
1671 | unsigned long addr = pquad->addr; | |
1672 | ||
1673 | if (tlb_type == hypervisor) | |
1674 | *(unsigned int *) addr = pquad->sun4v_insn; | |
1675 | else | |
1676 | *(unsigned int *) addr = pquad->sun4u_insn; | |
1677 | wmb(); | |
1678 | __asm__ __volatile__("flush %0" | |
1679 | : /* no outputs */ | |
1680 | : "r" (addr)); | |
1681 | ||
1682 | pquad++; | |
1683 | } | |
1684 | ||
517af332 DM |
1685 | p = &__tsb_phys_patch; |
1686 | while (p < &__tsb_phys_patch_end) { | |
1687 | unsigned long addr = p->addr; | |
1688 | ||
1689 | *(unsigned int *) addr = p->insn; | |
1690 | wmb(); | |
1691 | __asm__ __volatile__("flush %0" | |
1692 | : /* no outputs */ | |
1693 | : "r" (addr)); | |
1694 | ||
1695 | p++; | |
1696 | } | |
1697 | } | |
1698 | ||
490384e7 | 1699 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
1700 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1701 | #define NUM_KTSB_DESCR 2 | |
1702 | #else | |
1703 | #define NUM_KTSB_DESCR 1 | |
1704 | #endif | |
1705 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 DM |
1706 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
1707 | ||
9076d0e7 DM |
1708 | static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) |
1709 | { | |
1710 | pa >>= KTSB_PHYS_SHIFT; | |
1711 | ||
1712 | while (start < end) { | |
1713 | unsigned int *ia = (unsigned int *)(unsigned long)*start; | |
1714 | ||
1715 | ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10); | |
1716 | __asm__ __volatile__("flush %0" : : "r" (ia)); | |
1717 | ||
1718 | ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff); | |
1719 | __asm__ __volatile__("flush %0" : : "r" (ia + 1)); | |
1720 | ||
1721 | start++; | |
1722 | } | |
1723 | } | |
1724 | ||
1725 | static void ktsb_phys_patch(void) | |
1726 | { | |
1727 | extern unsigned int __swapper_tsb_phys_patch; | |
1728 | extern unsigned int __swapper_tsb_phys_patch_end; | |
9076d0e7 DM |
1729 | unsigned long ktsb_pa; |
1730 | ||
1731 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); | |
1732 | patch_one_ktsb_phys(&__swapper_tsb_phys_patch, | |
1733 | &__swapper_tsb_phys_patch_end, ktsb_pa); | |
1734 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
0785a8e8 DM |
1735 | { |
1736 | extern unsigned int __swapper_4m_tsb_phys_patch; | |
1737 | extern unsigned int __swapper_4m_tsb_phys_patch_end; | |
9076d0e7 DM |
1738 | ktsb_pa = (kern_base + |
1739 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1740 | patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, | |
1741 | &__swapper_4m_tsb_phys_patch_end, ktsb_pa); | |
0785a8e8 | 1742 | } |
9076d0e7 DM |
1743 | #endif |
1744 | } | |
1745 | ||
490384e7 DM |
1746 | static void __init sun4v_ktsb_init(void) |
1747 | { | |
1748 | unsigned long ktsb_pa; | |
1749 | ||
d7744a09 | 1750 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
1751 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
1752 | ||
1753 | switch (PAGE_SIZE) { | |
1754 | case 8 * 1024: | |
1755 | default: | |
1756 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
1757 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
1758 | break; | |
1759 | ||
1760 | case 64 * 1024: | |
1761 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
1762 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
1763 | break; | |
1764 | ||
1765 | case 512 * 1024: | |
1766 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
1767 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
1768 | break; | |
1769 | ||
1770 | case 4 * 1024 * 1024: | |
1771 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1772 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
1773 | break; | |
6cb79b3f | 1774 | } |
490384e7 | 1775 | |
3f19a84e | 1776 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
1777 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
1778 | ktsb_descr[0].ctx_idx = 0; | |
1779 | ktsb_descr[0].tsb_base = ktsb_pa; | |
1780 | ktsb_descr[0].resv = 0; | |
1781 | ||
d1acb421 | 1782 | #ifndef CONFIG_DEBUG_PAGEALLOC |
4f93d21d | 1783 | /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ |
d7744a09 DM |
1784 | ktsb_pa = (kern_base + |
1785 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1786 | ||
1787 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
c69ad0a3 DM |
1788 | ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | |
1789 | HV_PGSZ_MASK_256MB | | |
1790 | HV_PGSZ_MASK_2GB | | |
1791 | HV_PGSZ_MASK_16GB) & | |
1792 | cpu_pgsz_mask); | |
d7744a09 DM |
1793 | ktsb_descr[1].assoc = 1; |
1794 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
1795 | ktsb_descr[1].ctx_idx = 0; | |
1796 | ktsb_descr[1].tsb_base = ktsb_pa; | |
1797 | ktsb_descr[1].resv = 0; | |
d1acb421 | 1798 | #endif |
490384e7 DM |
1799 | } |
1800 | ||
2066aadd | 1801 | void sun4v_ktsb_register(void) |
490384e7 | 1802 | { |
7db35f31 | 1803 | unsigned long pa, ret; |
490384e7 DM |
1804 | |
1805 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
1806 | ||
7db35f31 DM |
1807 | ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); |
1808 | if (ret != 0) { | |
1809 | prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " | |
1810 | "errors with %lx\n", pa, ret); | |
1811 | prom_halt(); | |
1812 | } | |
490384e7 DM |
1813 | } |
1814 | ||
c69ad0a3 DM |
1815 | static void __init sun4u_linear_pte_xor_finalize(void) |
1816 | { | |
1817 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
1818 | /* This is where we would add Panther support for | |
1819 | * 32MB and 256MB pages. | |
1820 | */ | |
1821 | #endif | |
1822 | } | |
1823 | ||
1824 | static void __init sun4v_linear_pte_xor_finalize(void) | |
1825 | { | |
1826 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
1827 | if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { | |
1828 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ | |
922631b9 | 1829 | PAGE_OFFSET; |
c69ad0a3 DM |
1830 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
1831 | _PAGE_P_4V | _PAGE_W_4V); | |
1832 | } else { | |
1833 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
1834 | } | |
1835 | ||
1836 | if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { | |
1837 | kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ | |
922631b9 | 1838 | PAGE_OFFSET; |
c69ad0a3 DM |
1839 | kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
1840 | _PAGE_P_4V | _PAGE_W_4V); | |
1841 | } else { | |
1842 | kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; | |
1843 | } | |
1844 | ||
1845 | if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { | |
1846 | kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ | |
922631b9 | 1847 | PAGE_OFFSET; |
c69ad0a3 DM |
1848 | kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
1849 | _PAGE_P_4V | _PAGE_W_4V); | |
1850 | } else { | |
1851 | kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; | |
1852 | } | |
1853 | #endif | |
1854 | } | |
1855 | ||
1da177e4 LT |
1856 | /* paging_init() sets up the page tables */ |
1857 | ||
1da177e4 | 1858 | static unsigned long last_valid_pfn; |
2b77933c | 1859 | pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
1da177e4 | 1860 | |
c4bce90e DM |
1861 | static void sun4u_pgprot_init(void); |
1862 | static void sun4v_pgprot_init(void); | |
1863 | ||
1da177e4 LT |
1864 | void __init paging_init(void) |
1865 | { | |
919ee677 | 1866 | unsigned long end_pfn, shift, phys_base; |
0836a0eb | 1867 | unsigned long real_end, i; |
aa6f0790 | 1868 | int node; |
0836a0eb | 1869 | |
b2d43834 DM |
1870 | setup_page_offset(); |
1871 | ||
22adb358 DM |
1872 | /* These build time checkes make sure that the dcache_dirty_cpu() |
1873 | * page->flags usage will work. | |
1874 | * | |
1875 | * When a page gets marked as dcache-dirty, we store the | |
1876 | * cpu number starting at bit 32 in the page->flags. Also, | |
1877 | * functions like clear_dcache_dirty_cpu use the cpu mask | |
1878 | * in 13-bit signed-immediate instruction fields. | |
1879 | */ | |
9223b419 CL |
1880 | |
1881 | /* | |
1882 | * Page flags must not reach into upper 32 bits that are used | |
1883 | * for the cpu number | |
1884 | */ | |
1885 | BUILD_BUG_ON(NR_PAGEFLAGS > 32); | |
1886 | ||
1887 | /* | |
1888 | * The bit fields placed in the high range must not reach below | |
1889 | * the 32 bit boundary. Otherwise we cannot place the cpu field | |
1890 | * at the 32 bit boundary. | |
1891 | */ | |
22adb358 | 1892 | BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + |
9223b419 CL |
1893 | ilog2(roundup_pow_of_two(NR_CPUS)) > 32); |
1894 | ||
22adb358 DM |
1895 | BUILD_BUG_ON(NR_CPUS > 4096); |
1896 | ||
0eef331a | 1897 | kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; |
481295f9 DM |
1898 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; |
1899 | ||
d7744a09 | 1900 | /* Invalidate both kernel TSBs. */ |
8b234274 | 1901 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 1902 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 1903 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 1904 | #endif |
8b234274 | 1905 | |
c4bce90e DM |
1906 | if (tlb_type == hypervisor) |
1907 | sun4v_pgprot_init(); | |
1908 | else | |
1909 | sun4u_pgprot_init(); | |
1910 | ||
d257d5da | 1911 | if (tlb_type == cheetah_plus || |
9076d0e7 | 1912 | tlb_type == hypervisor) { |
517af332 | 1913 | tsb_phys_patch(); |
9076d0e7 DM |
1914 | ktsb_phys_patch(); |
1915 | } | |
517af332 | 1916 | |
c69ad0a3 | 1917 | if (tlb_type == hypervisor) |
d257d5da DM |
1918 | sun4v_patch_tlb_handlers(); |
1919 | ||
a94a172d DM |
1920 | /* Find available physical memory... |
1921 | * | |
1922 | * Read it twice in order to work around a bug in openfirmware. | |
1923 | * The call to grab this table itself can cause openfirmware to | |
1924 | * allocate memory, which in turn can take away some space from | |
1925 | * the list of available memory. Reading it twice makes sure | |
1926 | * we really do get the final value. | |
1927 | */ | |
1928 | read_obp_translations(); | |
1929 | read_obp_memory("reg", &pall[0], &pall_ents); | |
1930 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
13edad7a | 1931 | read_obp_memory("available", &pavail[0], &pavail_ents); |
0836a0eb DM |
1932 | |
1933 | phys_base = 0xffffffffffffffffUL; | |
3b2a7e23 | 1934 | for (i = 0; i < pavail_ents; i++) { |
13edad7a | 1935 | phys_base = min(phys_base, pavail[i].phys_addr); |
95f72d1e | 1936 | memblock_add(pavail[i].phys_addr, pavail[i].reg_size); |
3b2a7e23 DM |
1937 | } |
1938 | ||
95f72d1e | 1939 | memblock_reserve(kern_base, kern_size); |
0836a0eb | 1940 | |
4e82c9a6 DM |
1941 | find_ramdisk(phys_base); |
1942 | ||
95f72d1e | 1943 | memblock_enforce_memory_limit(cmdline_memory_size); |
25b0c659 | 1944 | |
1aadc056 | 1945 | memblock_allow_resize(); |
95f72d1e | 1946 | memblock_dump_all(); |
3b2a7e23 | 1947 | |
1da177e4 LT |
1948 | set_bit(0, mmu_context_bmap); |
1949 | ||
2bdb3cb2 DM |
1950 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
1951 | ||
1da177e4 | 1952 | real_end = (unsigned long)_end; |
0eef331a | 1953 | num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); |
64658743 DM |
1954 | printk("Kernel: Using %d locked TLB entries for main kernel image.\n", |
1955 | num_kernel_image_mappings); | |
2bdb3cb2 DM |
1956 | |
1957 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
1958 | * work. |
1959 | */ | |
1960 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
1961 | ||
56425306 | 1962 | memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir)); |
1da177e4 LT |
1963 | |
1964 | /* Now can init the kernel/bad page tables. */ | |
1965 | pud_set(pud_offset(&swapper_pg_dir[0], 0), | |
56425306 | 1966 | swapper_low_pmd_dir + (shift / sizeof(pgd_t))); |
1da177e4 | 1967 | |
c9c10830 | 1968 | inherit_prom_mappings(); |
5085b4a5 | 1969 | |
8f361453 DM |
1970 | init_kpte_bitmap(); |
1971 | ||
a8b900d8 DM |
1972 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
1973 | setup_tba(); | |
1da177e4 | 1974 | |
c9c10830 | 1975 | __flush_tlb_all(); |
9ad98c5b | 1976 | |
ad072004 | 1977 | prom_build_devicetree(); |
b696fdc2 | 1978 | of_populate_present_mask(); |
b99c6ebe DM |
1979 | #ifndef CONFIG_SMP |
1980 | of_fill_in_cpu_data(); | |
1981 | #endif | |
ad072004 | 1982 | |
890db403 | 1983 | if (tlb_type == hypervisor) { |
4a283339 | 1984 | sun4v_mdesc_init(); |
6ac5c610 | 1985 | mdesc_populate_present_mask(cpu_all_mask); |
b99c6ebe DM |
1986 | #ifndef CONFIG_SMP |
1987 | mdesc_fill_in_cpu_data(cpu_all_mask); | |
1988 | #endif | |
ce33fdc5 | 1989 | mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); |
c69ad0a3 DM |
1990 | |
1991 | sun4v_linear_pte_xor_finalize(); | |
1992 | ||
1993 | sun4v_ktsb_init(); | |
1994 | sun4v_ktsb_register(); | |
ce33fdc5 DM |
1995 | } else { |
1996 | unsigned long impl, ver; | |
1997 | ||
1998 | cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | | |
1999 | HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); | |
2000 | ||
2001 | __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); | |
2002 | impl = ((ver >> 32) & 0xffff); | |
2003 | if (impl == PANTHER_IMPL) | |
2004 | cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | | |
2005 | HV_PGSZ_MASK_256MB); | |
c69ad0a3 DM |
2006 | |
2007 | sun4u_linear_pte_xor_finalize(); | |
890db403 | 2008 | } |
4a283339 | 2009 | |
c69ad0a3 DM |
2010 | /* Flush the TLBs and the 4M TSB so that the updated linear |
2011 | * pte XOR settings are realized for all mappings. | |
2012 | */ | |
2013 | __flush_tlb_all(); | |
2014 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
2015 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); | |
2016 | #endif | |
2017 | __flush_tlb_all(); | |
2018 | ||
5ed56f1a DM |
2019 | /* Setup bootmem... */ |
2020 | last_valid_pfn = end_pfn = bootmem_init(phys_base); | |
2021 | ||
4f70f7a9 DM |
2022 | /* Once the OF device tree and MDESC have been setup, we know |
2023 | * the list of possible cpus. Therefore we can allocate the | |
2024 | * IRQ stacks. | |
2025 | */ | |
2026 | for_each_possible_cpu(i) { | |
aa6f0790 | 2027 | node = cpu_to_node(i); |
5ed56f1a DM |
2028 | |
2029 | softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node), | |
2030 | THREAD_SIZE, | |
2031 | THREAD_SIZE, 0); | |
2032 | hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node), | |
2033 | THREAD_SIZE, | |
2034 | THREAD_SIZE, 0); | |
4f70f7a9 DM |
2035 | } |
2036 | ||
56425306 | 2037 | kernel_physical_mapping_init(); |
56425306 | 2038 | |
1da177e4 | 2039 | { |
919ee677 | 2040 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
1da177e4 | 2041 | |
919ee677 | 2042 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); |
1da177e4 | 2043 | |
919ee677 | 2044 | max_zone_pfns[ZONE_NORMAL] = end_pfn; |
1da177e4 | 2045 | |
919ee677 | 2046 | free_area_init_nodes(max_zone_pfns); |
1da177e4 LT |
2047 | } |
2048 | ||
3c62a2d3 | 2049 | printk("Booting Linux...\n"); |
1da177e4 LT |
2050 | } |
2051 | ||
7c9503b8 | 2052 | int page_in_phys_avail(unsigned long paddr) |
919ee677 DM |
2053 | { |
2054 | int i; | |
2055 | ||
2056 | paddr &= PAGE_MASK; | |
2057 | ||
2058 | for (i = 0; i < pavail_ents; i++) { | |
2059 | unsigned long start, end; | |
2060 | ||
2061 | start = pavail[i].phys_addr; | |
2062 | end = start + pavail[i].reg_size; | |
2063 | ||
2064 | if (paddr >= start && paddr < end) | |
2065 | return 1; | |
2066 | } | |
2067 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
2068 | return 1; | |
2069 | #ifdef CONFIG_BLK_DEV_INITRD | |
2070 | if (paddr >= __pa(initrd_start) && | |
2071 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
2072 | return 1; | |
2073 | #endif | |
2074 | ||
2075 | return 0; | |
2076 | } | |
2077 | ||
2078 | static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata; | |
2079 | static int pavail_rescan_ents __initdata; | |
2080 | ||
2081 | /* Certain OBP calls, such as fetching "available" properties, can | |
2082 | * claim physical memory. So, along with initializing the valid | |
2083 | * address bitmap, what we do here is refetch the physical available | |
2084 | * memory list again, and make sure it provides at least as much | |
2085 | * memory as 'pavail' does. | |
2086 | */ | |
d8ed1d43 | 2087 | static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap) |
1da177e4 | 2088 | { |
1da177e4 LT |
2089 | int i; |
2090 | ||
13edad7a | 2091 | read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents); |
1da177e4 | 2092 | |
13edad7a | 2093 | for (i = 0; i < pavail_ents; i++) { |
1da177e4 LT |
2094 | unsigned long old_start, old_end; |
2095 | ||
13edad7a | 2096 | old_start = pavail[i].phys_addr; |
919ee677 | 2097 | old_end = old_start + pavail[i].reg_size; |
1da177e4 LT |
2098 | while (old_start < old_end) { |
2099 | int n; | |
2100 | ||
c2a5a46b | 2101 | for (n = 0; n < pavail_rescan_ents; n++) { |
1da177e4 LT |
2102 | unsigned long new_start, new_end; |
2103 | ||
13edad7a DM |
2104 | new_start = pavail_rescan[n].phys_addr; |
2105 | new_end = new_start + | |
2106 | pavail_rescan[n].reg_size; | |
1da177e4 LT |
2107 | |
2108 | if (new_start <= old_start && | |
2109 | new_end >= (old_start + PAGE_SIZE)) { | |
0eef331a | 2110 | set_bit(old_start >> ILOG2_4MB, bitmap); |
1da177e4 LT |
2111 | goto do_next_page; |
2112 | } | |
2113 | } | |
919ee677 DM |
2114 | |
2115 | prom_printf("mem_init: Lost memory in pavail\n"); | |
2116 | prom_printf("mem_init: OLD start[%lx] size[%lx]\n", | |
2117 | pavail[i].phys_addr, | |
2118 | pavail[i].reg_size); | |
2119 | prom_printf("mem_init: NEW start[%lx] size[%lx]\n", | |
2120 | pavail_rescan[i].phys_addr, | |
2121 | pavail_rescan[i].reg_size); | |
2122 | prom_printf("mem_init: Cannot continue, aborting.\n"); | |
2123 | prom_halt(); | |
1da177e4 LT |
2124 | |
2125 | do_next_page: | |
2126 | old_start += PAGE_SIZE; | |
2127 | } | |
2128 | } | |
2129 | } | |
2130 | ||
d8ed1d43 DM |
2131 | static void __init patch_tlb_miss_handler_bitmap(void) |
2132 | { | |
2133 | extern unsigned int valid_addr_bitmap_insn[]; | |
2134 | extern unsigned int valid_addr_bitmap_patch[]; | |
2135 | ||
2136 | valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1]; | |
2137 | mb(); | |
2138 | valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0]; | |
2139 | flushi(&valid_addr_bitmap_insn[0]); | |
2140 | } | |
2141 | ||
961f8fa0 YL |
2142 | static void __init register_page_bootmem_info(void) |
2143 | { | |
2144 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
2145 | int i; | |
2146 | ||
2147 | for_each_online_node(i) | |
2148 | if (NODE_DATA(i)->node_spanned_pages) | |
2149 | register_page_bootmem_info_node(NODE_DATA(i)); | |
2150 | #endif | |
2151 | } | |
1da177e4 LT |
2152 | void __init mem_init(void) |
2153 | { | |
1da177e4 | 2154 | unsigned long addr, last; |
1da177e4 LT |
2155 | |
2156 | addr = PAGE_OFFSET + kern_base; | |
2157 | last = PAGE_ALIGN(kern_size) + addr; | |
2158 | while (addr < last) { | |
0eef331a | 2159 | set_bit(__pa(addr) >> ILOG2_4MB, sparc64_valid_addr_bitmap); |
1da177e4 LT |
2160 | addr += PAGE_SIZE; |
2161 | } | |
2162 | ||
d8ed1d43 DM |
2163 | setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap); |
2164 | patch_tlb_miss_handler_bitmap(); | |
1da177e4 | 2165 | |
1da177e4 LT |
2166 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
2167 | ||
961f8fa0 | 2168 | register_page_bootmem_info(); |
0c988534 | 2169 | free_all_bootmem(); |
919ee677 | 2170 | |
1da177e4 LT |
2171 | /* |
2172 | * Set up the zero page, mark it reserved, so that page count | |
2173 | * is not manipulated when freeing the page from user ptes. | |
2174 | */ | |
2175 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
2176 | if (mem_map_zero == NULL) { | |
2177 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
2178 | prom_halt(); | |
2179 | } | |
70affe45 | 2180 | mark_page_reserved(mem_map_zero); |
1da177e4 | 2181 | |
dceccbe9 | 2182 | mem_init_print_info(NULL); |
1da177e4 LT |
2183 | |
2184 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
2185 | cheetah_ecache_flush_init(); | |
2186 | } | |
2187 | ||
898cf0ec | 2188 | void free_initmem(void) |
1da177e4 LT |
2189 | { |
2190 | unsigned long addr, initend; | |
f2b60794 DM |
2191 | int do_free = 1; |
2192 | ||
2193 | /* If the physical memory maps were trimmed by kernel command | |
2194 | * line options, don't even try freeing this initmem stuff up. | |
2195 | * The kernel image could have been in the trimmed out region | |
2196 | * and if so the freeing below will free invalid page structs. | |
2197 | */ | |
2198 | if (cmdline_memory_size) | |
2199 | do_free = 0; | |
1da177e4 LT |
2200 | |
2201 | /* | |
2202 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
2203 | */ | |
2204 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
2205 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
2206 | for (; addr < initend; addr += PAGE_SIZE) { | |
2207 | unsigned long page; | |
1da177e4 LT |
2208 | |
2209 | page = (addr + | |
2210 | ((unsigned long) __va(kern_base)) - | |
2211 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 2212 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 | 2213 | |
70affe45 JL |
2214 | if (do_free) |
2215 | free_reserved_page(virt_to_page(page)); | |
1da177e4 LT |
2216 | } |
2217 | } | |
2218 | ||
2219 | #ifdef CONFIG_BLK_DEV_INITRD | |
2220 | void free_initrd_mem(unsigned long start, unsigned long end) | |
2221 | { | |
dceccbe9 JL |
2222 | free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, |
2223 | "initrd"); | |
1da177e4 LT |
2224 | } |
2225 | #endif | |
c4bce90e | 2226 | |
c4bce90e DM |
2227 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
2228 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
2229 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
2230 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
2231 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
2232 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
2233 | ||
2234 | pgprot_t PAGE_KERNEL __read_mostly; | |
2235 | EXPORT_SYMBOL(PAGE_KERNEL); | |
2236 | ||
2237 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
2238 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
2239 | |
2240 | pgprot_t PAGE_SHARED __read_mostly; | |
2241 | EXPORT_SYMBOL(PAGE_SHARED); | |
2242 | ||
c4bce90e DM |
2243 | unsigned long pg_iobits __read_mostly; |
2244 | ||
2245 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 2246 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 2247 | |
c4bce90e | 2248 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
2249 | EXPORT_SYMBOL(_PAGE_E); |
2250 | ||
c4bce90e | 2251 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 2252 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e | 2253 | |
46644c24 | 2254 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
46644c24 DM |
2255 | unsigned long vmemmap_table[VMEMMAP_SIZE]; |
2256 | ||
2856cc2e DM |
2257 | static long __meminitdata addr_start, addr_end; |
2258 | static int __meminitdata node_start; | |
2259 | ||
0aad818b JW |
2260 | int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, |
2261 | int node) | |
46644c24 | 2262 | { |
46644c24 DM |
2263 | unsigned long phys_start = (vstart - VMEMMAP_BASE); |
2264 | unsigned long phys_end = (vend - VMEMMAP_BASE); | |
2265 | unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK; | |
2266 | unsigned long end = VMEMMAP_ALIGN(phys_end); | |
2267 | unsigned long pte_base; | |
2268 | ||
2269 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2270 | _PAGE_CP_4U | _PAGE_CV_4U | | |
2271 | _PAGE_P_4U | _PAGE_W_4U); | |
2272 | if (tlb_type == hypervisor) | |
2273 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2274 | _PAGE_CP_4V | _PAGE_CV_4V | | |
2275 | _PAGE_P_4V | _PAGE_W_4V); | |
2276 | ||
2277 | for (; addr < end; addr += VMEMMAP_CHUNK) { | |
2278 | unsigned long *vmem_pp = | |
2279 | vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT); | |
2280 | void *block; | |
2281 | ||
2282 | if (!(*vmem_pp & _PAGE_VALID)) { | |
0eef331a | 2283 | block = vmemmap_alloc_block(1UL << ILOG2_4MB, node); |
46644c24 DM |
2284 | if (!block) |
2285 | return -ENOMEM; | |
2286 | ||
2287 | *vmem_pp = pte_base | __pa(block); | |
2288 | ||
2856cc2e DM |
2289 | /* check to see if we have contiguous blocks */ |
2290 | if (addr_end != addr || node_start != node) { | |
2291 | if (addr_start) | |
2292 | printk(KERN_DEBUG " [%lx-%lx] on node %d\n", | |
2293 | addr_start, addr_end-1, node_start); | |
2294 | addr_start = addr; | |
2295 | node_start = node; | |
2296 | } | |
2297 | addr_end = addr + VMEMMAP_CHUNK; | |
46644c24 DM |
2298 | } |
2299 | } | |
2300 | return 0; | |
2301 | } | |
2856cc2e DM |
2302 | |
2303 | void __meminit vmemmap_populate_print_last(void) | |
2304 | { | |
2305 | if (addr_start) { | |
2306 | printk(KERN_DEBUG " [%lx-%lx] on node %d\n", | |
2307 | addr_start, addr_end-1, node_start); | |
2308 | addr_start = 0; | |
2309 | addr_end = 0; | |
2310 | node_start = 0; | |
2311 | } | |
2312 | } | |
46723bfa | 2313 | |
0aad818b | 2314 | void vmemmap_free(unsigned long start, unsigned long end) |
0197518c TC |
2315 | { |
2316 | } | |
2317 | ||
46644c24 DM |
2318 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ |
2319 | ||
c4bce90e DM |
2320 | static void prot_init_common(unsigned long page_none, |
2321 | unsigned long page_shared, | |
2322 | unsigned long page_copy, | |
2323 | unsigned long page_readonly, | |
2324 | unsigned long page_exec_bit) | |
2325 | { | |
2326 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 2327 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
2328 | |
2329 | protection_map[0x0] = __pgprot(page_none); | |
2330 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
2331 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
2332 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
2333 | protection_map[0x4] = __pgprot(page_readonly); | |
2334 | protection_map[0x5] = __pgprot(page_readonly); | |
2335 | protection_map[0x6] = __pgprot(page_copy); | |
2336 | protection_map[0x7] = __pgprot(page_copy); | |
2337 | protection_map[0x8] = __pgprot(page_none); | |
2338 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
2339 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
2340 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
2341 | protection_map[0xc] = __pgprot(page_readonly); | |
2342 | protection_map[0xd] = __pgprot(page_readonly); | |
2343 | protection_map[0xe] = __pgprot(page_shared); | |
2344 | protection_map[0xf] = __pgprot(page_shared); | |
2345 | } | |
2346 | ||
2347 | static void __init sun4u_pgprot_init(void) | |
2348 | { | |
2349 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2350 | unsigned long page_exec_bit; | |
4f93d21d | 2351 | int i; |
c4bce90e DM |
2352 | |
2353 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2354 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2355 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2356 | _PAGE_EXEC_4U); | |
2357 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2358 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2359 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2360 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
c4bce90e DM |
2361 | |
2362 | _PAGE_IE = _PAGE_IE_4U; | |
2363 | _PAGE_E = _PAGE_E_4U; | |
2364 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
2365 | ||
2366 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
2367 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
2368 | ||
d1acb421 | 2369 | #ifdef CONFIG_DEBUG_PAGEALLOC |
922631b9 | 2370 | kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; |
d1acb421 | 2371 | #else |
9cc3a1ac | 2372 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
922631b9 | 2373 | PAGE_OFFSET; |
d1acb421 | 2374 | #endif |
9cc3a1ac DM |
2375 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
2376 | _PAGE_P_4U | _PAGE_W_4U); | |
2377 | ||
4f93d21d DM |
2378 | for (i = 1; i < 4; i++) |
2379 | kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; | |
c4bce90e | 2380 | |
c4bce90e DM |
2381 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | |
2382 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
2383 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
2384 | ||
2385 | ||
2386 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
2387 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2388 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
2389 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2390 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2391 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2392 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2393 | ||
2394 | page_exec_bit = _PAGE_EXEC_4U; | |
2395 | ||
2396 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2397 | page_exec_bit); | |
2398 | } | |
2399 | ||
2400 | static void __init sun4v_pgprot_init(void) | |
2401 | { | |
2402 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2403 | unsigned long page_exec_bit; | |
4f93d21d | 2404 | int i; |
c4bce90e DM |
2405 | |
2406 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
2407 | _PAGE_CACHE_4V | _PAGE_P_4V | | |
2408 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | | |
2409 | _PAGE_EXEC_4V); | |
2410 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
c4bce90e DM |
2411 | |
2412 | _PAGE_IE = _PAGE_IE_4V; | |
2413 | _PAGE_E = _PAGE_E_4V; | |
2414 | _PAGE_CACHE = _PAGE_CACHE_4V; | |
2415 | ||
d1acb421 | 2416 | #ifdef CONFIG_DEBUG_PAGEALLOC |
922631b9 | 2417 | kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; |
d1acb421 | 2418 | #else |
9cc3a1ac | 2419 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
922631b9 | 2420 | PAGE_OFFSET; |
d1acb421 | 2421 | #endif |
9cc3a1ac DM |
2422 | kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2423 | _PAGE_P_4V | _PAGE_W_4V); | |
2424 | ||
c69ad0a3 DM |
2425 | for (i = 1; i < 4; i++) |
2426 | kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; | |
4f93d21d | 2427 | |
c4bce90e DM |
2428 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | |
2429 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
2430 | ||
c4bce90e DM |
2431 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | |
2432 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
2433 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
2434 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
2435 | ||
2436 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V; | |
2437 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2438 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); | |
2439 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2440 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2441 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2442 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2443 | ||
2444 | page_exec_bit = _PAGE_EXEC_4V; | |
2445 | ||
2446 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2447 | page_exec_bit); | |
2448 | } | |
2449 | ||
2450 | unsigned long pte_sz_bits(unsigned long sz) | |
2451 | { | |
2452 | if (tlb_type == hypervisor) { | |
2453 | switch (sz) { | |
2454 | case 8 * 1024: | |
2455 | default: | |
2456 | return _PAGE_SZ8K_4V; | |
2457 | case 64 * 1024: | |
2458 | return _PAGE_SZ64K_4V; | |
2459 | case 512 * 1024: | |
2460 | return _PAGE_SZ512K_4V; | |
2461 | case 4 * 1024 * 1024: | |
2462 | return _PAGE_SZ4MB_4V; | |
6cb79b3f | 2463 | } |
c4bce90e DM |
2464 | } else { |
2465 | switch (sz) { | |
2466 | case 8 * 1024: | |
2467 | default: | |
2468 | return _PAGE_SZ8K_4U; | |
2469 | case 64 * 1024: | |
2470 | return _PAGE_SZ64K_4U; | |
2471 | case 512 * 1024: | |
2472 | return _PAGE_SZ512K_4U; | |
2473 | case 4 * 1024 * 1024: | |
2474 | return _PAGE_SZ4MB_4U; | |
6cb79b3f | 2475 | } |
c4bce90e DM |
2476 | } |
2477 | } | |
2478 | ||
2479 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
2480 | { | |
2481 | pte_t pte; | |
cf627156 DM |
2482 | |
2483 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
2484 | pte_val(pte) |= (((unsigned long)space) << 32); |
2485 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 2486 | |
cf627156 | 2487 | return pte; |
c4bce90e DM |
2488 | } |
2489 | ||
2490 | static unsigned long kern_large_tte(unsigned long paddr) | |
2491 | { | |
2492 | unsigned long val; | |
2493 | ||
2494 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2495 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
2496 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
2497 | if (tlb_type == hypervisor) | |
2498 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2499 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V | | |
2500 | _PAGE_EXEC_4V | _PAGE_W_4V); | |
2501 | ||
2502 | return val | paddr; | |
2503 | } | |
2504 | ||
c4bce90e DM |
2505 | /* If not locked, zap it. */ |
2506 | void __flush_tlb_all(void) | |
2507 | { | |
2508 | unsigned long pstate; | |
2509 | int i; | |
2510 | ||
2511 | __asm__ __volatile__("flushw\n\t" | |
2512 | "rdpr %%pstate, %0\n\t" | |
2513 | "wrpr %0, %1, %%pstate" | |
2514 | : "=r" (pstate) | |
2515 | : "i" (PSTATE_IE)); | |
8f361453 DM |
2516 | if (tlb_type == hypervisor) { |
2517 | sun4v_mmu_demap_all(); | |
2518 | } else if (tlb_type == spitfire) { | |
c4bce90e DM |
2519 | for (i = 0; i < 64; i++) { |
2520 | /* Spitfire Errata #32 workaround */ | |
2521 | /* NOTE: Always runs on spitfire, so no | |
2522 | * cheetah+ page size encodings. | |
2523 | */ | |
2524 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2525 | "flush %%g6" | |
2526 | : /* No outputs */ | |
2527 | : "r" (0), | |
2528 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2529 | ||
2530 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
2531 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2532 | "membar #Sync" | |
2533 | : /* no outputs */ | |
2534 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
2535 | spitfire_put_dtlb_data(i, 0x0UL); | |
2536 | } | |
2537 | ||
2538 | /* Spitfire Errata #32 workaround */ | |
2539 | /* NOTE: Always runs on spitfire, so no | |
2540 | * cheetah+ page size encodings. | |
2541 | */ | |
2542 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2543 | "flush %%g6" | |
2544 | : /* No outputs */ | |
2545 | : "r" (0), | |
2546 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2547 | ||
2548 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
2549 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2550 | "membar #Sync" | |
2551 | : /* no outputs */ | |
2552 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
2553 | spitfire_put_itlb_data(i, 0x0UL); | |
2554 | } | |
2555 | } | |
2556 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
2557 | cheetah_flush_dtlb_all(); | |
2558 | cheetah_flush_itlb_all(); | |
2559 | } | |
2560 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
2561 | : : "r" (pstate)); | |
2562 | } | |
c460bec7 | 2563 | |
c460bec7 DM |
2564 | pte_t *pte_alloc_one_kernel(struct mm_struct *mm, |
2565 | unsigned long address) | |
2566 | { | |
37b3a8ff DM |
2567 | struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | |
2568 | __GFP_REPEAT | __GFP_ZERO); | |
2569 | pte_t *pte = NULL; | |
c460bec7 | 2570 | |
c460bec7 DM |
2571 | if (page) |
2572 | pte = (pte_t *) page_address(page); | |
2573 | ||
2574 | return pte; | |
2575 | } | |
2576 | ||
2577 | pgtable_t pte_alloc_one(struct mm_struct *mm, | |
2578 | unsigned long address) | |
2579 | { | |
37b3a8ff DM |
2580 | struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | |
2581 | __GFP_REPEAT | __GFP_ZERO); | |
1ae9ae5f KS |
2582 | if (!page) |
2583 | return NULL; | |
2584 | if (!pgtable_page_ctor(page)) { | |
2585 | free_hot_cold_page(page, 0); | |
2586 | return NULL; | |
c460bec7 | 2587 | } |
1ae9ae5f | 2588 | return (pte_t *) page_address(page); |
c460bec7 DM |
2589 | } |
2590 | ||
2591 | void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |
2592 | { | |
37b3a8ff | 2593 | free_page((unsigned long)pte); |
c460bec7 DM |
2594 | } |
2595 | ||
2596 | static void __pte_free(pgtable_t pte) | |
2597 | { | |
2598 | struct page *page = virt_to_page(pte); | |
37b3a8ff DM |
2599 | |
2600 | pgtable_page_dtor(page); | |
2601 | __free_page(page); | |
c460bec7 DM |
2602 | } |
2603 | ||
2604 | void pte_free(struct mm_struct *mm, pgtable_t pte) | |
2605 | { | |
2606 | __pte_free(pte); | |
2607 | } | |
2608 | ||
2609 | void pgtable_free(void *table, bool is_page) | |
2610 | { | |
2611 | if (is_page) | |
2612 | __pte_free(table); | |
2613 | else | |
2614 | kmem_cache_free(pgtable_cache, table); | |
2615 | } | |
9e695d2e DM |
2616 | |
2617 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
9e695d2e DM |
2618 | void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, |
2619 | pmd_t *pmd) | |
2620 | { | |
2621 | unsigned long pte, flags; | |
2622 | struct mm_struct *mm; | |
2623 | pmd_t entry = *pmd; | |
9e695d2e DM |
2624 | |
2625 | if (!pmd_large(entry) || !pmd_young(entry)) | |
2626 | return; | |
2627 | ||
a7b9403f | 2628 | pte = pmd_val(entry); |
9e695d2e | 2629 | |
18f38132 DM |
2630 | /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ |
2631 | if (!(pte & _PAGE_VALID)) | |
2632 | return; | |
2633 | ||
37b3a8ff DM |
2634 | /* We are fabricating 8MB pages using 4MB real hw pages. */ |
2635 | pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); | |
9e695d2e DM |
2636 | |
2637 | mm = vma->vm_mm; | |
2638 | ||
2639 | spin_lock_irqsave(&mm->context.lock, flags); | |
2640 | ||
2641 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) | |
37b3a8ff | 2642 | __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, |
9e695d2e DM |
2643 | addr, pte); |
2644 | ||
2645 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
2646 | } | |
2647 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
2648 | ||
2649 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) | |
2650 | static void context_reload(void *__data) | |
2651 | { | |
2652 | struct mm_struct *mm = __data; | |
2653 | ||
2654 | if (mm == current->mm) | |
2655 | load_secondary_context(mm); | |
2656 | } | |
2657 | ||
0fbebed6 | 2658 | void hugetlb_setup(struct pt_regs *regs) |
9e695d2e | 2659 | { |
0fbebed6 DM |
2660 | struct mm_struct *mm = current->mm; |
2661 | struct tsb_config *tp; | |
9e695d2e | 2662 | |
0fbebed6 DM |
2663 | if (in_atomic() || !mm) { |
2664 | const struct exception_table_entry *entry; | |
2665 | ||
2666 | entry = search_exception_tables(regs->tpc); | |
2667 | if (entry) { | |
2668 | regs->tpc = entry->fixup; | |
2669 | regs->tnpc = regs->tpc + 4; | |
2670 | return; | |
2671 | } | |
2672 | pr_alert("Unexpected HugeTLB setup in atomic context.\n"); | |
2673 | die_if_kernel("HugeTSB in atomic", regs); | |
2674 | } | |
2675 | ||
2676 | tp = &mm->context.tsb_block[MM_TSB_HUGE]; | |
2677 | if (likely(tp->tsb == NULL)) | |
2678 | tsb_grow(mm, MM_TSB_HUGE, 0); | |
9e695d2e | 2679 | |
9e695d2e DM |
2680 | tsb_context_switch(mm); |
2681 | smp_tsb_sync(mm); | |
2682 | ||
2683 | /* On UltraSPARC-III+ and later, configure the second half of | |
2684 | * the Data-TLB for huge pages. | |
2685 | */ | |
2686 | if (tlb_type == cheetah_plus) { | |
2687 | unsigned long ctx; | |
2688 | ||
2689 | spin_lock(&ctx_alloc_lock); | |
2690 | ctx = mm->context.sparc64_ctx_val; | |
2691 | ctx &= ~CTX_PGSZ_MASK; | |
2692 | ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; | |
2693 | ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; | |
2694 | ||
2695 | if (ctx != mm->context.sparc64_ctx_val) { | |
2696 | /* When changing the page size fields, we | |
2697 | * must perform a context flush so that no | |
2698 | * stale entries match. This flush must | |
2699 | * occur with the original context register | |
2700 | * settings. | |
2701 | */ | |
2702 | do_flush_tlb_mm(mm); | |
2703 | ||
2704 | /* Reload the context register of all processors | |
2705 | * also executing in this address space. | |
2706 | */ | |
2707 | mm->context.sparc64_ctx_val = ctx; | |
2708 | on_each_cpu(context_reload, mm, 0); | |
2709 | } | |
2710 | spin_unlock(&ctx_alloc_lock); | |
2711 | } | |
2712 | } | |
2713 | #endif | |
f6d4fb5c | 2714 | |
2715 | static struct resource code_resource = { | |
2716 | .name = "Kernel code", | |
2717 | .flags = IORESOURCE_BUSY | IORESOURCE_MEM | |
2718 | }; | |
2719 | ||
2720 | static struct resource data_resource = { | |
2721 | .name = "Kernel data", | |
2722 | .flags = IORESOURCE_BUSY | IORESOURCE_MEM | |
2723 | }; | |
2724 | ||
2725 | static struct resource bss_resource = { | |
2726 | .name = "Kernel bss", | |
2727 | .flags = IORESOURCE_BUSY | IORESOURCE_MEM | |
2728 | }; | |
2729 | ||
2730 | static inline resource_size_t compute_kern_paddr(void *addr) | |
2731 | { | |
2732 | return (resource_size_t) (addr - KERNBASE + kern_base); | |
2733 | } | |
2734 | ||
2735 | static void __init kernel_lds_init(void) | |
2736 | { | |
2737 | code_resource.start = compute_kern_paddr(_text); | |
2738 | code_resource.end = compute_kern_paddr(_etext - 1); | |
2739 | data_resource.start = compute_kern_paddr(_etext); | |
2740 | data_resource.end = compute_kern_paddr(_edata - 1); | |
2741 | bss_resource.start = compute_kern_paddr(__bss_start); | |
2742 | bss_resource.end = compute_kern_paddr(_end - 1); | |
2743 | } | |
2744 | ||
2745 | static int __init report_memory(void) | |
2746 | { | |
2747 | int i; | |
2748 | struct resource *res; | |
2749 | ||
2750 | kernel_lds_init(); | |
2751 | ||
2752 | for (i = 0; i < pavail_ents; i++) { | |
2753 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
2754 | ||
2755 | if (!res) { | |
2756 | pr_warn("Failed to allocate source.\n"); | |
2757 | break; | |
2758 | } | |
2759 | ||
2760 | res->name = "System RAM"; | |
2761 | res->start = pavail[i].phys_addr; | |
2762 | res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; | |
2763 | res->flags = IORESOURCE_BUSY | IORESOURCE_MEM; | |
2764 | ||
2765 | if (insert_resource(&iomem_resource, res) < 0) { | |
2766 | pr_warn("Resource insertion failed.\n"); | |
2767 | break; | |
2768 | } | |
2769 | ||
2770 | insert_resource(res, &code_resource); | |
2771 | insert_resource(res, &data_resource); | |
2772 | insert_resource(res, &bss_resource); | |
2773 | } | |
2774 | ||
2775 | return 0; | |
2776 | } | |
2777 | device_initcall(report_memory); | |
e9011d08 | 2778 | |
4ca9a237 DM |
2779 | #ifdef CONFIG_SMP |
2780 | #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range | |
2781 | #else | |
2782 | #define do_flush_tlb_kernel_range __flush_tlb_kernel_range | |
2783 | #endif | |
2784 | ||
2785 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
2786 | { | |
2787 | if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { | |
2788 | if (start < LOW_OBP_ADDRESS) { | |
2789 | flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); | |
2790 | do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); | |
2791 | } | |
2792 | if (end > HI_OBP_ADDRESS) { | |
2793 | flush_tsb_kernel_range(end, HI_OBP_ADDRESS); | |
2794 | do_flush_tlb_kernel_range(end, HI_OBP_ADDRESS); | |
2795 | } | |
2796 | } else { | |
2797 | flush_tsb_kernel_range(start, end); | |
2798 | do_flush_tlb_kernel_range(start, end); | |
2799 | } | |
2800 | } |