Commit | Line | Data |
---|---|---|
74bf4312 DM |
1 | /* arch/sparc64/mm/tsb.c |
2 | * | |
a3cf5e6b | 3 | * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net> |
74bf4312 DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
a3cf5e6b | 7 | #include <linux/preempt.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
74bf4312 | 9 | #include <asm/page.h> |
98c5584c | 10 | #include <asm/pgtable.h> |
f36391d2 | 11 | #include <asm/mmu_context.h> |
bd40791e | 12 | #include <asm/tsb.h> |
f36391d2 | 13 | #include <asm/tlb.h> |
9b4006dc | 14 | #include <asm/oplib.h> |
74bf4312 | 15 | |
74bf4312 DM |
16 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
17 | ||
dcc1e8dd | 18 | static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long hash_shift, unsigned long nentries) |
74bf4312 | 19 | { |
dcc1e8dd | 20 | vaddr >>= hash_shift; |
98c5584c | 21 | return vaddr & (nentries - 1); |
74bf4312 DM |
22 | } |
23 | ||
8b234274 | 24 | static inline int tag_compare(unsigned long tag, unsigned long vaddr) |
74bf4312 | 25 | { |
8b234274 | 26 | return (tag == (vaddr >> 22)); |
74bf4312 DM |
27 | } |
28 | ||
29 | /* TSB flushes need only occur on the processor initiating the address | |
30 | * space modification, not on each cpu the address space has run on. | |
31 | * Only the TLB flush needs that treatment. | |
32 | */ | |
33 | ||
34 | void flush_tsb_kernel_range(unsigned long start, unsigned long end) | |
35 | { | |
36 | unsigned long v; | |
37 | ||
38 | for (v = start; v < end; v += PAGE_SIZE) { | |
dcc1e8dd DM |
39 | unsigned long hash = tsb_hash(v, PAGE_SHIFT, |
40 | KERNEL_TSB_NENTRIES); | |
98c5584c | 41 | struct tsb *ent = &swapper_tsb[hash]; |
74bf4312 | 42 | |
293666b7 | 43 | if (tag_compare(ent->tag, v)) |
8b234274 | 44 | ent->tag = (1UL << TSB_TAG_INVALID_BIT); |
74bf4312 DM |
45 | } |
46 | } | |
47 | ||
f36391d2 DM |
48 | static void __flush_tsb_one_entry(unsigned long tsb, unsigned long v, |
49 | unsigned long hash_shift, | |
50 | unsigned long nentries) | |
74bf4312 | 51 | { |
f36391d2 | 52 | unsigned long tag, ent, hash; |
7a1ac526 | 53 | |
f36391d2 DM |
54 | v &= ~0x1UL; |
55 | hash = tsb_hash(v, hash_shift, nentries); | |
56 | ent = tsb + (hash * sizeof(struct tsb)); | |
57 | tag = (v >> 22UL); | |
74bf4312 | 58 | |
f36391d2 DM |
59 | tsb_flush(ent, tag); |
60 | } | |
74bf4312 | 61 | |
f36391d2 DM |
62 | static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift, |
63 | unsigned long tsb, unsigned long nentries) | |
64 | { | |
65 | unsigned long i; | |
517af332 | 66 | |
f36391d2 DM |
67 | for (i = 0; i < tb->tlb_nr; i++) |
68 | __flush_tsb_one_entry(tsb, tb->vaddrs[i], hash_shift, nentries); | |
dcc1e8dd DM |
69 | } |
70 | ||
90f08e39 | 71 | void flush_tsb_user(struct tlb_batch *tb) |
dcc1e8dd | 72 | { |
90f08e39 | 73 | struct mm_struct *mm = tb->mm; |
dcc1e8dd DM |
74 | unsigned long nentries, base, flags; |
75 | ||
76 | spin_lock_irqsave(&mm->context.lock, flags); | |
7a1ac526 | 77 | |
dcc1e8dd DM |
78 | base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb; |
79 | nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries; | |
80 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
81 | base = __pa(base); | |
90f08e39 | 82 | __flush_tsb_one(tb, PAGE_SHIFT, base, nentries); |
dcc1e8dd | 83 | |
9e695d2e | 84 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
85 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb) { |
86 | base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb; | |
87 | nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries; | |
88 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
89 | base = __pa(base); | |
37b3a8ff | 90 | __flush_tsb_one(tb, REAL_HPAGE_SHIFT, base, nentries); |
dcc1e8dd DM |
91 | } |
92 | #endif | |
7a1ac526 | 93 | spin_unlock_irqrestore(&mm->context.lock, flags); |
74bf4312 | 94 | } |
09f94287 | 95 | |
f36391d2 DM |
96 | void flush_tsb_user_page(struct mm_struct *mm, unsigned long vaddr) |
97 | { | |
98 | unsigned long nentries, base, flags; | |
99 | ||
100 | spin_lock_irqsave(&mm->context.lock, flags); | |
101 | ||
102 | base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb; | |
103 | nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries; | |
104 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
105 | base = __pa(base); | |
106 | __flush_tsb_one_entry(base, vaddr, PAGE_SHIFT, nentries); | |
107 | ||
108 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) | |
109 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb) { | |
110 | base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb; | |
111 | nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries; | |
112 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
113 | base = __pa(base); | |
37b3a8ff | 114 | __flush_tsb_one_entry(base, vaddr, REAL_HPAGE_SHIFT, nentries); |
f36391d2 DM |
115 | } |
116 | #endif | |
117 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
118 | } | |
119 | ||
dcc1e8dd DM |
120 | #define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_8K |
121 | #define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_8K | |
dcc1e8dd | 122 | |
9e695d2e | 123 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
124 | #define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_4MB |
125 | #define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_4MB | |
dcc1e8dd DM |
126 | #endif |
127 | ||
128 | static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsigned long tsb_bytes) | |
98c5584c DM |
129 | { |
130 | unsigned long tsb_reg, base, tsb_paddr; | |
131 | unsigned long page_sz, tte; | |
132 | ||
dcc1e8dd DM |
133 | mm->context.tsb_block[tsb_idx].tsb_nentries = |
134 | tsb_bytes / sizeof(struct tsb); | |
98c5584c DM |
135 | |
136 | base = TSBMAP_BASE; | |
c4bce90e | 137 | tte = pgprot_val(PAGE_KERNEL_LOCKED); |
dcc1e8dd | 138 | tsb_paddr = __pa(mm->context.tsb_block[tsb_idx].tsb); |
517af332 | 139 | BUG_ON(tsb_paddr & (tsb_bytes - 1UL)); |
98c5584c DM |
140 | |
141 | /* Use the smallest page size that can map the whole TSB | |
142 | * in one TLB entry. | |
143 | */ | |
144 | switch (tsb_bytes) { | |
145 | case 8192 << 0: | |
146 | tsb_reg = 0x0UL; | |
147 | #ifdef DCACHE_ALIASING_POSSIBLE | |
148 | base += (tsb_paddr & 8192); | |
149 | #endif | |
98c5584c DM |
150 | page_sz = 8192; |
151 | break; | |
152 | ||
153 | case 8192 << 1: | |
154 | tsb_reg = 0x1UL; | |
98c5584c DM |
155 | page_sz = 64 * 1024; |
156 | break; | |
157 | ||
158 | case 8192 << 2: | |
159 | tsb_reg = 0x2UL; | |
98c5584c DM |
160 | page_sz = 64 * 1024; |
161 | break; | |
162 | ||
163 | case 8192 << 3: | |
164 | tsb_reg = 0x3UL; | |
98c5584c DM |
165 | page_sz = 64 * 1024; |
166 | break; | |
167 | ||
168 | case 8192 << 4: | |
169 | tsb_reg = 0x4UL; | |
98c5584c DM |
170 | page_sz = 512 * 1024; |
171 | break; | |
172 | ||
173 | case 8192 << 5: | |
174 | tsb_reg = 0x5UL; | |
98c5584c DM |
175 | page_sz = 512 * 1024; |
176 | break; | |
177 | ||
178 | case 8192 << 6: | |
179 | tsb_reg = 0x6UL; | |
98c5584c DM |
180 | page_sz = 512 * 1024; |
181 | break; | |
182 | ||
183 | case 8192 << 7: | |
184 | tsb_reg = 0x7UL; | |
98c5584c DM |
185 | page_sz = 4 * 1024 * 1024; |
186 | break; | |
bd40791e DM |
187 | |
188 | default: | |
7e5766fa DM |
189 | printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n", |
190 | current->comm, current->pid, tsb_bytes); | |
191 | do_exit(SIGSEGV); | |
6cb79b3f | 192 | } |
c4bce90e | 193 | tte |= pte_sz_bits(page_sz); |
98c5584c | 194 | |
618e9ed9 | 195 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) { |
517af332 DM |
196 | /* Physical mapping, no locked TLB entry for TSB. */ |
197 | tsb_reg |= tsb_paddr; | |
198 | ||
dcc1e8dd DM |
199 | mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg; |
200 | mm->context.tsb_block[tsb_idx].tsb_map_vaddr = 0; | |
201 | mm->context.tsb_block[tsb_idx].tsb_map_pte = 0; | |
517af332 DM |
202 | } else { |
203 | tsb_reg |= base; | |
204 | tsb_reg |= (tsb_paddr & (page_sz - 1UL)); | |
205 | tte |= (tsb_paddr & ~(page_sz - 1UL)); | |
206 | ||
dcc1e8dd DM |
207 | mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg; |
208 | mm->context.tsb_block[tsb_idx].tsb_map_vaddr = base; | |
209 | mm->context.tsb_block[tsb_idx].tsb_map_pte = tte; | |
517af332 | 210 | } |
98c5584c | 211 | |
618e9ed9 DM |
212 | /* Setup the Hypervisor TSB descriptor. */ |
213 | if (tlb_type == hypervisor) { | |
dcc1e8dd | 214 | struct hv_tsb_descr *hp = &mm->context.tsb_descr[tsb_idx]; |
618e9ed9 | 215 | |
dcc1e8dd DM |
216 | switch (tsb_idx) { |
217 | case MM_TSB_BASE: | |
218 | hp->pgsz_idx = HV_PGSZ_IDX_BASE; | |
618e9ed9 | 219 | break; |
9e695d2e | 220 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
221 | case MM_TSB_HUGE: |
222 | hp->pgsz_idx = HV_PGSZ_IDX_HUGE; | |
618e9ed9 | 223 | break; |
dcc1e8dd DM |
224 | #endif |
225 | default: | |
226 | BUG(); | |
6cb79b3f | 227 | } |
618e9ed9 DM |
228 | hp->assoc = 1; |
229 | hp->num_ttes = tsb_bytes / 16; | |
230 | hp->ctx_idx = 0; | |
dcc1e8dd DM |
231 | switch (tsb_idx) { |
232 | case MM_TSB_BASE: | |
233 | hp->pgsz_mask = HV_PGSZ_MASK_BASE; | |
618e9ed9 | 234 | break; |
9e695d2e | 235 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
236 | case MM_TSB_HUGE: |
237 | hp->pgsz_mask = HV_PGSZ_MASK_HUGE; | |
618e9ed9 | 238 | break; |
dcc1e8dd DM |
239 | #endif |
240 | default: | |
241 | BUG(); | |
6cb79b3f | 242 | } |
618e9ed9 DM |
243 | hp->tsb_base = tsb_paddr; |
244 | hp->resv = 0; | |
245 | } | |
98c5584c DM |
246 | } |
247 | ||
4dedbf8d DM |
248 | struct kmem_cache *pgtable_cache __read_mostly; |
249 | ||
e18b890b | 250 | static struct kmem_cache *tsb_caches[8] __read_mostly; |
9b4006dc DM |
251 | |
252 | static const char *tsb_cache_names[8] = { | |
253 | "tsb_8KB", | |
254 | "tsb_16KB", | |
255 | "tsb_32KB", | |
256 | "tsb_64KB", | |
257 | "tsb_128KB", | |
258 | "tsb_256KB", | |
259 | "tsb_512KB", | |
260 | "tsb_1MB", | |
261 | }; | |
262 | ||
3a2cba99 | 263 | void __init pgtable_cache_init(void) |
9b4006dc DM |
264 | { |
265 | unsigned long i; | |
266 | ||
4dedbf8d DM |
267 | pgtable_cache = kmem_cache_create("pgtable_cache", |
268 | PAGE_SIZE, PAGE_SIZE, | |
269 | 0, | |
270 | _clear_page); | |
271 | if (!pgtable_cache) { | |
272 | prom_printf("pgtable_cache_init(): Could not create!\n"); | |
273 | prom_halt(); | |
274 | } | |
275 | ||
151b628f | 276 | for (i = 0; i < ARRAY_SIZE(tsb_cache_names); i++) { |
9b4006dc DM |
277 | unsigned long size = 8192 << i; |
278 | const char *name = tsb_cache_names[i]; | |
279 | ||
280 | tsb_caches[i] = kmem_cache_create(name, | |
281 | size, size, | |
20c2df83 | 282 | 0, NULL); |
9b4006dc DM |
283 | if (!tsb_caches[i]) { |
284 | prom_printf("Could not create %s cache\n", name); | |
285 | prom_halt(); | |
286 | } | |
287 | } | |
288 | } | |
289 | ||
0871420f DM |
290 | int sysctl_tsb_ratio = -2; |
291 | ||
292 | static unsigned long tsb_size_to_rss_limit(unsigned long new_size) | |
293 | { | |
294 | unsigned long num_ents = (new_size / sizeof(struct tsb)); | |
295 | ||
296 | if (sysctl_tsb_ratio < 0) | |
297 | return num_ents - (num_ents >> -sysctl_tsb_ratio); | |
298 | else | |
299 | return num_ents + (num_ents >> sysctl_tsb_ratio); | |
300 | } | |
301 | ||
dcc1e8dd DM |
302 | /* When the RSS of an address space exceeds tsb_rss_limit for a TSB, |
303 | * do_sparc64_fault() invokes this routine to try and grow it. | |
7a1ac526 | 304 | * |
bd40791e | 305 | * When we reach the maximum TSB size supported, we stick ~0UL into |
dcc1e8dd | 306 | * tsb_rss_limit for that TSB so the grow checks in do_sparc64_fault() |
bd40791e DM |
307 | * will not trigger any longer. |
308 | * | |
309 | * The TSB can be anywhere from 8K to 1MB in size, in increasing powers | |
310 | * of two. The TSB must be aligned to it's size, so f.e. a 512K TSB | |
b52439c2 DM |
311 | * must be 512K aligned. It also must be physically contiguous, so we |
312 | * cannot use vmalloc(). | |
bd40791e DM |
313 | * |
314 | * The idea here is to grow the TSB when the RSS of the process approaches | |
315 | * the number of entries that the current TSB can hold at once. Currently, | |
316 | * we trigger when the RSS hits 3/4 of the TSB capacity. | |
317 | */ | |
dcc1e8dd | 318 | void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long rss) |
bd40791e DM |
319 | { |
320 | unsigned long max_tsb_size = 1 * 1024 * 1024; | |
9b4006dc | 321 | unsigned long new_size, old_size, flags; |
7a1ac526 | 322 | struct tsb *old_tsb, *new_tsb; |
9b4006dc DM |
323 | unsigned long new_cache_index, old_cache_index; |
324 | unsigned long new_rss_limit; | |
b52439c2 | 325 | gfp_t gfp_flags; |
bd40791e DM |
326 | |
327 | if (max_tsb_size > (PAGE_SIZE << MAX_ORDER)) | |
328 | max_tsb_size = (PAGE_SIZE << MAX_ORDER); | |
329 | ||
9b4006dc DM |
330 | new_cache_index = 0; |
331 | for (new_size = 8192; new_size < max_tsb_size; new_size <<= 1UL) { | |
0871420f DM |
332 | new_rss_limit = tsb_size_to_rss_limit(new_size); |
333 | if (new_rss_limit > rss) | |
bd40791e | 334 | break; |
9b4006dc | 335 | new_cache_index++; |
bd40791e DM |
336 | } |
337 | ||
9b4006dc | 338 | if (new_size == max_tsb_size) |
b52439c2 | 339 | new_rss_limit = ~0UL; |
b52439c2 | 340 | |
9b4006dc | 341 | retry_tsb_alloc: |
b52439c2 | 342 | gfp_flags = GFP_KERNEL; |
9b4006dc | 343 | if (new_size > (PAGE_SIZE * 2)) |
a55ee1ff | 344 | gfp_flags |= __GFP_NOWARN | __GFP_NORETRY; |
b52439c2 | 345 | |
1f261ef5 DM |
346 | new_tsb = kmem_cache_alloc_node(tsb_caches[new_cache_index], |
347 | gfp_flags, numa_node_id()); | |
9b4006dc | 348 | if (unlikely(!new_tsb)) { |
b52439c2 DM |
349 | /* Not being able to fork due to a high-order TSB |
350 | * allocation failure is very bad behavior. Just back | |
351 | * down to a 0-order allocation and force no TSB | |
352 | * growing for this address space. | |
353 | */ | |
dcc1e8dd DM |
354 | if (mm->context.tsb_block[tsb_index].tsb == NULL && |
355 | new_cache_index > 0) { | |
9b4006dc DM |
356 | new_cache_index = 0; |
357 | new_size = 8192; | |
b52439c2 | 358 | new_rss_limit = ~0UL; |
9b4006dc | 359 | goto retry_tsb_alloc; |
b52439c2 DM |
360 | } |
361 | ||
362 | /* If we failed on a TSB grow, we are under serious | |
363 | * memory pressure so don't try to grow any more. | |
364 | */ | |
dcc1e8dd DM |
365 | if (mm->context.tsb_block[tsb_index].tsb != NULL) |
366 | mm->context.tsb_block[tsb_index].tsb_rss_limit = ~0UL; | |
bd40791e | 367 | return; |
b52439c2 | 368 | } |
bd40791e | 369 | |
8b234274 | 370 | /* Mark all tags as invalid. */ |
bb8646d8 | 371 | tsb_init(new_tsb, new_size); |
7a1ac526 DM |
372 | |
373 | /* Ok, we are about to commit the changes. If we are | |
374 | * growing an existing TSB the locking is very tricky, | |
375 | * so WATCH OUT! | |
376 | * | |
377 | * We have to hold mm->context.lock while committing to the | |
378 | * new TSB, this synchronizes us with processors in | |
379 | * flush_tsb_user() and switch_mm() for this address space. | |
380 | * | |
381 | * But even with that lock held, processors run asynchronously | |
382 | * accessing the old TSB via TLB miss handling. This is OK | |
383 | * because those actions are just propagating state from the | |
384 | * Linux page tables into the TSB, page table mappings are not | |
385 | * being changed. If a real fault occurs, the processor will | |
386 | * synchronize with us when it hits flush_tsb_user(), this is | |
387 | * also true for the case where vmscan is modifying the page | |
388 | * tables. The only thing we need to be careful with is to | |
389 | * skip any locked TSB entries during copy_tsb(). | |
390 | * | |
391 | * When we finish committing to the new TSB, we have to drop | |
392 | * the lock and ask all other cpus running this address space | |
393 | * to run tsb_context_switch() to see the new TSB table. | |
394 | */ | |
395 | spin_lock_irqsave(&mm->context.lock, flags); | |
396 | ||
dcc1e8dd DM |
397 | old_tsb = mm->context.tsb_block[tsb_index].tsb; |
398 | old_cache_index = | |
399 | (mm->context.tsb_block[tsb_index].tsb_reg_val & 0x7UL); | |
400 | old_size = (mm->context.tsb_block[tsb_index].tsb_nentries * | |
401 | sizeof(struct tsb)); | |
7a1ac526 | 402 | |
9b4006dc | 403 | |
7a1ac526 DM |
404 | /* Handle multiple threads trying to grow the TSB at the same time. |
405 | * One will get in here first, and bump the size and the RSS limit. | |
406 | * The others will get in here next and hit this check. | |
407 | */ | |
dcc1e8dd DM |
408 | if (unlikely(old_tsb && |
409 | (rss < mm->context.tsb_block[tsb_index].tsb_rss_limit))) { | |
7a1ac526 DM |
410 | spin_unlock_irqrestore(&mm->context.lock, flags); |
411 | ||
9b4006dc | 412 | kmem_cache_free(tsb_caches[new_cache_index], new_tsb); |
7a1ac526 DM |
413 | return; |
414 | } | |
8b234274 | 415 | |
dcc1e8dd | 416 | mm->context.tsb_block[tsb_index].tsb_rss_limit = new_rss_limit; |
bd40791e | 417 | |
7a1ac526 DM |
418 | if (old_tsb) { |
419 | extern void copy_tsb(unsigned long old_tsb_base, | |
420 | unsigned long old_tsb_size, | |
421 | unsigned long new_tsb_base, | |
422 | unsigned long new_tsb_size); | |
423 | unsigned long old_tsb_base = (unsigned long) old_tsb; | |
424 | unsigned long new_tsb_base = (unsigned long) new_tsb; | |
425 | ||
426 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) { | |
427 | old_tsb_base = __pa(old_tsb_base); | |
428 | new_tsb_base = __pa(new_tsb_base); | |
429 | } | |
9b4006dc | 430 | copy_tsb(old_tsb_base, old_size, new_tsb_base, new_size); |
7a1ac526 | 431 | } |
bd40791e | 432 | |
dcc1e8dd DM |
433 | mm->context.tsb_block[tsb_index].tsb = new_tsb; |
434 | setup_tsb_params(mm, tsb_index, new_size); | |
bd40791e | 435 | |
7a1ac526 DM |
436 | spin_unlock_irqrestore(&mm->context.lock, flags); |
437 | ||
bd40791e DM |
438 | /* If old_tsb is NULL, we're being invoked for the first time |
439 | * from init_new_context(). | |
440 | */ | |
441 | if (old_tsb) { | |
7a1ac526 | 442 | /* Reload it on the local cpu. */ |
bd40791e DM |
443 | tsb_context_switch(mm); |
444 | ||
7a1ac526 | 445 | /* Now force other processors to do the same. */ |
a3cf5e6b | 446 | preempt_disable(); |
7a1ac526 | 447 | smp_tsb_sync(mm); |
a3cf5e6b | 448 | preempt_enable(); |
7a1ac526 DM |
449 | |
450 | /* Now it is safe to free the old tsb. */ | |
9b4006dc | 451 | kmem_cache_free(tsb_caches[old_cache_index], old_tsb); |
bd40791e DM |
452 | } |
453 | } | |
454 | ||
09f94287 DM |
455 | int init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
456 | { | |
9e695d2e | 457 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
458 | unsigned long huge_pte_count; |
459 | #endif | |
460 | unsigned int i; | |
461 | ||
a77754b4 | 462 | spin_lock_init(&mm->context.lock); |
09f94287 DM |
463 | |
464 | mm->context.sparc64_ctx_val = 0UL; | |
09f94287 | 465 | |
9e695d2e | 466 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
467 | /* We reset it to zero because the fork() page copying |
468 | * will re-increment the counters as the parent PTEs are | |
469 | * copied into the child address space. | |
470 | */ | |
471 | huge_pte_count = mm->context.huge_pte_count; | |
472 | mm->context.huge_pte_count = 0; | |
473 | #endif | |
474 | ||
bd40791e DM |
475 | /* copy_mm() copies over the parent's mm_struct before calling |
476 | * us, so we need to zero out the TSB pointer or else tsb_grow() | |
477 | * will be confused and think there is an older TSB to free up. | |
478 | */ | |
dcc1e8dd DM |
479 | for (i = 0; i < MM_NUM_TSBS; i++) |
480 | mm->context.tsb_block[i].tsb = NULL; | |
7a1ac526 DM |
481 | |
482 | /* If this is fork, inherit the parent's TSB size. We would | |
483 | * grow it to that size on the first page fault anyways. | |
484 | */ | |
dcc1e8dd | 485 | tsb_grow(mm, MM_TSB_BASE, get_mm_rss(mm)); |
bd40791e | 486 | |
9e695d2e | 487 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
488 | if (unlikely(huge_pte_count)) |
489 | tsb_grow(mm, MM_TSB_HUGE, huge_pte_count); | |
490 | #endif | |
491 | ||
492 | if (unlikely(!mm->context.tsb_block[MM_TSB_BASE].tsb)) | |
bd40791e | 493 | return -ENOMEM; |
09f94287 DM |
494 | |
495 | return 0; | |
496 | } | |
497 | ||
dcc1e8dd | 498 | static void tsb_destroy_one(struct tsb_config *tp) |
09f94287 | 499 | { |
dcc1e8dd | 500 | unsigned long cache_index; |
bd40791e | 501 | |
dcc1e8dd DM |
502 | if (!tp->tsb) |
503 | return; | |
504 | cache_index = tp->tsb_reg_val & 0x7UL; | |
505 | kmem_cache_free(tsb_caches[cache_index], tp->tsb); | |
506 | tp->tsb = NULL; | |
507 | tp->tsb_reg_val = 0UL; | |
508 | } | |
98c5584c | 509 | |
dcc1e8dd DM |
510 | void destroy_context(struct mm_struct *mm) |
511 | { | |
512 | unsigned long flags, i; | |
513 | ||
514 | for (i = 0; i < MM_NUM_TSBS; i++) | |
515 | tsb_destroy_one(&mm->context.tsb_block[i]); | |
09f94287 | 516 | |
77b838fa | 517 | spin_lock_irqsave(&ctx_alloc_lock, flags); |
09f94287 DM |
518 | |
519 | if (CTX_VALID(mm->context)) { | |
520 | unsigned long nr = CTX_NRBITS(mm->context); | |
521 | mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); | |
522 | } | |
523 | ||
77b838fa | 524 | spin_unlock_irqrestore(&ctx_alloc_lock, flags); |
09f94287 | 525 | } |