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1da177e4 LT |
1 | /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $ |
2 | * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points. | |
3 | * | |
4 | * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx) | |
7 | * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/errno.h> |
11 | ||
12 | #include <asm/head.h> | |
13 | #include <asm/asi.h> | |
14 | #include <asm/smp.h> | |
15 | #include <asm/ptrace.h> | |
16 | #include <asm/page.h> | |
17 | #include <asm/signal.h> | |
18 | #include <asm/pgtable.h> | |
19 | #include <asm/processor.h> | |
20 | #include <asm/visasm.h> | |
21 | #include <asm/estate.h> | |
22 | #include <asm/auxio.h> | |
6c52a96e | 23 | #include <asm/sfafsr.h> |
fd0504c3 | 24 | #include <asm/pil.h> |
59359ff8 | 25 | #include <asm/unistd.h> |
1da177e4 | 26 | |
1da177e4 LT |
27 | #define curptr g6 |
28 | ||
1da177e4 LT |
29 | .text |
30 | .align 32 | |
31 | ||
1da177e4 LT |
32 | /* This is trivial with the new code... */ |
33 | .globl do_fpdis | |
34 | do_fpdis: | |
ba639933 | 35 | sethi %hi(TSTATE_PEF), %g4 |
1da177e4 LT |
36 | rdpr %tstate, %g5 |
37 | andcc %g5, %g4, %g0 | |
38 | be,pt %xcc, 1f | |
39 | nop | |
40 | rd %fprs, %g5 | |
41 | andcc %g5, FPRS_FEF, %g0 | |
42 | be,pt %xcc, 1f | |
43 | nop | |
44 | ||
45 | /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */ | |
46 | sethi %hi(109f), %g7 | |
47 | ba,pt %xcc, etrap | |
48 | 109: or %g7, %lo(109b), %g7 | |
49 | add %g0, %g0, %g0 | |
50 | ba,a,pt %xcc, rtrap_clr_l6 | |
51 | ||
ffe483d5 | 52 | 1: TRAP_LOAD_THREAD_REG(%g6, %g1) |
56fb4df6 | 53 | ldub [%g6 + TI_FPSAVED], %g5 |
ba639933 DM |
54 | wr %g0, FPRS_FEF, %fprs |
55 | andcc %g5, FPRS_FEF, %g0 | |
56 | be,a,pt %icc, 1f | |
57 | clr %g7 | |
58 | ldx [%g6 + TI_GSR], %g7 | |
59 | 1: andcc %g5, FPRS_DL, %g0 | |
60 | bne,pn %icc, 2f | |
61 | fzero %f0 | |
62 | andcc %g5, FPRS_DU, %g0 | |
63 | bne,pn %icc, 1f | |
64 | fzero %f2 | |
1da177e4 LT |
65 | faddd %f0, %f2, %f4 |
66 | fmuld %f0, %f2, %f6 | |
67 | faddd %f0, %f2, %f8 | |
68 | fmuld %f0, %f2, %f10 | |
69 | faddd %f0, %f2, %f12 | |
70 | fmuld %f0, %f2, %f14 | |
71 | faddd %f0, %f2, %f16 | |
72 | fmuld %f0, %f2, %f18 | |
73 | faddd %f0, %f2, %f20 | |
74 | fmuld %f0, %f2, %f22 | |
75 | faddd %f0, %f2, %f24 | |
76 | fmuld %f0, %f2, %f26 | |
77 | faddd %f0, %f2, %f28 | |
78 | fmuld %f0, %f2, %f30 | |
79 | faddd %f0, %f2, %f32 | |
80 | fmuld %f0, %f2, %f34 | |
81 | faddd %f0, %f2, %f36 | |
82 | fmuld %f0, %f2, %f38 | |
83 | faddd %f0, %f2, %f40 | |
84 | fmuld %f0, %f2, %f42 | |
85 | faddd %f0, %f2, %f44 | |
86 | fmuld %f0, %f2, %f46 | |
87 | faddd %f0, %f2, %f48 | |
88 | fmuld %f0, %f2, %f50 | |
89 | faddd %f0, %f2, %f52 | |
90 | fmuld %f0, %f2, %f54 | |
91 | faddd %f0, %f2, %f56 | |
92 | fmuld %f0, %f2, %f58 | |
93 | b,pt %xcc, fpdis_exit2 | |
94 | faddd %f0, %f2, %f60 | |
95 | 1: mov SECONDARY_CONTEXT, %g3 | |
96 | add %g6, TI_FPREGS + 0x80, %g1 | |
97 | faddd %f0, %f2, %f4 | |
98 | fmuld %f0, %f2, %f6 | |
8b11bd12 DM |
99 | |
100 | 661: ldxa [%g3] ASI_DMMU, %g5 | |
101 | .section .sun4v_1insn_patch, "ax" | |
102 | .word 661b | |
103 | ldxa [%g3] ASI_MMU, %g5 | |
104 | .previous | |
105 | ||
0835ae0f DM |
106 | sethi %hi(sparc64_kern_sec_context), %g2 |
107 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 | |
8b11bd12 DM |
108 | |
109 | 661: stxa %g2, [%g3] ASI_DMMU | |
110 | .section .sun4v_1insn_patch, "ax" | |
111 | .word 661b | |
112 | stxa %g2, [%g3] ASI_MMU | |
113 | .previous | |
114 | ||
1da177e4 LT |
115 | membar #Sync |
116 | add %g6, TI_FPREGS + 0xc0, %g2 | |
117 | faddd %f0, %f2, %f8 | |
118 | fmuld %f0, %f2, %f10 | |
ba639933 DM |
119 | membar #Sync |
120 | ldda [%g1] ASI_BLK_S, %f32 | |
1da177e4 | 121 | ldda [%g2] ASI_BLK_S, %f48 |
ba639933 | 122 | membar #Sync |
1da177e4 LT |
123 | faddd %f0, %f2, %f12 |
124 | fmuld %f0, %f2, %f14 | |
125 | faddd %f0, %f2, %f16 | |
126 | fmuld %f0, %f2, %f18 | |
127 | faddd %f0, %f2, %f20 | |
128 | fmuld %f0, %f2, %f22 | |
129 | faddd %f0, %f2, %f24 | |
130 | fmuld %f0, %f2, %f26 | |
131 | faddd %f0, %f2, %f28 | |
132 | fmuld %f0, %f2, %f30 | |
133 | b,pt %xcc, fpdis_exit | |
b445e26c | 134 | nop |
1da177e4 LT |
135 | 2: andcc %g5, FPRS_DU, %g0 |
136 | bne,pt %icc, 3f | |
137 | fzero %f32 | |
138 | mov SECONDARY_CONTEXT, %g3 | |
139 | fzero %f34 | |
8b11bd12 DM |
140 | |
141 | 661: ldxa [%g3] ASI_DMMU, %g5 | |
142 | .section .sun4v_1insn_patch, "ax" | |
143 | .word 661b | |
144 | ldxa [%g3] ASI_MMU, %g5 | |
145 | .previous | |
146 | ||
1da177e4 | 147 | add %g6, TI_FPREGS, %g1 |
0835ae0f DM |
148 | sethi %hi(sparc64_kern_sec_context), %g2 |
149 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 | |
8b11bd12 DM |
150 | |
151 | 661: stxa %g2, [%g3] ASI_DMMU | |
152 | .section .sun4v_1insn_patch, "ax" | |
153 | .word 661b | |
154 | stxa %g2, [%g3] ASI_MMU | |
155 | .previous | |
156 | ||
1da177e4 LT |
157 | membar #Sync |
158 | add %g6, TI_FPREGS + 0x40, %g2 | |
159 | faddd %f32, %f34, %f36 | |
160 | fmuld %f32, %f34, %f38 | |
ba639933 DM |
161 | membar #Sync |
162 | ldda [%g1] ASI_BLK_S, %f0 | |
1da177e4 | 163 | ldda [%g2] ASI_BLK_S, %f16 |
ba639933 | 164 | membar #Sync |
1da177e4 LT |
165 | faddd %f32, %f34, %f40 |
166 | fmuld %f32, %f34, %f42 | |
167 | faddd %f32, %f34, %f44 | |
168 | fmuld %f32, %f34, %f46 | |
169 | faddd %f32, %f34, %f48 | |
170 | fmuld %f32, %f34, %f50 | |
171 | faddd %f32, %f34, %f52 | |
172 | fmuld %f32, %f34, %f54 | |
173 | faddd %f32, %f34, %f56 | |
174 | fmuld %f32, %f34, %f58 | |
175 | faddd %f32, %f34, %f60 | |
176 | fmuld %f32, %f34, %f62 | |
177 | ba,pt %xcc, fpdis_exit | |
b445e26c | 178 | nop |
1da177e4 LT |
179 | 3: mov SECONDARY_CONTEXT, %g3 |
180 | add %g6, TI_FPREGS, %g1 | |
8b11bd12 DM |
181 | |
182 | 661: ldxa [%g3] ASI_DMMU, %g5 | |
183 | .section .sun4v_1insn_patch, "ax" | |
184 | .word 661b | |
185 | ldxa [%g3] ASI_MMU, %g5 | |
186 | .previous | |
187 | ||
0835ae0f DM |
188 | sethi %hi(sparc64_kern_sec_context), %g2 |
189 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 | |
8b11bd12 DM |
190 | |
191 | 661: stxa %g2, [%g3] ASI_DMMU | |
192 | .section .sun4v_1insn_patch, "ax" | |
193 | .word 661b | |
194 | stxa %g2, [%g3] ASI_MMU | |
195 | .previous | |
196 | ||
1da177e4 LT |
197 | membar #Sync |
198 | mov 0x40, %g2 | |
ba639933 DM |
199 | membar #Sync |
200 | ldda [%g1] ASI_BLK_S, %f0 | |
1da177e4 LT |
201 | ldda [%g1 + %g2] ASI_BLK_S, %f16 |
202 | add %g1, 0x80, %g1 | |
203 | ldda [%g1] ASI_BLK_S, %f32 | |
204 | ldda [%g1 + %g2] ASI_BLK_S, %f48 | |
205 | membar #Sync | |
206 | fpdis_exit: | |
8b11bd12 DM |
207 | |
208 | 661: stxa %g5, [%g3] ASI_DMMU | |
209 | .section .sun4v_1insn_patch, "ax" | |
210 | .word 661b | |
211 | stxa %g5, [%g3] ASI_MMU | |
212 | .previous | |
213 | ||
1da177e4 LT |
214 | membar #Sync |
215 | fpdis_exit2: | |
216 | wr %g7, 0, %gsr | |
217 | ldx [%g6 + TI_XFSR], %fsr | |
218 | rdpr %tstate, %g3 | |
219 | or %g3, %g4, %g3 ! anal... | |
220 | wrpr %g3, %tstate | |
221 | wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits | |
222 | retry | |
223 | ||
224 | .align 32 | |
225 | fp_other_bounce: | |
226 | call do_fpother | |
227 | add %sp, PTREGS_OFF, %o0 | |
228 | ba,pt %xcc, rtrap | |
229 | clr %l6 | |
230 | ||
231 | .globl do_fpother_check_fitos | |
232 | .align 32 | |
233 | do_fpother_check_fitos: | |
ffe483d5 | 234 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
1da177e4 LT |
235 | sethi %hi(fp_other_bounce - 4), %g7 |
236 | or %g7, %lo(fp_other_bounce - 4), %g7 | |
237 | ||
238 | /* NOTE: Need to preserve %g7 until we fully commit | |
239 | * to the fitos fixup. | |
240 | */ | |
241 | stx %fsr, [%g6 + TI_XFSR] | |
242 | rdpr %tstate, %g3 | |
243 | andcc %g3, TSTATE_PRIV, %g0 | |
244 | bne,pn %xcc, do_fptrap_after_fsr | |
245 | nop | |
246 | ldx [%g6 + TI_XFSR], %g3 | |
247 | srlx %g3, 14, %g1 | |
248 | and %g1, 7, %g1 | |
249 | cmp %g1, 2 ! Unfinished FP-OP | |
250 | bne,pn %xcc, do_fptrap_after_fsr | |
251 | sethi %hi(1 << 23), %g1 ! Inexact | |
252 | andcc %g3, %g1, %g0 | |
253 | bne,pn %xcc, do_fptrap_after_fsr | |
254 | rdpr %tpc, %g1 | |
255 | lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail | |
256 | #define FITOS_MASK 0xc1f83fe0 | |
257 | #define FITOS_COMPARE 0x81a01880 | |
258 | sethi %hi(FITOS_MASK), %g1 | |
259 | or %g1, %lo(FITOS_MASK), %g1 | |
260 | and %g3, %g1, %g1 | |
261 | sethi %hi(FITOS_COMPARE), %g2 | |
262 | or %g2, %lo(FITOS_COMPARE), %g2 | |
263 | cmp %g1, %g2 | |
264 | bne,pn %xcc, do_fptrap_after_fsr | |
265 | nop | |
266 | std %f62, [%g6 + TI_FPREGS + (62 * 4)] | |
267 | sethi %hi(fitos_table_1), %g1 | |
268 | and %g3, 0x1f, %g2 | |
269 | or %g1, %lo(fitos_table_1), %g1 | |
270 | sllx %g2, 2, %g2 | |
271 | jmpl %g1 + %g2, %g0 | |
272 | ba,pt %xcc, fitos_emul_continue | |
273 | ||
274 | fitos_table_1: | |
275 | fitod %f0, %f62 | |
276 | fitod %f1, %f62 | |
277 | fitod %f2, %f62 | |
278 | fitod %f3, %f62 | |
279 | fitod %f4, %f62 | |
280 | fitod %f5, %f62 | |
281 | fitod %f6, %f62 | |
282 | fitod %f7, %f62 | |
283 | fitod %f8, %f62 | |
284 | fitod %f9, %f62 | |
285 | fitod %f10, %f62 | |
286 | fitod %f11, %f62 | |
287 | fitod %f12, %f62 | |
288 | fitod %f13, %f62 | |
289 | fitod %f14, %f62 | |
290 | fitod %f15, %f62 | |
291 | fitod %f16, %f62 | |
292 | fitod %f17, %f62 | |
293 | fitod %f18, %f62 | |
294 | fitod %f19, %f62 | |
295 | fitod %f20, %f62 | |
296 | fitod %f21, %f62 | |
297 | fitod %f22, %f62 | |
298 | fitod %f23, %f62 | |
299 | fitod %f24, %f62 | |
300 | fitod %f25, %f62 | |
301 | fitod %f26, %f62 | |
302 | fitod %f27, %f62 | |
303 | fitod %f28, %f62 | |
304 | fitod %f29, %f62 | |
305 | fitod %f30, %f62 | |
306 | fitod %f31, %f62 | |
307 | ||
308 | fitos_emul_continue: | |
309 | sethi %hi(fitos_table_2), %g1 | |
310 | srl %g3, 25, %g2 | |
311 | or %g1, %lo(fitos_table_2), %g1 | |
312 | and %g2, 0x1f, %g2 | |
313 | sllx %g2, 2, %g2 | |
314 | jmpl %g1 + %g2, %g0 | |
315 | ba,pt %xcc, fitos_emul_fini | |
316 | ||
317 | fitos_table_2: | |
318 | fdtos %f62, %f0 | |
319 | fdtos %f62, %f1 | |
320 | fdtos %f62, %f2 | |
321 | fdtos %f62, %f3 | |
322 | fdtos %f62, %f4 | |
323 | fdtos %f62, %f5 | |
324 | fdtos %f62, %f6 | |
325 | fdtos %f62, %f7 | |
326 | fdtos %f62, %f8 | |
327 | fdtos %f62, %f9 | |
328 | fdtos %f62, %f10 | |
329 | fdtos %f62, %f11 | |
330 | fdtos %f62, %f12 | |
331 | fdtos %f62, %f13 | |
332 | fdtos %f62, %f14 | |
333 | fdtos %f62, %f15 | |
334 | fdtos %f62, %f16 | |
335 | fdtos %f62, %f17 | |
336 | fdtos %f62, %f18 | |
337 | fdtos %f62, %f19 | |
338 | fdtos %f62, %f20 | |
339 | fdtos %f62, %f21 | |
340 | fdtos %f62, %f22 | |
341 | fdtos %f62, %f23 | |
342 | fdtos %f62, %f24 | |
343 | fdtos %f62, %f25 | |
344 | fdtos %f62, %f26 | |
345 | fdtos %f62, %f27 | |
346 | fdtos %f62, %f28 | |
347 | fdtos %f62, %f29 | |
348 | fdtos %f62, %f30 | |
349 | fdtos %f62, %f31 | |
350 | ||
351 | fitos_emul_fini: | |
352 | ldd [%g6 + TI_FPREGS + (62 * 4)], %f62 | |
353 | done | |
354 | ||
355 | .globl do_fptrap | |
356 | .align 32 | |
357 | do_fptrap: | |
8e42550c | 358 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
1da177e4 LT |
359 | stx %fsr, [%g6 + TI_XFSR] |
360 | do_fptrap_after_fsr: | |
361 | ldub [%g6 + TI_FPSAVED], %g3 | |
362 | rd %fprs, %g1 | |
363 | or %g3, %g1, %g3 | |
364 | stb %g3, [%g6 + TI_FPSAVED] | |
365 | rd %gsr, %g3 | |
366 | stx %g3, [%g6 + TI_GSR] | |
367 | mov SECONDARY_CONTEXT, %g3 | |
8b11bd12 DM |
368 | |
369 | 661: ldxa [%g3] ASI_DMMU, %g5 | |
370 | .section .sun4v_1insn_patch, "ax" | |
371 | .word 661b | |
372 | ldxa [%g3] ASI_MMU, %g5 | |
373 | .previous | |
374 | ||
0835ae0f DM |
375 | sethi %hi(sparc64_kern_sec_context), %g2 |
376 | ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2 | |
8b11bd12 DM |
377 | |
378 | 661: stxa %g2, [%g3] ASI_DMMU | |
379 | .section .sun4v_1insn_patch, "ax" | |
380 | .word 661b | |
381 | stxa %g2, [%g3] ASI_MMU | |
382 | .previous | |
383 | ||
1da177e4 LT |
384 | membar #Sync |
385 | add %g6, TI_FPREGS, %g2 | |
386 | andcc %g1, FPRS_DL, %g0 | |
387 | be,pn %icc, 4f | |
388 | mov 0x40, %g3 | |
389 | stda %f0, [%g2] ASI_BLK_S | |
390 | stda %f16, [%g2 + %g3] ASI_BLK_S | |
391 | andcc %g1, FPRS_DU, %g0 | |
392 | be,pn %icc, 5f | |
393 | 4: add %g2, 128, %g2 | |
394 | stda %f32, [%g2] ASI_BLK_S | |
395 | stda %f48, [%g2 + %g3] ASI_BLK_S | |
396 | 5: mov SECONDARY_CONTEXT, %g1 | |
397 | membar #Sync | |
8b11bd12 DM |
398 | |
399 | 661: stxa %g5, [%g1] ASI_DMMU | |
400 | .section .sun4v_1insn_patch, "ax" | |
401 | .word 661b | |
402 | stxa %g5, [%g1] ASI_MMU | |
403 | .previous | |
404 | ||
1da177e4 LT |
405 | membar #Sync |
406 | ba,pt %xcc, etrap | |
407 | wr %g0, 0, %fprs | |
408 | ||
1da177e4 LT |
409 | /* The registers for cross calls will be: |
410 | * | |
411 | * DATA 0: [low 32-bits] Address of function to call, jmp to this | |
412 | * [high 32-bits] MMU Context Argument 0, place in %g5 | |
80dc0d6b | 413 | * DATA 1: Address Argument 1, place in %g1 |
1da177e4 LT |
414 | * DATA 2: Address Argument 2, place in %g7 |
415 | * | |
416 | * With this method we can do most of the cross-call tlb/cache | |
417 | * flushing very quickly. | |
1da177e4 LT |
418 | */ |
419 | .text | |
420 | .align 32 | |
421 | .globl do_ivec | |
422 | do_ivec: | |
423 | mov 0x40, %g3 | |
424 | ldxa [%g3 + %g0] ASI_INTR_R, %g3 | |
425 | sethi %hi(KERNBASE), %g4 | |
426 | cmp %g3, %g4 | |
427 | bgeu,pn %xcc, do_ivec_xcall | |
428 | srlx %g3, 32, %g5 | |
429 | stxa %g0, [%g0] ASI_INTR_RECEIVE | |
430 | membar #Sync | |
431 | ||
432 | sethi %hi(ivector_table), %g2 | |
e18e2a00 | 433 | sllx %g3, 3, %g3 |
1da177e4 LT |
434 | or %g2, %lo(ivector_table), %g2 |
435 | add %g2, %g3, %g3 | |
088dd1f8 | 436 | |
ffe483d5 | 437 | TRAP_LOAD_IRQ_WORK(%g6, %g1) |
56fb4df6 | 438 | |
fd0504c3 | 439 | lduw [%g6], %g5 /* g5 = irq_work(cpu) */ |
1da177e4 | 440 | stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */ |
fd0504c3 DM |
441 | stw %g3, [%g6] /* irq_work(cpu) = bucket */ |
442 | wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint | |
1da177e4 LT |
443 | retry |
444 | do_ivec_xcall: | |
445 | mov 0x50, %g1 | |
1da177e4 LT |
446 | ldxa [%g1 + %g0] ASI_INTR_R, %g1 |
447 | srl %g3, 0, %g3 | |
088dd1f8 | 448 | |
1da177e4 LT |
449 | mov 0x60, %g7 |
450 | ldxa [%g7 + %g0] ASI_INTR_R, %g7 | |
451 | stxa %g0, [%g0] ASI_INTR_RECEIVE | |
452 | membar #Sync | |
453 | ba,pt %xcc, 1f | |
454 | nop | |
455 | ||
456 | .align 32 | |
457 | 1: jmpl %g3, %g0 | |
458 | nop | |
459 | ||
1da177e4 LT |
460 | .globl getcc, setcc |
461 | getcc: | |
462 | ldx [%o0 + PT_V9_TSTATE], %o1 | |
463 | srlx %o1, 32, %o1 | |
464 | and %o1, 0xf, %o1 | |
465 | retl | |
466 | stx %o1, [%o0 + PT_V9_G1] | |
467 | setcc: | |
468 | ldx [%o0 + PT_V9_TSTATE], %o1 | |
469 | ldx [%o0 + PT_V9_G1], %o2 | |
470 | or %g0, %ulo(TSTATE_ICC), %o3 | |
471 | sllx %o3, 32, %o3 | |
472 | andn %o1, %o3, %o1 | |
473 | sllx %o2, 32, %o2 | |
474 | and %o2, %o3, %o2 | |
475 | or %o1, %o2, %o1 | |
476 | retl | |
477 | stx %o1, [%o0 + PT_V9_TSTATE] | |
478 | ||
56fb4df6 DM |
479 | .globl utrap_trap |
480 | utrap_trap: /* %g3=handler,%g4=level */ | |
ffe483d5 | 481 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
56fb4df6 DM |
482 | ldx [%g6 + TI_UTRAPS], %g1 |
483 | brnz,pt %g1, invoke_utrap | |
1da177e4 | 484 | nop |
56fb4df6 DM |
485 | |
486 | ba,pt %xcc, etrap | |
487 | rd %pc, %g7 | |
488 | mov %l4, %o1 | |
489 | call bad_trap | |
490 | add %sp, PTREGS_OFF, %o0 | |
491 | ba,pt %xcc, rtrap | |
492 | clr %l6 | |
493 | ||
494 | invoke_utrap: | |
495 | sllx %g3, 3, %g3 | |
496 | ldx [%g1 + %g3], %g1 | |
1da177e4 LT |
497 | save %sp, -128, %sp |
498 | rdpr %tstate, %l6 | |
499 | rdpr %cwp, %l7 | |
500 | andn %l6, TSTATE_CWP, %l6 | |
501 | wrpr %l6, %l7, %tstate | |
502 | rdpr %tpc, %l6 | |
503 | rdpr %tnpc, %l7 | |
504 | wrpr %g1, 0, %tnpc | |
505 | done | |
1da177e4 | 506 | |
6c52a96e DM |
507 | /* We need to carefully read the error status, ACK |
508 | * the errors, prevent recursive traps, and pass the | |
509 | * information on to C code for logging. | |
510 | * | |
511 | * We pass the AFAR in as-is, and we encode the status | |
512 | * information as described in asm-sparc64/sfafsr.h | |
513 | */ | |
514 | .globl __spitfire_access_error | |
515 | __spitfire_access_error: | |
516 | /* Disable ESTATE error reporting so that we do not | |
517 | * take recursive traps and RED state the processor. | |
518 | */ | |
519 | stxa %g0, [%g0] ASI_ESTATE_ERROR_EN | |
520 | membar #Sync | |
521 | ||
522 | mov UDBE_UE, %g1 | |
523 | ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR | |
524 | ||
525 | /* __spitfire_cee_trap branches here with AFSR in %g4 and | |
526 | * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the | |
527 | * ESTATE Error Enable register. | |
528 | */ | |
529 | __spitfire_cee_trap_continue: | |
530 | ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR | |
531 | ||
532 | rdpr %tt, %g3 | |
533 | and %g3, 0x1ff, %g3 ! Paranoia | |
534 | sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3 | |
535 | or %g4, %g3, %g4 | |
536 | rdpr %tl, %g3 | |
537 | cmp %g3, 1 | |
538 | mov 1, %g3 | |
539 | bleu %xcc, 1f | |
540 | sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3 | |
541 | ||
542 | or %g4, %g3, %g4 | |
543 | ||
544 | /* Read in the UDB error register state, clearing the | |
545 | * sticky error bits as-needed. We only clear them if | |
546 | * the UE bit is set. Likewise, __spitfire_cee_trap | |
547 | * below will only do so if the CE bit is set. | |
548 | * | |
549 | * NOTE: UltraSparc-I/II have high and low UDB error | |
550 | * registers, corresponding to the two UDB units | |
551 | * present on those chips. UltraSparc-IIi only | |
552 | * has a single UDB, called "SDB" in the manual. | |
553 | * For IIi the upper UDB register always reads | |
554 | * as zero so for our purposes things will just | |
555 | * work with the checks below. | |
556 | */ | |
557 | 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3 | |
558 | and %g3, 0x3ff, %g7 ! Paranoia | |
559 | sllx %g7, SFSTAT_UDBH_SHIFT, %g7 | |
560 | or %g4, %g7, %g4 | |
561 | andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE | |
562 | be,pn %xcc, 1f | |
563 | nop | |
564 | stxa %g3, [%g0] ASI_UDB_ERROR_W | |
565 | membar #Sync | |
566 | ||
567 | 1: mov 0x18, %g3 | |
568 | ldxa [%g3] ASI_UDBL_ERROR_R, %g3 | |
569 | and %g3, 0x3ff, %g7 ! Paranoia | |
570 | sllx %g7, SFSTAT_UDBL_SHIFT, %g7 | |
571 | or %g4, %g7, %g4 | |
572 | andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE | |
573 | be,pn %xcc, 1f | |
574 | nop | |
575 | mov 0x18, %g7 | |
576 | stxa %g3, [%g7] ASI_UDB_ERROR_W | |
577 | membar #Sync | |
578 | ||
579 | 1: /* Ok, now that we've latched the error state, | |
580 | * clear the sticky bits in the AFSR. | |
581 | */ | |
582 | stxa %g4, [%g0] ASI_AFSR | |
583 | membar #Sync | |
584 | ||
585 | rdpr %tl, %g2 | |
586 | cmp %g2, 1 | |
587 | rdpr %pil, %g2 | |
588 | bleu,pt %xcc, 1f | |
589 | wrpr %g0, 15, %pil | |
590 | ||
591 | ba,pt %xcc, etraptl1 | |
592 | rd %pc, %g7 | |
593 | ||
594 | ba,pt %xcc, 2f | |
595 | nop | |
596 | ||
597 | 1: ba,pt %xcc, etrap_irq | |
598 | rd %pc, %g7 | |
599 | ||
10e26723 DM |
600 | 2: |
601 | #ifdef CONFIG_TRACE_IRQFLAGS | |
602 | call trace_hardirqs_off | |
603 | nop | |
604 | #endif | |
605 | mov %l4, %o1 | |
6c52a96e DM |
606 | mov %l5, %o2 |
607 | call spitfire_access_error | |
608 | add %sp, PTREGS_OFF, %o0 | |
609 | ba,pt %xcc, rtrap | |
610 | clr %l6 | |
611 | ||
612 | /* This is the trap handler entry point for ECC correctable | |
613 | * errors. They are corrected, but we listen for the trap | |
614 | * so that the event can be logged. | |
615 | * | |
616 | * Disrupting errors are either: | |
617 | * 1) single-bit ECC errors during UDB reads to system | |
618 | * memory | |
619 | * 2) data parity errors during write-back events | |
620 | * | |
621 | * As far as I can make out from the manual, the CEE trap | |
622 | * is only for correctable errors during memory read | |
623 | * accesses by the front-end of the processor. | |
624 | * | |
625 | * The code below is only for trap level 1 CEE events, | |
626 | * as it is the only situation where we can safely record | |
627 | * and log. For trap level >1 we just clear the CE bit | |
628 | * in the AFSR and return. | |
629 | * | |
630 | * This is just like __spiftire_access_error above, but it | |
631 | * specifically handles correctable errors. If an | |
632 | * uncorrectable error is indicated in the AFSR we | |
633 | * will branch directly above to __spitfire_access_error | |
634 | * to handle it instead. Uncorrectable therefore takes | |
635 | * priority over correctable, and the error logging | |
636 | * C code will notice this case by inspecting the | |
637 | * trap type. | |
638 | */ | |
639 | .globl __spitfire_cee_trap | |
640 | __spitfire_cee_trap: | |
641 | ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR | |
642 | mov 1, %g3 | |
643 | sllx %g3, SFAFSR_UE_SHIFT, %g3 | |
644 | andcc %g4, %g3, %g0 ! Check for UE | |
645 | bne,pn %xcc, __spitfire_access_error | |
646 | nop | |
647 | ||
648 | /* Ok, in this case we only have a correctable error. | |
649 | * Indicate we only wish to capture that state in register | |
650 | * %g1, and we only disable CE error reporting unlike UE | |
651 | * handling which disables all errors. | |
652 | */ | |
653 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3 | |
654 | andn %g3, ESTATE_ERR_CE, %g3 | |
655 | stxa %g3, [%g0] ASI_ESTATE_ERROR_EN | |
656 | membar #Sync | |
657 | ||
658 | /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */ | |
659 | ba,pt %xcc, __spitfire_cee_trap_continue | |
660 | mov UDBE_CE, %g1 | |
661 | ||
662 | .globl __spitfire_data_access_exception | |
663 | .globl __spitfire_data_access_exception_tl1 | |
664 | __spitfire_data_access_exception_tl1: | |
1da177e4 LT |
665 | rdpr %pstate, %g4 |
666 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate | |
667 | mov TLB_SFSR, %g3 | |
668 | mov DMMU_SFAR, %g5 | |
669 | ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR | |
670 | ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR | |
671 | stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit | |
672 | membar #Sync | |
bde4e4ee DM |
673 | rdpr %tt, %g3 |
674 | cmp %g3, 0x80 ! first win spill/fill trap | |
675 | blu,pn %xcc, 1f | |
676 | cmp %g3, 0xff ! last win spill/fill trap | |
677 | bgu,pn %xcc, 1f | |
678 | nop | |
1da177e4 LT |
679 | ba,pt %xcc, winfix_dax |
680 | rdpr %tpc, %g3 | |
bde4e4ee DM |
681 | 1: sethi %hi(109f), %g7 |
682 | ba,pt %xcc, etraptl1 | |
683 | 109: or %g7, %lo(109b), %g7 | |
684 | mov %l4, %o1 | |
685 | mov %l5, %o2 | |
6c52a96e | 686 | call spitfire_data_access_exception_tl1 |
bde4e4ee DM |
687 | add %sp, PTREGS_OFF, %o0 |
688 | ba,pt %xcc, rtrap | |
689 | clr %l6 | |
690 | ||
6c52a96e | 691 | __spitfire_data_access_exception: |
1da177e4 LT |
692 | rdpr %pstate, %g4 |
693 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate | |
694 | mov TLB_SFSR, %g3 | |
695 | mov DMMU_SFAR, %g5 | |
696 | ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR | |
697 | ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR | |
698 | stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit | |
699 | membar #Sync | |
700 | sethi %hi(109f), %g7 | |
701 | ba,pt %xcc, etrap | |
702 | 109: or %g7, %lo(109b), %g7 | |
703 | mov %l4, %o1 | |
704 | mov %l5, %o2 | |
6c52a96e | 705 | call spitfire_data_access_exception |
1da177e4 LT |
706 | add %sp, PTREGS_OFF, %o0 |
707 | ba,pt %xcc, rtrap | |
708 | clr %l6 | |
709 | ||
6c52a96e DM |
710 | .globl __spitfire_insn_access_exception |
711 | .globl __spitfire_insn_access_exception_tl1 | |
712 | __spitfire_insn_access_exception_tl1: | |
1da177e4 LT |
713 | rdpr %pstate, %g4 |
714 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate | |
715 | mov TLB_SFSR, %g3 | |
5ea68e02 DM |
716 | ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR |
717 | rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC | |
1da177e4 LT |
718 | stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit |
719 | membar #Sync | |
720 | sethi %hi(109f), %g7 | |
721 | ba,pt %xcc, etraptl1 | |
722 | 109: or %g7, %lo(109b), %g7 | |
723 | mov %l4, %o1 | |
724 | mov %l5, %o2 | |
6c52a96e | 725 | call spitfire_insn_access_exception_tl1 |
1da177e4 LT |
726 | add %sp, PTREGS_OFF, %o0 |
727 | ba,pt %xcc, rtrap | |
728 | clr %l6 | |
729 | ||
6c52a96e | 730 | __spitfire_insn_access_exception: |
1da177e4 LT |
731 | rdpr %pstate, %g4 |
732 | wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate | |
733 | mov TLB_SFSR, %g3 | |
5ea68e02 DM |
734 | ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR |
735 | rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC | |
1da177e4 LT |
736 | stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit |
737 | membar #Sync | |
738 | sethi %hi(109f), %g7 | |
739 | ba,pt %xcc, etrap | |
740 | 109: or %g7, %lo(109b), %g7 | |
741 | mov %l4, %o1 | |
742 | mov %l5, %o2 | |
6c52a96e | 743 | call spitfire_insn_access_exception |
1da177e4 LT |
744 | add %sp, PTREGS_OFF, %o0 |
745 | ba,pt %xcc, rtrap | |
746 | clr %l6 | |
747 | ||
1da177e4 LT |
748 | /* These get patched into the trap table at boot time |
749 | * once we know we have a cheetah processor. | |
750 | */ | |
751 | .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1 | |
752 | cheetah_fecc_trap_vector: | |
753 | membar #Sync | |
754 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
755 | andn %g1, DCU_DC | DCU_IC, %g1 | |
756 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
757 | membar #Sync | |
758 | sethi %hi(cheetah_fast_ecc), %g2 | |
759 | jmpl %g2 + %lo(cheetah_fast_ecc), %g0 | |
760 | mov 0, %g1 | |
761 | cheetah_fecc_trap_vector_tl1: | |
762 | membar #Sync | |
763 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
764 | andn %g1, DCU_DC | DCU_IC, %g1 | |
765 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
766 | membar #Sync | |
767 | sethi %hi(cheetah_fast_ecc), %g2 | |
768 | jmpl %g2 + %lo(cheetah_fast_ecc), %g0 | |
769 | mov 1, %g1 | |
770 | .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1 | |
771 | cheetah_cee_trap_vector: | |
772 | membar #Sync | |
773 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
774 | andn %g1, DCU_IC, %g1 | |
775 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
776 | membar #Sync | |
777 | sethi %hi(cheetah_cee), %g2 | |
778 | jmpl %g2 + %lo(cheetah_cee), %g0 | |
779 | mov 0, %g1 | |
780 | cheetah_cee_trap_vector_tl1: | |
781 | membar #Sync | |
782 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
783 | andn %g1, DCU_IC, %g1 | |
784 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
785 | membar #Sync | |
786 | sethi %hi(cheetah_cee), %g2 | |
787 | jmpl %g2 + %lo(cheetah_cee), %g0 | |
788 | mov 1, %g1 | |
789 | .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1 | |
790 | cheetah_deferred_trap_vector: | |
791 | membar #Sync | |
792 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; | |
793 | andn %g1, DCU_DC | DCU_IC, %g1; | |
794 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG; | |
795 | membar #Sync; | |
796 | sethi %hi(cheetah_deferred_trap), %g2 | |
797 | jmpl %g2 + %lo(cheetah_deferred_trap), %g0 | |
798 | mov 0, %g1 | |
799 | cheetah_deferred_trap_vector_tl1: | |
800 | membar #Sync; | |
801 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; | |
802 | andn %g1, DCU_DC | DCU_IC, %g1; | |
803 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG; | |
804 | membar #Sync; | |
805 | sethi %hi(cheetah_deferred_trap), %g2 | |
806 | jmpl %g2 + %lo(cheetah_deferred_trap), %g0 | |
807 | mov 1, %g1 | |
808 | ||
809 | /* Cheetah+ specific traps. These are for the new I/D cache parity | |
810 | * error traps. The first argument to cheetah_plus_parity_handler | |
811 | * is encoded as follows: | |
812 | * | |
813 | * Bit0: 0=dcache,1=icache | |
814 | * Bit1: 0=recoverable,1=unrecoverable | |
815 | */ | |
816 | .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1 | |
817 | cheetah_plus_dcpe_trap_vector: | |
818 | membar #Sync | |
819 | sethi %hi(do_cheetah_plus_data_parity), %g7 | |
820 | jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0 | |
821 | nop | |
822 | nop | |
823 | nop | |
824 | nop | |
825 | nop | |
826 | ||
827 | do_cheetah_plus_data_parity: | |
80dc0d6b DM |
828 | rdpr %pil, %g2 |
829 | wrpr %g0, 15, %pil | |
830 | ba,pt %xcc, etrap_irq | |
1da177e4 | 831 | rd %pc, %g7 |
10e26723 DM |
832 | #ifdef CONFIG_TRACE_IRQFLAGS |
833 | call trace_hardirqs_off | |
834 | nop | |
835 | #endif | |
1da177e4 LT |
836 | mov 0x0, %o0 |
837 | call cheetah_plus_parity_error | |
838 | add %sp, PTREGS_OFF, %o1 | |
80dc0d6b | 839 | ba,a,pt %xcc, rtrap_irq |
1da177e4 LT |
840 | |
841 | cheetah_plus_dcpe_trap_vector_tl1: | |
842 | membar #Sync | |
843 | wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate | |
844 | sethi %hi(do_dcpe_tl1), %g3 | |
845 | jmpl %g3 + %lo(do_dcpe_tl1), %g0 | |
846 | nop | |
847 | nop | |
848 | nop | |
849 | nop | |
850 | ||
851 | .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1 | |
852 | cheetah_plus_icpe_trap_vector: | |
853 | membar #Sync | |
854 | sethi %hi(do_cheetah_plus_insn_parity), %g7 | |
855 | jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0 | |
856 | nop | |
857 | nop | |
858 | nop | |
859 | nop | |
860 | nop | |
861 | ||
862 | do_cheetah_plus_insn_parity: | |
80dc0d6b DM |
863 | rdpr %pil, %g2 |
864 | wrpr %g0, 15, %pil | |
865 | ba,pt %xcc, etrap_irq | |
1da177e4 | 866 | rd %pc, %g7 |
10e26723 DM |
867 | #ifdef CONFIG_TRACE_IRQFLAGS |
868 | call trace_hardirqs_off | |
869 | nop | |
870 | #endif | |
1da177e4 LT |
871 | mov 0x1, %o0 |
872 | call cheetah_plus_parity_error | |
873 | add %sp, PTREGS_OFF, %o1 | |
80dc0d6b | 874 | ba,a,pt %xcc, rtrap_irq |
1da177e4 LT |
875 | |
876 | cheetah_plus_icpe_trap_vector_tl1: | |
877 | membar #Sync | |
878 | wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate | |
879 | sethi %hi(do_icpe_tl1), %g3 | |
880 | jmpl %g3 + %lo(do_icpe_tl1), %g0 | |
881 | nop | |
882 | nop | |
883 | nop | |
884 | nop | |
885 | ||
886 | /* If we take one of these traps when tl >= 1, then we | |
887 | * jump to interrupt globals. If some trap level above us | |
888 | * was also using interrupt globals, we cannot recover. | |
889 | * We may use all interrupt global registers except %g6. | |
890 | */ | |
891 | .globl do_dcpe_tl1, do_icpe_tl1 | |
892 | do_dcpe_tl1: | |
893 | rdpr %tl, %g1 ! Save original trap level | |
894 | mov 1, %g2 ! Setup TSTATE checking loop | |
895 | sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit | |
896 | 1: wrpr %g2, %tl ! Set trap level to check | |
897 | rdpr %tstate, %g4 ! Read TSTATE for this level | |
898 | andcc %g4, %g3, %g0 ! Interrupt globals in use? | |
899 | bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable | |
900 | wrpr %g1, %tl ! Restore original trap level | |
901 | add %g2, 1, %g2 ! Next trap level | |
902 | cmp %g2, %g1 ! Hit them all yet? | |
903 | ble,pt %icc, 1b ! Not yet | |
904 | nop | |
905 | wrpr %g1, %tl ! Restore original trap level | |
906 | do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ | |
80dc0d6b DM |
907 | sethi %hi(dcache_parity_tl1_occurred), %g2 |
908 | lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1 | |
909 | add %g1, 1, %g1 | |
910 | stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)] | |
1da177e4 LT |
911 | /* Reset D-cache parity */ |
912 | sethi %hi(1 << 16), %g1 ! D-cache size | |
913 | mov (1 << 5), %g2 ! D-cache line size | |
914 | sub %g1, %g2, %g1 ! Move down 1 cacheline | |
915 | 1: srl %g1, 14, %g3 ! Compute UTAG | |
916 | membar #Sync | |
917 | stxa %g3, [%g1] ASI_DCACHE_UTAG | |
918 | membar #Sync | |
919 | sub %g2, 8, %g3 ! 64-bit data word within line | |
920 | 2: membar #Sync | |
921 | stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA | |
922 | membar #Sync | |
923 | subcc %g3, 8, %g3 ! Next 64-bit data word | |
924 | bge,pt %icc, 2b | |
925 | nop | |
926 | subcc %g1, %g2, %g1 ! Next cacheline | |
927 | bge,pt %icc, 1b | |
928 | nop | |
929 | ba,pt %xcc, dcpe_icpe_tl1_common | |
930 | nop | |
931 | ||
932 | do_dcpe_tl1_fatal: | |
933 | sethi %hi(1f), %g7 | |
934 | ba,pt %xcc, etraptl1 | |
935 | 1: or %g7, %lo(1b), %g7 | |
936 | mov 0x2, %o0 | |
937 | call cheetah_plus_parity_error | |
938 | add %sp, PTREGS_OFF, %o1 | |
939 | ba,pt %xcc, rtrap | |
940 | clr %l6 | |
941 | ||
942 | do_icpe_tl1: | |
943 | rdpr %tl, %g1 ! Save original trap level | |
944 | mov 1, %g2 ! Setup TSTATE checking loop | |
945 | sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit | |
946 | 1: wrpr %g2, %tl ! Set trap level to check | |
947 | rdpr %tstate, %g4 ! Read TSTATE for this level | |
948 | andcc %g4, %g3, %g0 ! Interrupt globals in use? | |
949 | bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable | |
950 | wrpr %g1, %tl ! Restore original trap level | |
951 | add %g2, 1, %g2 ! Next trap level | |
952 | cmp %g2, %g1 ! Hit them all yet? | |
953 | ble,pt %icc, 1b ! Not yet | |
954 | nop | |
955 | wrpr %g1, %tl ! Restore original trap level | |
956 | do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */ | |
80dc0d6b DM |
957 | sethi %hi(icache_parity_tl1_occurred), %g2 |
958 | lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1 | |
959 | add %g1, 1, %g1 | |
960 | stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)] | |
1da177e4 LT |
961 | /* Flush I-cache */ |
962 | sethi %hi(1 << 15), %g1 ! I-cache size | |
963 | mov (1 << 5), %g2 ! I-cache line size | |
964 | sub %g1, %g2, %g1 | |
965 | 1: or %g1, (2 << 3), %g3 | |
966 | stxa %g0, [%g3] ASI_IC_TAG | |
967 | membar #Sync | |
968 | subcc %g1, %g2, %g1 | |
969 | bge,pt %icc, 1b | |
970 | nop | |
971 | ba,pt %xcc, dcpe_icpe_tl1_common | |
972 | nop | |
973 | ||
974 | do_icpe_tl1_fatal: | |
975 | sethi %hi(1f), %g7 | |
976 | ba,pt %xcc, etraptl1 | |
977 | 1: or %g7, %lo(1b), %g7 | |
978 | mov 0x3, %o0 | |
979 | call cheetah_plus_parity_error | |
980 | add %sp, PTREGS_OFF, %o1 | |
981 | ba,pt %xcc, rtrap | |
982 | clr %l6 | |
983 | ||
984 | dcpe_icpe_tl1_common: | |
985 | /* Flush D-cache, re-enable D/I caches in DCU and finally | |
986 | * retry the trapping instruction. | |
987 | */ | |
988 | sethi %hi(1 << 16), %g1 ! D-cache size | |
989 | mov (1 << 5), %g2 ! D-cache line size | |
990 | sub %g1, %g2, %g1 | |
991 | 1: stxa %g0, [%g1] ASI_DCACHE_TAG | |
992 | membar #Sync | |
993 | subcc %g1, %g2, %g1 | |
994 | bge,pt %icc, 1b | |
995 | nop | |
996 | ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 | |
997 | or %g1, (DCU_DC | DCU_IC), %g1 | |
998 | stxa %g1, [%g0] ASI_DCU_CONTROL_REG | |
999 | membar #Sync | |
1000 | retry | |
1001 | ||
3c2cafaf DM |
1002 | /* Capture I/D/E-cache state into per-cpu error scoreboard. |
1003 | * | |
1004 | * %g1: (TL>=0) ? 1 : 0 | |
1005 | * %g2: scratch | |
1006 | * %g3: scratch | |
1007 | * %g4: AFSR | |
1008 | * %g5: AFAR | |
56fb4df6 | 1009 | * %g6: unused, will have current thread ptr after etrap |
3c2cafaf DM |
1010 | * %g7: scratch |
1011 | */ | |
1012 | __cheetah_log_error: | |
1013 | /* Put "TL1" software bit into AFSR. */ | |
1014 | and %g1, 0x1, %g1 | |
1015 | sllx %g1, 63, %g2 | |
1016 | or %g4, %g2, %g4 | |
1017 | ||
1018 | /* Get log entry pointer for this cpu at this trap level. */ | |
1019 | BRANCH_IF_JALAPENO(g2,g3,50f) | |
1020 | ldxa [%g0] ASI_SAFARI_CONFIG, %g2 | |
1021 | srlx %g2, 17, %g2 | |
1022 | ba,pt %xcc, 60f | |
1023 | and %g2, 0x3ff, %g2 | |
1024 | ||
1025 | 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2 | |
1026 | srlx %g2, 17, %g2 | |
1027 | and %g2, 0x1f, %g2 | |
1028 | ||
1029 | 60: sllx %g2, 9, %g2 | |
1030 | sethi %hi(cheetah_error_log), %g3 | |
1031 | ldx [%g3 + %lo(cheetah_error_log)], %g3 | |
1032 | brz,pn %g3, 80f | |
1033 | nop | |
1034 | ||
1035 | add %g3, %g2, %g3 | |
1036 | sllx %g1, 8, %g1 | |
1037 | add %g3, %g1, %g1 | |
1038 | ||
1039 | /* %g1 holds pointer to the top of the logging scoreboard */ | |
1040 | ldx [%g1 + 0x0], %g7 | |
1041 | cmp %g7, -1 | |
1042 | bne,pn %xcc, 80f | |
1043 | nop | |
1044 | ||
1045 | stx %g4, [%g1 + 0x0] | |
1046 | stx %g5, [%g1 + 0x8] | |
1047 | add %g1, 0x10, %g1 | |
1048 | ||
1049 | /* %g1 now points to D-cache logging area */ | |
1050 | set 0x3ff8, %g2 /* DC_addr mask */ | |
1051 | and %g5, %g2, %g2 /* DC_addr bits of AFAR */ | |
1052 | srlx %g5, 12, %g3 | |
1053 | or %g3, 1, %g3 /* PHYS tag + valid */ | |
1054 | ||
1055 | 10: ldxa [%g2] ASI_DCACHE_TAG, %g7 | |
1056 | cmp %g3, %g7 /* TAG match? */ | |
1057 | bne,pt %xcc, 13f | |
1058 | nop | |
1059 | ||
1060 | /* Yep, what we want, capture state. */ | |
1061 | stx %g2, [%g1 + 0x20] | |
1062 | stx %g7, [%g1 + 0x28] | |
1063 | ||
1064 | /* A membar Sync is required before and after utag access. */ | |
1065 | membar #Sync | |
1066 | ldxa [%g2] ASI_DCACHE_UTAG, %g7 | |
1067 | membar #Sync | |
1068 | stx %g7, [%g1 + 0x30] | |
1069 | ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7 | |
1070 | stx %g7, [%g1 + 0x38] | |
1071 | clr %g3 | |
1072 | ||
1073 | 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7 | |
1074 | stx %g7, [%g1] | |
1075 | add %g3, (1 << 5), %g3 | |
1076 | cmp %g3, (4 << 5) | |
1077 | bl,pt %xcc, 12b | |
1078 | add %g1, 0x8, %g1 | |
1079 | ||
1080 | ba,pt %xcc, 20f | |
1081 | add %g1, 0x20, %g1 | |
1082 | ||
1083 | 13: sethi %hi(1 << 14), %g7 | |
1084 | add %g2, %g7, %g2 | |
1085 | srlx %g2, 14, %g7 | |
1086 | cmp %g7, 4 | |
1087 | bl,pt %xcc, 10b | |
1088 | nop | |
1089 | ||
1090 | add %g1, 0x40, %g1 | |
1091 | ||
1092 | /* %g1 now points to I-cache logging area */ | |
1093 | 20: set 0x1fe0, %g2 /* IC_addr mask */ | |
1094 | and %g5, %g2, %g2 /* IC_addr bits of AFAR */ | |
1095 | sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */ | |
1096 | srlx %g5, (13 - 8), %g3 /* Make PTAG */ | |
1097 | andn %g3, 0xff, %g3 /* Mask off undefined bits */ | |
1098 | ||
1099 | 21: ldxa [%g2] ASI_IC_TAG, %g7 | |
1100 | andn %g7, 0xff, %g7 | |
1101 | cmp %g3, %g7 | |
1102 | bne,pt %xcc, 23f | |
1103 | nop | |
1104 | ||
1105 | /* Yep, what we want, capture state. */ | |
1106 | stx %g2, [%g1 + 0x40] | |
1107 | stx %g7, [%g1 + 0x48] | |
1108 | add %g2, (1 << 3), %g2 | |
1109 | ldxa [%g2] ASI_IC_TAG, %g7 | |
1110 | add %g2, (1 << 3), %g2 | |
1111 | stx %g7, [%g1 + 0x50] | |
1112 | ldxa [%g2] ASI_IC_TAG, %g7 | |
1113 | add %g2, (1 << 3), %g2 | |
1114 | stx %g7, [%g1 + 0x60] | |
1115 | ldxa [%g2] ASI_IC_TAG, %g7 | |
1116 | stx %g7, [%g1 + 0x68] | |
1117 | sub %g2, (3 << 3), %g2 | |
1118 | ldxa [%g2] ASI_IC_STAG, %g7 | |
1119 | stx %g7, [%g1 + 0x58] | |
1120 | clr %g3 | |
1121 | srlx %g2, 2, %g2 | |
1122 | ||
1123 | 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7 | |
1124 | stx %g7, [%g1] | |
1125 | add %g3, (1 << 3), %g3 | |
1126 | cmp %g3, (8 << 3) | |
1127 | bl,pt %xcc, 22b | |
1128 | add %g1, 0x8, %g1 | |
1129 | ||
1130 | ba,pt %xcc, 30f | |
1131 | add %g1, 0x30, %g1 | |
1132 | ||
1133 | 23: sethi %hi(1 << 14), %g7 | |
1134 | add %g2, %g7, %g2 | |
1135 | srlx %g2, 14, %g7 | |
1136 | cmp %g7, 4 | |
1137 | bl,pt %xcc, 21b | |
1138 | nop | |
1139 | ||
1140 | add %g1, 0x70, %g1 | |
1141 | ||
1142 | /* %g1 now points to E-cache logging area */ | |
1143 | 30: andn %g5, (32 - 1), %g2 | |
1144 | stx %g2, [%g1 + 0x20] | |
1145 | ldxa [%g2] ASI_EC_TAG_DATA, %g7 | |
1146 | stx %g7, [%g1 + 0x28] | |
1147 | ldxa [%g2] ASI_EC_R, %g0 | |
1148 | clr %g3 | |
1149 | ||
1150 | 31: ldxa [%g3] ASI_EC_DATA, %g7 | |
1151 | stx %g7, [%g1 + %g3] | |
1152 | add %g3, 0x8, %g3 | |
1153 | cmp %g3, 0x20 | |
1154 | ||
1155 | bl,pt %xcc, 31b | |
1156 | nop | |
1157 | 80: | |
1158 | rdpr %tt, %g2 | |
1159 | cmp %g2, 0x70 | |
1160 | be c_fast_ecc | |
1161 | cmp %g2, 0x63 | |
1162 | be c_cee | |
1163 | nop | |
1164 | ba,pt %xcc, c_deferred | |
1165 | ||
1da177e4 LT |
1166 | /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc |
1167 | * in the trap table. That code has done a memory barrier | |
1168 | * and has disabled both the I-cache and D-cache in the DCU | |
1169 | * control register. The I-cache is disabled so that we may | |
1170 | * capture the corrupted cache line, and the D-cache is disabled | |
1171 | * because corrupt data may have been placed there and we don't | |
1172 | * want to reference it. | |
1173 | * | |
1174 | * %g1 is one if this trap occurred at %tl >= 1. | |
1175 | * | |
1176 | * Next, we turn off error reporting so that we don't recurse. | |
1177 | */ | |
1178 | .globl cheetah_fast_ecc | |
1179 | cheetah_fast_ecc: | |
1180 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 | |
1181 | andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 | |
1182 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN | |
1183 | membar #Sync | |
1184 | ||
1185 | /* Fetch and clear AFSR/AFAR */ | |
1186 | ldxa [%g0] ASI_AFSR, %g4 | |
1187 | ldxa [%g0] ASI_AFAR, %g5 | |
1188 | stxa %g4, [%g0] ASI_AFSR | |
1189 | membar #Sync | |
1190 | ||
3c2cafaf DM |
1191 | ba,pt %xcc, __cheetah_log_error |
1192 | nop | |
1da177e4 | 1193 | |
3c2cafaf | 1194 | c_fast_ecc: |
1da177e4 LT |
1195 | rdpr %pil, %g2 |
1196 | wrpr %g0, 15, %pil | |
1197 | ba,pt %xcc, etrap_irq | |
1198 | rd %pc, %g7 | |
10e26723 DM |
1199 | #ifdef CONFIG_TRACE_IRQFLAGS |
1200 | call trace_hardirqs_off | |
1201 | nop | |
1202 | #endif | |
1da177e4 LT |
1203 | mov %l4, %o1 |
1204 | mov %l5, %o2 | |
1205 | call cheetah_fecc_handler | |
1206 | add %sp, PTREGS_OFF, %o0 | |
1207 | ba,a,pt %xcc, rtrap_irq | |
1208 | ||
1209 | /* Our caller has disabled I-cache and performed membar Sync. */ | |
1210 | .globl cheetah_cee | |
1211 | cheetah_cee: | |
1212 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 | |
1213 | andn %g2, ESTATE_ERROR_CEEN, %g2 | |
1214 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN | |
1215 | membar #Sync | |
1216 | ||
1217 | /* Fetch and clear AFSR/AFAR */ | |
1218 | ldxa [%g0] ASI_AFSR, %g4 | |
1219 | ldxa [%g0] ASI_AFAR, %g5 | |
1220 | stxa %g4, [%g0] ASI_AFSR | |
1221 | membar #Sync | |
1222 | ||
3c2cafaf DM |
1223 | ba,pt %xcc, __cheetah_log_error |
1224 | nop | |
1da177e4 | 1225 | |
3c2cafaf | 1226 | c_cee: |
1da177e4 LT |
1227 | rdpr %pil, %g2 |
1228 | wrpr %g0, 15, %pil | |
1229 | ba,pt %xcc, etrap_irq | |
1230 | rd %pc, %g7 | |
10e26723 DM |
1231 | #ifdef CONFIG_TRACE_IRQFLAGS |
1232 | call trace_hardirqs_off | |
1233 | nop | |
1234 | #endif | |
1da177e4 LT |
1235 | mov %l4, %o1 |
1236 | mov %l5, %o2 | |
1237 | call cheetah_cee_handler | |
1238 | add %sp, PTREGS_OFF, %o0 | |
1239 | ba,a,pt %xcc, rtrap_irq | |
1240 | ||
1241 | /* Our caller has disabled I-cache+D-cache and performed membar Sync. */ | |
1242 | .globl cheetah_deferred_trap | |
1243 | cheetah_deferred_trap: | |
1244 | ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2 | |
1245 | andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2 | |
1246 | stxa %g2, [%g0] ASI_ESTATE_ERROR_EN | |
1247 | membar #Sync | |
1248 | ||
1249 | /* Fetch and clear AFSR/AFAR */ | |
1250 | ldxa [%g0] ASI_AFSR, %g4 | |
1251 | ldxa [%g0] ASI_AFAR, %g5 | |
1252 | stxa %g4, [%g0] ASI_AFSR | |
1253 | membar #Sync | |
1254 | ||
3c2cafaf DM |
1255 | ba,pt %xcc, __cheetah_log_error |
1256 | nop | |
1da177e4 | 1257 | |
3c2cafaf | 1258 | c_deferred: |
1da177e4 LT |
1259 | rdpr %pil, %g2 |
1260 | wrpr %g0, 15, %pil | |
1261 | ba,pt %xcc, etrap_irq | |
1262 | rd %pc, %g7 | |
10e26723 DM |
1263 | #ifdef CONFIG_TRACE_IRQFLAGS |
1264 | call trace_hardirqs_off | |
1265 | nop | |
1266 | #endif | |
1da177e4 LT |
1267 | mov %l4, %o1 |
1268 | mov %l5, %o2 | |
1269 | call cheetah_deferred_handler | |
1270 | add %sp, PTREGS_OFF, %o0 | |
1271 | ba,a,pt %xcc, rtrap_irq | |
1272 | ||
1273 | .globl __do_privact | |
1274 | __do_privact: | |
1275 | mov TLB_SFSR, %g3 | |
1276 | stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit | |
1277 | membar #Sync | |
1278 | sethi %hi(109f), %g7 | |
1279 | ba,pt %xcc, etrap | |
1280 | 109: or %g7, %lo(109b), %g7 | |
1281 | call do_privact | |
1282 | add %sp, PTREGS_OFF, %o0 | |
1283 | ba,pt %xcc, rtrap | |
1284 | clr %l6 | |
1285 | ||
1286 | .globl do_mna | |
1287 | do_mna: | |
1288 | rdpr %tl, %g3 | |
1289 | cmp %g3, 1 | |
1290 | ||
1291 | /* Setup %g4/%g5 now as they are used in the | |
1292 | * winfixup code. | |
1293 | */ | |
1294 | mov TLB_SFSR, %g3 | |
1295 | mov DMMU_SFAR, %g4 | |
1296 | ldxa [%g4] ASI_DMMU, %g4 | |
1297 | ldxa [%g3] ASI_DMMU, %g5 | |
1298 | stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit | |
1299 | membar #Sync | |
1300 | bgu,pn %icc, winfix_mna | |
1301 | rdpr %tpc, %g3 | |
1302 | ||
1303 | 1: sethi %hi(109f), %g7 | |
1304 | ba,pt %xcc, etrap | |
1305 | 109: or %g7, %lo(109b), %g7 | |
1306 | mov %l4, %o1 | |
1307 | mov %l5, %o2 | |
1308 | call mem_address_unaligned | |
1309 | add %sp, PTREGS_OFF, %o0 | |
1310 | ba,pt %xcc, rtrap | |
1311 | clr %l6 | |
1312 | ||
1313 | .globl do_lddfmna | |
1314 | do_lddfmna: | |
1315 | sethi %hi(109f), %g7 | |
1316 | mov TLB_SFSR, %g4 | |
1317 | ldxa [%g4] ASI_DMMU, %g5 | |
1318 | stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit | |
1319 | membar #Sync | |
1320 | mov DMMU_SFAR, %g4 | |
1321 | ldxa [%g4] ASI_DMMU, %g4 | |
1322 | ba,pt %xcc, etrap | |
1323 | 109: or %g7, %lo(109b), %g7 | |
1324 | mov %l4, %o1 | |
1325 | mov %l5, %o2 | |
1326 | call handle_lddfmna | |
1327 | add %sp, PTREGS_OFF, %o0 | |
1328 | ba,pt %xcc, rtrap | |
1329 | clr %l6 | |
1330 | ||
1331 | .globl do_stdfmna | |
1332 | do_stdfmna: | |
1333 | sethi %hi(109f), %g7 | |
1334 | mov TLB_SFSR, %g4 | |
1335 | ldxa [%g4] ASI_DMMU, %g5 | |
1336 | stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit | |
1337 | membar #Sync | |
1338 | mov DMMU_SFAR, %g4 | |
1339 | ldxa [%g4] ASI_DMMU, %g4 | |
1340 | ba,pt %xcc, etrap | |
1341 | 109: or %g7, %lo(109b), %g7 | |
1342 | mov %l4, %o1 | |
1343 | mov %l5, %o2 | |
1344 | call handle_stdfmna | |
1345 | add %sp, PTREGS_OFF, %o0 | |
1346 | ba,pt %xcc, rtrap | |
1347 | clr %l6 | |
1348 | ||
1349 | .globl breakpoint_trap | |
1350 | breakpoint_trap: | |
1351 | call sparc_breakpoint | |
1352 | add %sp, PTREGS_OFF, %o0 | |
1353 | ba,pt %xcc, rtrap | |
1354 | nop | |
1355 | ||
1356 | #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \ | |
1357 | defined(CONFIG_SOLARIS_EMUL_MODULE) | |
1358 | /* SunOS uses syscall zero as the 'indirect syscall' it looks | |
1359 | * like indir_syscall(scall_num, arg0, arg1, arg2...); etc. | |
1360 | * This is complete brain damage. | |
1361 | */ | |
1362 | .globl sunos_indir | |
1363 | sunos_indir: | |
1364 | srl %o0, 0, %o0 | |
1365 | mov %o7, %l4 | |
1366 | cmp %o0, NR_SYSCALLS | |
1367 | blu,a,pt %icc, 1f | |
1368 | sll %o0, 0x2, %o0 | |
1369 | sethi %hi(sunos_nosys), %l6 | |
1370 | b,pt %xcc, 2f | |
1371 | or %l6, %lo(sunos_nosys), %l6 | |
1372 | 1: sethi %hi(sunos_sys_table), %l7 | |
1373 | or %l7, %lo(sunos_sys_table), %l7 | |
1374 | lduw [%l7 + %o0], %l6 | |
1375 | 2: mov %o1, %o0 | |
1376 | mov %o2, %o1 | |
1377 | mov %o3, %o2 | |
1378 | mov %o4, %o3 | |
1379 | mov %o5, %o4 | |
1380 | call %l6 | |
1381 | mov %l4, %o7 | |
1382 | ||
1383 | .globl sunos_getpid | |
1384 | sunos_getpid: | |
1385 | call sys_getppid | |
1386 | nop | |
1387 | call sys_getpid | |
1388 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I1] | |
1389 | b,pt %xcc, ret_sys_call | |
1390 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] | |
1391 | ||
1392 | /* SunOS getuid() returns uid in %o0 and euid in %o1 */ | |
1393 | .globl sunos_getuid | |
1394 | sunos_getuid: | |
1395 | call sys32_geteuid16 | |
1396 | nop | |
1397 | call sys32_getuid16 | |
1398 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I1] | |
1399 | b,pt %xcc, ret_sys_call | |
1400 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] | |
1401 | ||
1402 | /* SunOS getgid() returns gid in %o0 and egid in %o1 */ | |
1403 | .globl sunos_getgid | |
1404 | sunos_getgid: | |
1405 | call sys32_getegid16 | |
1406 | nop | |
1407 | call sys32_getgid16 | |
1408 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I1] | |
1409 | b,pt %xcc, ret_sys_call | |
1410 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] | |
1411 | #endif | |
1412 | ||
1413 | /* SunOS's execv() call only specifies the argv argument, the | |
1414 | * environment settings are the same as the calling processes. | |
1415 | */ | |
1416 | .globl sunos_execv | |
1417 | sys_execve: | |
1418 | sethi %hi(sparc_execve), %g1 | |
1419 | ba,pt %xcc, execve_merge | |
1420 | or %g1, %lo(sparc_execve), %g1 | |
1421 | #ifdef CONFIG_COMPAT | |
1422 | .globl sys_execve | |
1423 | sunos_execv: | |
1424 | stx %g0, [%sp + PTREGS_OFF + PT_V9_I2] | |
1425 | .globl sys32_execve | |
1426 | sys32_execve: | |
1427 | sethi %hi(sparc32_execve), %g1 | |
1428 | or %g1, %lo(sparc32_execve), %g1 | |
1429 | #endif | |
1430 | execve_merge: | |
1431 | flushw | |
1432 | jmpl %g1, %g0 | |
1433 | add %sp, PTREGS_OFF, %o0 | |
1434 | ||
1435 | .globl sys_pipe, sys_sigpause, sys_nis_syscall | |
1da177e4 LT |
1436 | .globl sys_rt_sigreturn |
1437 | .globl sys_ptrace | |
1438 | .globl sys_sigaltstack | |
1439 | .align 32 | |
1440 | sys_pipe: ba,pt %xcc, sparc_pipe | |
1441 | add %sp, PTREGS_OFF, %o0 | |
1442 | sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall | |
1443 | add %sp, PTREGS_OFF, %o0 | |
1444 | sys_memory_ordering: | |
1445 | ba,pt %xcc, sparc_memory_ordering | |
1446 | add %sp, PTREGS_OFF, %o1 | |
1447 | sys_sigaltstack:ba,pt %xcc, do_sigaltstack | |
1448 | add %i6, STACK_BIAS, %o2 | |
1449 | #ifdef CONFIG_COMPAT | |
1450 | .globl sys32_sigstack | |
1451 | sys32_sigstack: ba,pt %xcc, do_sys32_sigstack | |
1452 | mov %i6, %o2 | |
1453 | .globl sys32_sigaltstack | |
1454 | sys32_sigaltstack: | |
1455 | ba,pt %xcc, do_sys32_sigaltstack | |
1456 | mov %i6, %o2 | |
1457 | #endif | |
1458 | .align 32 | |
1da177e4 LT |
1459 | #ifdef CONFIG_COMPAT |
1460 | .globl sys32_sigreturn | |
1461 | sys32_sigreturn: | |
1462 | add %sp, PTREGS_OFF, %o0 | |
1463 | call do_sigreturn32 | |
1464 | add %o7, 1f-.-4, %o7 | |
1465 | nop | |
1466 | #endif | |
1467 | sys_rt_sigreturn: | |
1468 | add %sp, PTREGS_OFF, %o0 | |
1469 | call do_rt_sigreturn | |
1470 | add %o7, 1f-.-4, %o7 | |
1471 | nop | |
1472 | #ifdef CONFIG_COMPAT | |
1473 | .globl sys32_rt_sigreturn | |
1474 | sys32_rt_sigreturn: | |
1475 | add %sp, PTREGS_OFF, %o0 | |
1476 | call do_rt_sigreturn32 | |
1477 | add %o7, 1f-.-4, %o7 | |
1478 | nop | |
1479 | #endif | |
1480 | sys_ptrace: add %sp, PTREGS_OFF, %o0 | |
1481 | call do_ptrace | |
1482 | add %o7, 1f-.-4, %o7 | |
1483 | nop | |
1484 | .align 32 | |
1485 | 1: ldx [%curptr + TI_FLAGS], %l5 | |
f7ceba36 | 1486 | andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 |
1da177e4 LT |
1487 | be,pt %icc, rtrap |
1488 | clr %l6 | |
8d8a6479 | 1489 | add %sp, PTREGS_OFF, %o0 |
1da177e4 | 1490 | call syscall_trace |
8d8a6479 | 1491 | mov 1, %o1 |
1da177e4 LT |
1492 | |
1493 | ba,pt %xcc, rtrap | |
1494 | clr %l6 | |
1495 | ||
1496 | /* This is how fork() was meant to be done, 8 instruction entry. | |
1497 | * | |
1498 | * I questioned the following code briefly, let me clear things | |
1499 | * up so you must not reason on it like I did. | |
1500 | * | |
1501 | * Know the fork_kpsr etc. we use in the sparc32 port? We don't | |
1502 | * need it here because the only piece of window state we copy to | |
1503 | * the child is the CWP register. Even if the parent sleeps, | |
1504 | * we are safe because we stuck it into pt_regs of the parent | |
1505 | * so it will not change. | |
1506 | * | |
1507 | * XXX This raises the question, whether we can do the same on | |
1508 | * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The | |
1509 | * XXX answer is yes. We stick fork_kpsr in UREG_G0 and | |
1510 | * XXX fork_kwim in UREG_G1 (global registers are considered | |
1511 | * XXX volatile across a system call in the sparc ABI I think | |
1512 | * XXX if it isn't we can use regs->y instead, anyone who depends | |
1513 | * XXX upon the Y register being preserved across a fork deserves | |
1514 | * XXX to lose). | |
1515 | * | |
1516 | * In fact we should take advantage of that fact for other things | |
1517 | * during system calls... | |
1518 | */ | |
1519 | .globl sys_fork, sys_vfork, sys_clone, sparc_exit | |
1520 | .globl ret_from_syscall | |
1521 | .align 32 | |
1522 | sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */ | |
1523 | sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0 | |
1524 | or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0 | |
1525 | ba,pt %xcc, sys_clone | |
1526 | sys_fork: clr %o1 | |
1527 | mov SIGCHLD, %o0 | |
1528 | sys_clone: flushw | |
1529 | movrz %o1, %fp, %o1 | |
1530 | mov 0, %o3 | |
1531 | ba,pt %xcc, sparc_do_fork | |
1532 | add %sp, PTREGS_OFF, %o2 | |
1533 | ret_from_syscall: | |
db7d9a4e DM |
1534 | /* Clear current_thread_info()->new_child, and |
1535 | * check performance counter stuff too. | |
1da177e4 | 1536 | */ |
db7d9a4e DM |
1537 | stb %g0, [%g6 + TI_NEW_CHILD] |
1538 | ldx [%g6 + TI_FLAGS], %l0 | |
1da177e4 LT |
1539 | call schedule_tail |
1540 | mov %g7, %o0 | |
1541 | andcc %l0, _TIF_PERFCTR, %g0 | |
1542 | be,pt %icc, 1f | |
1543 | nop | |
1544 | ldx [%g6 + TI_PCR], %o7 | |
1545 | wr %g0, %o7, %pcr | |
1546 | ||
1547 | /* Blackbird errata workaround. See commentary in | |
1548 | * smp.c:smp_percpu_timer_interrupt() for more | |
1549 | * information. | |
1550 | */ | |
1551 | ba,pt %xcc, 99f | |
1552 | nop | |
1553 | .align 64 | |
1554 | 99: wr %g0, %g0, %pic | |
1555 | rd %pic, %g0 | |
1556 | ||
1557 | 1: b,pt %xcc, ret_sys_call | |
1558 | ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0 | |
764afe2e DM |
1559 | sparc_exit: rdpr %pstate, %g2 |
1560 | wrpr %g2, PSTATE_IE, %pstate | |
1da177e4 LT |
1561 | rdpr %otherwin, %g1 |
1562 | rdpr %cansave, %g3 | |
1563 | add %g3, %g1, %g3 | |
1564 | wrpr %g3, 0x0, %cansave | |
1565 | wrpr %g0, 0x0, %otherwin | |
764afe2e | 1566 | wrpr %g2, 0x0, %pstate |
1da177e4 LT |
1567 | ba,pt %xcc, sys_exit |
1568 | stb %g0, [%g6 + TI_WSAVED] | |
1569 | ||
1570 | linux_sparc_ni_syscall: | |
1571 | sethi %hi(sys_ni_syscall), %l7 | |
1572 | b,pt %xcc, 4f | |
1573 | or %l7, %lo(sys_ni_syscall), %l7 | |
1574 | ||
1575 | linux_syscall_trace32: | |
8d8a6479 | 1576 | add %sp, PTREGS_OFF, %o0 |
1da177e4 | 1577 | call syscall_trace |
8d8a6479 | 1578 | clr %o1 |
1da177e4 | 1579 | srl %i0, 0, %o0 |
8d8a6479 | 1580 | srl %i4, 0, %o4 |
1da177e4 LT |
1581 | srl %i1, 0, %o1 |
1582 | srl %i2, 0, %o2 | |
1583 | b,pt %xcc, 2f | |
1584 | srl %i3, 0, %o3 | |
1585 | ||
1586 | linux_syscall_trace: | |
8d8a6479 | 1587 | add %sp, PTREGS_OFF, %o0 |
1da177e4 | 1588 | call syscall_trace |
8d8a6479 | 1589 | clr %o1 |
1da177e4 LT |
1590 | mov %i0, %o0 |
1591 | mov %i1, %o1 | |
1592 | mov %i2, %o2 | |
1593 | mov %i3, %o3 | |
1594 | b,pt %xcc, 2f | |
1595 | mov %i4, %o4 | |
1596 | ||
1597 | ||
1598 | /* Linux 32-bit and SunOS system calls enter here... */ | |
1599 | .align 32 | |
1600 | .globl linux_sparc_syscall32 | |
1601 | linux_sparc_syscall32: | |
1602 | /* Direct access to user regs, much faster. */ | |
1603 | cmp %g1, NR_SYSCALLS ! IEU1 Group | |
1604 | bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI | |
1605 | srl %i0, 0, %o0 ! IEU0 | |
1606 | sll %g1, 2, %l4 ! IEU0 Group | |
1da177e4 LT |
1607 | srl %i4, 0, %o4 ! IEU1 |
1608 | lduw [%l7 + %l4], %l7 ! Load | |
1609 | srl %i1, 0, %o1 ! IEU0 Group | |
1610 | ldx [%curptr + TI_FLAGS], %l0 ! Load | |
1611 | ||
1612 | srl %i5, 0, %o5 ! IEU1 | |
1613 | srl %i2, 0, %o2 ! IEU0 Group | |
f7ceba36 | 1614 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 |
1da177e4 LT |
1615 | bne,pn %icc, linux_syscall_trace32 ! CTI |
1616 | mov %i0, %l5 ! IEU1 | |
1617 | call %l7 ! CTI Group brk forced | |
1618 | srl %i3, 0, %o3 ! IEU0 | |
1619 | ba,a,pt %xcc, 3f | |
1620 | ||
1621 | /* Linux native and SunOS system calls enter here... */ | |
1622 | .align 32 | |
1623 | .globl linux_sparc_syscall, ret_sys_call | |
1624 | linux_sparc_syscall: | |
1625 | /* Direct access to user regs, much faster. */ | |
1626 | cmp %g1, NR_SYSCALLS ! IEU1 Group | |
1627 | bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI | |
1628 | mov %i0, %o0 ! IEU0 | |
1629 | sll %g1, 2, %l4 ! IEU0 Group | |
1da177e4 LT |
1630 | mov %i1, %o1 ! IEU1 |
1631 | lduw [%l7 + %l4], %l7 ! Load | |
1632 | 4: mov %i2, %o2 ! IEU0 Group | |
1633 | ldx [%curptr + TI_FLAGS], %l0 ! Load | |
1634 | ||
1635 | mov %i3, %o3 ! IEU1 | |
1636 | mov %i4, %o4 ! IEU0 Group | |
f7ceba36 | 1637 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0 |
1da177e4 LT |
1638 | bne,pn %icc, linux_syscall_trace ! CTI Group |
1639 | mov %i0, %l5 ! IEU0 | |
1640 | 2: call %l7 ! CTI Group brk forced | |
1641 | mov %i5, %o5 ! IEU0 | |
1642 | nop | |
1643 | ||
1644 | 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] | |
1645 | ret_sys_call: | |
1da177e4 LT |
1646 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3 |
1647 | ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc | |
1648 | sra %o0, 0, %o0 | |
1649 | mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2 | |
1650 | sllx %g2, 32, %g2 | |
1651 | ||
1652 | /* Check if force_successful_syscall_return() | |
1653 | * was invoked. | |
1654 | */ | |
695ca07b RM |
1655 | ldub [%curptr + TI_SYS_NOERROR], %l2 |
1656 | brnz,a,pn %l2, 80f | |
db7d9a4e | 1657 | stb %g0, [%curptr + TI_SYS_NOERROR] |
1da177e4 | 1658 | |
1da177e4 LT |
1659 | cmp %o0, -ERESTART_RESTARTBLOCK |
1660 | bgeu,pn %xcc, 1f | |
f7ceba36 | 1661 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6 |
1da177e4 LT |
1662 | 80: |
1663 | /* System call success, clear Carry condition code. */ | |
1664 | andn %g3, %g2, %g3 | |
1665 | stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE] | |
1666 | bne,pn %icc, linux_syscall_trace2 | |
1667 | add %l1, 0x4, %l2 ! npc = npc+4 | |
1668 | stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] | |
1669 | ba,pt %xcc, rtrap_clr_l6 | |
1670 | stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] | |
1671 | ||
1672 | 1: | |
1673 | /* System call failure, set Carry condition code. | |
1674 | * Also, get abs(errno) to return to the process. | |
1675 | */ | |
f7ceba36 | 1676 | andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6 |
1da177e4 LT |
1677 | sub %g0, %o0, %o0 |
1678 | or %g3, %g2, %g3 | |
1679 | stx %o0, [%sp + PTREGS_OFF + PT_V9_I0] | |
1680 | mov 1, %l6 | |
1681 | stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE] | |
1682 | bne,pn %icc, linux_syscall_trace2 | |
1683 | add %l1, 0x4, %l2 ! npc = npc+4 | |
1684 | stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] | |
1685 | ||
1686 | b,pt %xcc, rtrap | |
1687 | stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] | |
1688 | linux_syscall_trace2: | |
8d8a6479 | 1689 | add %sp, PTREGS_OFF, %o0 |
1da177e4 | 1690 | call syscall_trace |
8d8a6479 | 1691 | mov 1, %o1 |
1da177e4 LT |
1692 | stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC] |
1693 | ba,pt %xcc, rtrap | |
1694 | stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC] | |
1695 | ||
1696 | .align 32 | |
1697 | .globl __flushw_user | |
1698 | __flushw_user: | |
1699 | rdpr %otherwin, %g1 | |
1700 | brz,pn %g1, 2f | |
1701 | clr %g2 | |
1702 | 1: save %sp, -128, %sp | |
1703 | rdpr %otherwin, %g1 | |
1704 | brnz,pt %g1, 1b | |
1705 | add %g2, 1, %g2 | |
1706 | 1: sub %g2, 1, %g2 | |
1707 | brnz,pt %g2, 1b | |
1708 | restore %g0, %g0, %g0 | |
1709 | 2: retl | |
1710 | nop | |
56fb4df6 | 1711 | |
92704a1c DM |
1712 | #ifdef CONFIG_SMP |
1713 | .globl hard_smp_processor_id | |
1714 | hard_smp_processor_id: | |
ebd8c56c DM |
1715 | #endif |
1716 | .globl real_hard_smp_processor_id | |
1717 | real_hard_smp_processor_id: | |
92704a1c | 1718 | __GET_CPUID(%o0) |
56fb4df6 DM |
1719 | retl |
1720 | nop | |
85dfa19b DM |
1721 | |
1722 | /* %o0: devhandle | |
1723 | * %o1: devino | |
1724 | * | |
1725 | * returns %o0: sysino | |
1726 | */ | |
6c0f402f | 1727 | .globl sun4v_devino_to_sysino |
85dfa19b DM |
1728 | sun4v_devino_to_sysino: |
1729 | mov HV_FAST_INTR_DEVINO2SYSINO, %o5 | |
1730 | ta HV_FAST_TRAP | |
1731 | retl | |
1732 | mov %o1, %o0 | |
6c0f402f DM |
1733 | |
1734 | /* %o0: sysino | |
1735 | * | |
1736 | * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED}) | |
1737 | */ | |
1738 | .globl sun4v_intr_getenabled | |
1739 | sun4v_intr_getenabled: | |
1740 | mov HV_FAST_INTR_GETENABLED, %o5 | |
1741 | ta HV_FAST_TRAP | |
1742 | retl | |
1743 | mov %o1, %o0 | |
1744 | ||
1745 | /* %o0: sysino | |
1746 | * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED}) | |
1747 | */ | |
1748 | .globl sun4v_intr_setenabled | |
1749 | sun4v_intr_setenabled: | |
1750 | mov HV_FAST_INTR_SETENABLED, %o5 | |
1751 | ta HV_FAST_TRAP | |
1752 | retl | |
1753 | nop | |
1754 | ||
1755 | /* %o0: sysino | |
1756 | * | |
1757 | * returns %o0: intr_state (HV_INTR_STATE_*) | |
1758 | */ | |
1759 | .globl sun4v_intr_getstate | |
1760 | sun4v_intr_getstate: | |
1761 | mov HV_FAST_INTR_GETSTATE, %o5 | |
1762 | ta HV_FAST_TRAP | |
1763 | retl | |
1764 | mov %o1, %o0 | |
1765 | ||
1766 | /* %o0: sysino | |
1767 | * %o1: intr_state (HV_INTR_STATE_*) | |
1768 | */ | |
1769 | .globl sun4v_intr_setstate | |
1770 | sun4v_intr_setstate: | |
1771 | mov HV_FAST_INTR_SETSTATE, %o5 | |
1772 | ta HV_FAST_TRAP | |
1773 | retl | |
1774 | nop | |
1775 | ||
1776 | /* %o0: sysino | |
1777 | * | |
1778 | * returns %o0: cpuid | |
1779 | */ | |
1780 | .globl sun4v_intr_gettarget | |
1781 | sun4v_intr_gettarget: | |
1782 | mov HV_FAST_INTR_GETTARGET, %o5 | |
1783 | ta HV_FAST_TRAP | |
1784 | retl | |
1785 | mov %o1, %o0 | |
1786 | ||
1787 | /* %o0: sysino | |
1788 | * %o1: cpuid | |
1789 | */ | |
1790 | .globl sun4v_intr_settarget | |
1791 | sun4v_intr_settarget: | |
1792 | mov HV_FAST_INTR_SETTARGET, %o5 | |
1793 | ta HV_FAST_TRAP | |
1794 | retl | |
1795 | nop | |
1796 | ||
94f8762d DM |
1797 | /* %o0: type |
1798 | * %o1: queue paddr | |
1799 | * %o2: num queue entries | |
1800 | * | |
1801 | * returns %o0: status | |
1802 | */ | |
1803 | .globl sun4v_cpu_qconf | |
1804 | sun4v_cpu_qconf: | |
1805 | mov HV_FAST_CPU_QCONF, %o5 | |
1806 | ta HV_FAST_TRAP | |
1807 | retl | |
1808 | nop | |
6f5374c9 DM |
1809 | |
1810 | /* returns %o0: status | |
1811 | */ | |
1812 | .globl sun4v_cpu_yield | |
1813 | sun4v_cpu_yield: | |
1814 | mov HV_FAST_CPU_YIELD, %o5 | |
1815 | ta HV_FAST_TRAP | |
1816 | retl | |
1817 | nop | |
b830ab66 DM |
1818 | |
1819 | /* %o0: num cpus in cpu list | |
1820 | * %o1: cpu list paddr | |
1821 | * %o2: mondo block paddr | |
1822 | * | |
1823 | * returns %o0: status | |
1824 | */ | |
1825 | .globl sun4v_cpu_mondo_send | |
1826 | sun4v_cpu_mondo_send: | |
1827 | mov HV_FAST_CPU_MONDO_SEND, %o5 | |
1828 | ta HV_FAST_TRAP | |
1829 | retl | |
1830 | nop | |
1831 | ||
1832 | /* %o0: CPU ID | |
1833 | * | |
1834 | * returns %o0: -status if status non-zero, else | |
1835 | * %o0: cpu state as HV_CPU_STATE_* | |
1836 | */ | |
1837 | .globl sun4v_cpu_state | |
1838 | sun4v_cpu_state: | |
1839 | mov HV_FAST_CPU_STATE, %o5 | |
1840 | ta HV_FAST_TRAP | |
1841 | brnz,pn %o0, 1f | |
1842 | sub %g0, %o0, %o0 | |
1843 | mov %o1, %o0 | |
1844 | 1: retl | |
1845 | nop |