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[SPARC64]: Move kernel TLB miss handling into a seperate file.
[deliverable/linux.git] / arch / sparc64 / kernel / entry.S
CommitLineData
1da177e4
LT		 1/* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 */
9
10#include <linux/config.h>
11#include <linux/errno.h>
12
13#include <asm/head.h>
14#include <asm/asi.h>
15#include <asm/smp.h>
16#include <asm/ptrace.h>
17#include <asm/page.h>
18#include <asm/signal.h>
19#include <asm/pgtable.h>
20#include <asm/processor.h>
21#include <asm/visasm.h>
22#include <asm/estate.h>
23#include <asm/auxio.h>
6c52a96e 24#include <asm/sfafsr.h>
1da177e4 25
1da177e4
LT		 26#define curptr g6
27
28#define NR_SYSCALLS 284 /* Each OS is different... */
29
30 .text
31 .align 32
32
1da177e4
LT		 33 /* This is trivial with the new code... */
34 .globl do_fpdis
35do_fpdis:
36 sethi %hi(TSTATE_PEF), %g4 ! IEU0
37 rdpr %tstate, %g5
38 andcc %g5, %g4, %g0
39 be,pt %xcc, 1f
40 nop
41 rd %fprs, %g5
42 andcc %g5, FPRS_FEF, %g0
43 be,pt %xcc, 1f
44 nop
45
46 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
47 sethi %hi(109f), %g7
48 ba,pt %xcc, etrap
49109: or %g7, %lo(109b), %g7
50 add %g0, %g0, %g0
51 ba,a,pt %xcc, rtrap_clr_l6
52
531: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
54 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
55 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
56 be,a,pt %icc, 1f ! CTI
57 clr %g7 ! IEU0
58 ldx [%g6 + TI_GSR], %g7 ! Load Group
591: andcc %g5, FPRS_DL, %g0 ! IEU1
60 bne,pn %icc, 2f ! CTI
61 fzero %f0 ! FPA
62 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
63 bne,pn %icc, 1f ! CTI
64 fzero %f2 ! FPA
65 faddd %f0, %f2, %f4
66 fmuld %f0, %f2, %f6
67 faddd %f0, %f2, %f8
68 fmuld %f0, %f2, %f10
69 faddd %f0, %f2, %f12
70 fmuld %f0, %f2, %f14
71 faddd %f0, %f2, %f16
72 fmuld %f0, %f2, %f18
73 faddd %f0, %f2, %f20
74 fmuld %f0, %f2, %f22
75 faddd %f0, %f2, %f24
76 fmuld %f0, %f2, %f26
77 faddd %f0, %f2, %f28
78 fmuld %f0, %f2, %f30
79 faddd %f0, %f2, %f32
80 fmuld %f0, %f2, %f34
81 faddd %f0, %f2, %f36
82 fmuld %f0, %f2, %f38
83 faddd %f0, %f2, %f40
84 fmuld %f0, %f2, %f42
85 faddd %f0, %f2, %f44
86 fmuld %f0, %f2, %f46
87 faddd %f0, %f2, %f48
88 fmuld %f0, %f2, %f50
89 faddd %f0, %f2, %f52
90 fmuld %f0, %f2, %f54
91 faddd %f0, %f2, %f56
92 fmuld %f0, %f2, %f58
93 b,pt %xcc, fpdis_exit2
94 faddd %f0, %f2, %f60
951: mov SECONDARY_CONTEXT, %g3
96 add %g6, TI_FPREGS + 0x80, %g1
97 faddd %f0, %f2, %f4
98 fmuld %f0, %f2, %f6
99 ldxa [%g3] ASI_DMMU, %g5
100cplus_fptrap_insn_1:
101 sethi %hi(0), %g2
102 stxa %g2, [%g3] ASI_DMMU
103 membar #Sync
104 add %g6, TI_FPREGS + 0xc0, %g2
105 faddd %f0, %f2, %f8
106 fmuld %f0, %f2, %f10
107 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
108 ldda [%g2] ASI_BLK_S, %f48
109 faddd %f0, %f2, %f12
110 fmuld %f0, %f2, %f14
111 faddd %f0, %f2, %f16
112 fmuld %f0, %f2, %f18
113 faddd %f0, %f2, %f20
114 fmuld %f0, %f2, %f22
115 faddd %f0, %f2, %f24
116 fmuld %f0, %f2, %f26
117 faddd %f0, %f2, %f28
118 fmuld %f0, %f2, %f30
b445e26c 119 membar #Sync
1da177e4 120 b,pt %xcc, fpdis_exit
b445e26c 121 nop
1da177e4
LT		 1222: andcc %g5, FPRS_DU, %g0
123 bne,pt %icc, 3f
124 fzero %f32
125 mov SECONDARY_CONTEXT, %g3
126 fzero %f34
127 ldxa [%g3] ASI_DMMU, %g5
128 add %g6, TI_FPREGS, %g1
129cplus_fptrap_insn_2:
130 sethi %hi(0), %g2
131 stxa %g2, [%g3] ASI_DMMU
132 membar #Sync
133 add %g6, TI_FPREGS + 0x40, %g2
134 faddd %f32, %f34, %f36
135 fmuld %f32, %f34, %f38
136 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
137 ldda [%g2] ASI_BLK_S, %f16
138 faddd %f32, %f34, %f40
139 fmuld %f32, %f34, %f42
140 faddd %f32, %f34, %f44
141 fmuld %f32, %f34, %f46
142 faddd %f32, %f34, %f48
143 fmuld %f32, %f34, %f50
144 faddd %f32, %f34, %f52
145 fmuld %f32, %f34, %f54
146 faddd %f32, %f34, %f56
147 fmuld %f32, %f34, %f58
148 faddd %f32, %f34, %f60
149 fmuld %f32, %f34, %f62
b445e26c 150 membar #Sync
1da177e4 151 ba,pt %xcc, fpdis_exit
b445e26c 152 nop
1da177e4
LT		 1533: mov SECONDARY_CONTEXT, %g3
154 add %g6, TI_FPREGS, %g1
155 ldxa [%g3] ASI_DMMU, %g5
156cplus_fptrap_insn_3:
157 sethi %hi(0), %g2
158 stxa %g2, [%g3] ASI_DMMU
159 membar #Sync
160 mov 0x40, %g2
161 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
162 ldda [%g1 + %g2] ASI_BLK_S, %f16
163 add %g1, 0x80, %g1
164 ldda [%g1] ASI_BLK_S, %f32
165 ldda [%g1 + %g2] ASI_BLK_S, %f48
166 membar #Sync
167fpdis_exit:
168 stxa %g5, [%g3] ASI_DMMU
169 membar #Sync
170fpdis_exit2:
171 wr %g7, 0, %gsr
172 ldx [%g6 + TI_XFSR], %fsr
173 rdpr %tstate, %g3
174 or %g3, %g4, %g3 ! anal...
175 wrpr %g3, %tstate
176 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
177 retry
178
179 .align 32
180fp_other_bounce:
181 call do_fpother
182 add %sp, PTREGS_OFF, %o0
183 ba,pt %xcc, rtrap
184 clr %l6
185
186 .globl do_fpother_check_fitos
187 .align 32
188do_fpother_check_fitos:
189 sethi %hi(fp_other_bounce - 4), %g7
190 or %g7, %lo(fp_other_bounce - 4), %g7
191
192 /* NOTE: Need to preserve %g7 until we fully commit
193 * to the fitos fixup.
194 */
195 stx %fsr, [%g6 + TI_XFSR]
196 rdpr %tstate, %g3
197 andcc %g3, TSTATE_PRIV, %g0
198 bne,pn %xcc, do_fptrap_after_fsr
199 nop
200 ldx [%g6 + TI_XFSR], %g3
201 srlx %g3, 14, %g1
202 and %g1, 7, %g1
203 cmp %g1, 2 ! Unfinished FP-OP
204 bne,pn %xcc, do_fptrap_after_fsr
205 sethi %hi(1 << 23), %g1 ! Inexact
206 andcc %g3, %g1, %g0
207 bne,pn %xcc, do_fptrap_after_fsr
208 rdpr %tpc, %g1
209 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
210#define FITOS_MASK 0xc1f83fe0
211#define FITOS_COMPARE 0x81a01880
212 sethi %hi(FITOS_MASK), %g1
213 or %g1, %lo(FITOS_MASK), %g1
214 and %g3, %g1, %g1
215 sethi %hi(FITOS_COMPARE), %g2
216 or %g2, %lo(FITOS_COMPARE), %g2
217 cmp %g1, %g2
218 bne,pn %xcc, do_fptrap_after_fsr
219 nop
220 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
221 sethi %hi(fitos_table_1), %g1
222 and %g3, 0x1f, %g2
223 or %g1, %lo(fitos_table_1), %g1
224 sllx %g2, 2, %g2
225 jmpl %g1 + %g2, %g0
226 ba,pt %xcc, fitos_emul_continue
227
228fitos_table_1:
229 fitod %f0, %f62
230 fitod %f1, %f62
231 fitod %f2, %f62
232 fitod %f3, %f62
233 fitod %f4, %f62
234 fitod %f5, %f62
235 fitod %f6, %f62
236 fitod %f7, %f62
237 fitod %f8, %f62
238 fitod %f9, %f62
239 fitod %f10, %f62
240 fitod %f11, %f62
241 fitod %f12, %f62
242 fitod %f13, %f62
243 fitod %f14, %f62
244 fitod %f15, %f62
245 fitod %f16, %f62
246 fitod %f17, %f62
247 fitod %f18, %f62
248 fitod %f19, %f62
249 fitod %f20, %f62
250 fitod %f21, %f62
251 fitod %f22, %f62
252 fitod %f23, %f62
253 fitod %f24, %f62
254 fitod %f25, %f62
255 fitod %f26, %f62
256 fitod %f27, %f62
257 fitod %f28, %f62
258 fitod %f29, %f62
259 fitod %f30, %f62
260 fitod %f31, %f62
261
262fitos_emul_continue:
263 sethi %hi(fitos_table_2), %g1
264 srl %g3, 25, %g2
265 or %g1, %lo(fitos_table_2), %g1
266 and %g2, 0x1f, %g2
267 sllx %g2, 2, %g2
268 jmpl %g1 + %g2, %g0
269 ba,pt %xcc, fitos_emul_fini
270
271fitos_table_2:
272 fdtos %f62, %f0
273 fdtos %f62, %f1
274 fdtos %f62, %f2
275 fdtos %f62, %f3
276 fdtos %f62, %f4
277 fdtos %f62, %f5
278 fdtos %f62, %f6
279 fdtos %f62, %f7
280 fdtos %f62, %f8
281 fdtos %f62, %f9
282 fdtos %f62, %f10
283 fdtos %f62, %f11
284 fdtos %f62, %f12
285 fdtos %f62, %f13
286 fdtos %f62, %f14
287 fdtos %f62, %f15
288 fdtos %f62, %f16
289 fdtos %f62, %f17
290 fdtos %f62, %f18
291 fdtos %f62, %f19
292 fdtos %f62, %f20
293 fdtos %f62, %f21
294 fdtos %f62, %f22
295 fdtos %f62, %f23
296 fdtos %f62, %f24
297 fdtos %f62, %f25
298 fdtos %f62, %f26
299 fdtos %f62, %f27
300 fdtos %f62, %f28
301 fdtos %f62, %f29
302 fdtos %f62, %f30
303 fdtos %f62, %f31
304
305fitos_emul_fini:
306 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
307 done
308
309 .globl do_fptrap
310 .align 32
311do_fptrap:
312 stx %fsr, [%g6 + TI_XFSR]
313do_fptrap_after_fsr:
314 ldub [%g6 + TI_FPSAVED], %g3
315 rd %fprs, %g1
316 or %g3, %g1, %g3
317 stb %g3, [%g6 + TI_FPSAVED]
318 rd %gsr, %g3
319 stx %g3, [%g6 + TI_GSR]
320 mov SECONDARY_CONTEXT, %g3
321 ldxa [%g3] ASI_DMMU, %g5
322cplus_fptrap_insn_4:
323 sethi %hi(0), %g2
324 stxa %g2, [%g3] ASI_DMMU
325 membar #Sync
326 add %g6, TI_FPREGS, %g2
327 andcc %g1, FPRS_DL, %g0
328 be,pn %icc, 4f
329 mov 0x40, %g3
330 stda %f0, [%g2] ASI_BLK_S
331 stda %f16, [%g2 + %g3] ASI_BLK_S
332 andcc %g1, FPRS_DU, %g0
333 be,pn %icc, 5f
3344: add %g2, 128, %g2
335 stda %f32, [%g2] ASI_BLK_S
336 stda %f48, [%g2 + %g3] ASI_BLK_S
3375: mov SECONDARY_CONTEXT, %g1
338 membar #Sync
339 stxa %g5, [%g1] ASI_DMMU
340 membar #Sync
341 ba,pt %xcc, etrap
342 wr %g0, 0, %fprs
343
344cplus_fptrap_1:
345 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
346
347 .globl cheetah_plus_patch_fpdis
348cheetah_plus_patch_fpdis:
349 /* We configure the dTLB512_0 for 4MB pages and the
350 * dTLB512_1 for 8K pages when in context zero.
351 */
352 sethi %hi(cplus_fptrap_1), %o0
353 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
354
355 set cplus_fptrap_insn_1, %o2
356 stw %o1, [%o2]
357 flush %o2
358 set cplus_fptrap_insn_2, %o2
359 stw %o1, [%o2]
360 flush %o2
361 set cplus_fptrap_insn_3, %o2
362 stw %o1, [%o2]
363 flush %o2
364 set cplus_fptrap_insn_4, %o2
365 stw %o1, [%o2]
366 flush %o2
367
368 retl
369 nop
370
371 /* The registers for cross calls will be:
372 *
373 * DATA 0: [low 32-bits] Address of function to call, jmp to this
374 * [high 32-bits] MMU Context Argument 0, place in %g5
375 * DATA 1: Address Argument 1, place in %g6
376 * DATA 2: Address Argument 2, place in %g7
377 *
378 * With this method we can do most of the cross-call tlb/cache
379 * flushing very quickly.
380 *
381 * Current CPU's IRQ worklist table is locked into %g1,
382 * don't touch.
383 */
384 .text
385 .align 32
386 .globl do_ivec
387do_ivec:
388 mov 0x40, %g3
389 ldxa [%g3 + %g0] ASI_INTR_R, %g3
390 sethi %hi(KERNBASE), %g4
391 cmp %g3, %g4
392 bgeu,pn %xcc, do_ivec_xcall
393 srlx %g3, 32, %g5
394 stxa %g0, [%g0] ASI_INTR_RECEIVE
395 membar #Sync
396
397 sethi %hi(ivector_table), %g2
398 sllx %g3, 5, %g3
399 or %g2, %lo(ivector_table), %g2
400 add %g2, %g3, %g3
1da177e4 401 ldub [%g3 + 0x04], %g4 /* pil */
088dd1f8 402 mov 1, %g2
1da177e4
LT		 403 sllx %g2, %g4, %g2
404 sllx %g4, 2, %g4
088dd1f8 405
1da177e4
LT		 406 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
407 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
408 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
409 wr %g2, 0x0, %set_softint
410 retry
411do_ivec_xcall:
412 mov 0x50, %g1
1da177e4
LT		 413 ldxa [%g1 + %g0] ASI_INTR_R, %g1
414 srl %g3, 0, %g3
088dd1f8 415
1da177e4
LT		 416 mov 0x60, %g7
417 ldxa [%g7 + %g0] ASI_INTR_R, %g7
418 stxa %g0, [%g0] ASI_INTR_RECEIVE
419 membar #Sync
420 ba,pt %xcc, 1f
421 nop
422
423 .align 32
4241: jmpl %g3, %g0
425 nop
426
1da177e4
LT		 427 .globl save_alternate_globals
428save_alternate_globals: /* %o0 = save_area */
429 rdpr %pstate, %o5
430 andn %o5, PSTATE_IE, %o1
431 wrpr %o1, PSTATE_AG, %pstate
432 stx %g0, [%o0 + 0x00]
433 stx %g1, [%o0 + 0x08]
434 stx %g2, [%o0 + 0x10]
435 stx %g3, [%o0 + 0x18]
436 stx %g4, [%o0 + 0x20]
437 stx %g5, [%o0 + 0x28]
438 stx %g6, [%o0 + 0x30]
439 stx %g7, [%o0 + 0x38]
440 wrpr %o1, PSTATE_IG, %pstate
441 stx %g0, [%o0 + 0x40]
442 stx %g1, [%o0 + 0x48]
443 stx %g2, [%o0 + 0x50]
444 stx %g3, [%o0 + 0x58]
445 stx %g4, [%o0 + 0x60]
446 stx %g5, [%o0 + 0x68]
447 stx %g6, [%o0 + 0x70]
448 stx %g7, [%o0 + 0x78]
449 wrpr %o1, PSTATE_MG, %pstate
450 stx %g0, [%o0 + 0x80]
451 stx %g1, [%o0 + 0x88]
452 stx %g2, [%o0 + 0x90]
453 stx %g3, [%o0 + 0x98]
454 stx %g4, [%o0 + 0xa0]
455 stx %g5, [%o0 + 0xa8]
456 stx %g6, [%o0 + 0xb0]
457 stx %g7, [%o0 + 0xb8]
458 wrpr %o5, 0x0, %pstate
459 retl
460 nop
461
462 .globl restore_alternate_globals
463restore_alternate_globals: /* %o0 = save_area */
464 rdpr %pstate, %o5
465 andn %o5, PSTATE_IE, %o1
466 wrpr %o1, PSTATE_AG, %pstate
467 ldx [%o0 + 0x00], %g0
468 ldx [%o0 + 0x08], %g1
469 ldx [%o0 + 0x10], %g2
470 ldx [%o0 + 0x18], %g3
471 ldx [%o0 + 0x20], %g4
472 ldx [%o0 + 0x28], %g5
473 ldx [%o0 + 0x30], %g6
474 ldx [%o0 + 0x38], %g7
475 wrpr %o1, PSTATE_IG, %pstate
476 ldx [%o0 + 0x40], %g0
477 ldx [%o0 + 0x48], %g1
478 ldx [%o0 + 0x50], %g2
479 ldx [%o0 + 0x58], %g3
480 ldx [%o0 + 0x60], %g4
481 ldx [%o0 + 0x68], %g5
482 ldx [%o0 + 0x70], %g6
483 ldx [%o0 + 0x78], %g7
484 wrpr %o1, PSTATE_MG, %pstate
485 ldx [%o0 + 0x80], %g0
486 ldx [%o0 + 0x88], %g1
487 ldx [%o0 + 0x90], %g2
488 ldx [%o0 + 0x98], %g3
489 ldx [%o0 + 0xa0], %g4
490 ldx [%o0 + 0xa8], %g5
491 ldx [%o0 + 0xb0], %g6
492 ldx [%o0 + 0xb8], %g7
493 wrpr %o5, 0x0, %pstate
494 retl
495 nop
496
497 .globl getcc, setcc
498getcc:
499 ldx [%o0 + PT_V9_TSTATE], %o1
500 srlx %o1, 32, %o1
501 and %o1, 0xf, %o1
502 retl
503 stx %o1, [%o0 + PT_V9_G1]
504setcc:
505 ldx [%o0 + PT_V9_TSTATE], %o1
506 ldx [%o0 + PT_V9_G1], %o2
507 or %g0, %ulo(TSTATE_ICC), %o3
508 sllx %o3, 32, %o3
509 andn %o1, %o3, %o1
510 sllx %o2, 32, %o2
511 and %o2, %o3, %o2
512 or %o1, %o2, %o1
513 retl
514 stx %o1, [%o0 + PT_V9_TSTATE]
515
516 .globl utrap, utrap_ill
517utrap: brz,pn %g1, etrap
518 nop
519 save %sp, -128, %sp
520 rdpr %tstate, %l6
521 rdpr %cwp, %l7
522 andn %l6, TSTATE_CWP, %l6
523 wrpr %l6, %l7, %tstate
524 rdpr %tpc, %l6
525 rdpr %tnpc, %l7
526 wrpr %g1, 0, %tnpc
527 done
528utrap_ill:
529 call bad_trap
530 add %sp, PTREGS_OFF, %o0
531 ba,pt %xcc, rtrap
532 clr %l6
533
1da177e4
LT		 534 /* XXX Here is stuff we still need to write... -DaveM XXX */
535 .globl netbsd_syscall
536netbsd_syscall:
537 retl
538 nop
539
6c52a96e
DM		 540 /* We need to carefully read the error status, ACK
541 * the errors, prevent recursive traps, and pass the
542 * information on to C code for logging.
543 *
544 * We pass the AFAR in as-is, and we encode the status
545 * information as described in asm-sparc64/sfafsr.h
546 */
547 .globl __spitfire_access_error
548__spitfire_access_error:
549 /* Disable ESTATE error reporting so that we do not
550 * take recursive traps and RED state the processor.
551 */
552 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
553 membar #Sync
554
555 mov UDBE_UE, %g1
556 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
557
558 /* __spitfire_cee_trap branches here with AFSR in %g4 and
559 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the
560 * ESTATE Error Enable register.
561 */
562__spitfire_cee_trap_continue:
563 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
564
565 rdpr %tt, %g3
566 and %g3, 0x1ff, %g3 ! Paranoia
567 sllx %g3, SFSTAT_TRAP_TYPE_SHIFT, %g3
568 or %g4, %g3, %g4
569 rdpr %tl, %g3
570 cmp %g3, 1
571 mov 1, %g3
572 bleu %xcc, 1f
573 sllx %g3, SFSTAT_TL_GT_ONE_SHIFT, %g3
574
575 or %g4, %g3, %g4
576
577 /* Read in the UDB error register state, clearing the
578 * sticky error bits as-needed. We only clear them if
579 * the UE bit is set. Likewise, __spitfire_cee_trap
580 * below will only do so if the CE bit is set.
581 *
582 * NOTE: UltraSparc-I/II have high and low UDB error
583 * registers, corresponding to the two UDB units
584 * present on those chips. UltraSparc-IIi only
585 * has a single UDB, called "SDB" in the manual.
586 * For IIi the upper UDB register always reads
587 * as zero so for our purposes things will just
588 * work with the checks below.
589 */
5901: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
591 and %g3, 0x3ff, %g7 ! Paranoia
592 sllx %g7, SFSTAT_UDBH_SHIFT, %g7
593 or %g4, %g7, %g4
594 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
595 be,pn %xcc, 1f
596 nop
597 stxa %g3, [%g0] ASI_UDB_ERROR_W
598 membar #Sync
599
6001: mov 0x18, %g3
601 ldxa [%g3] ASI_UDBL_ERROR_R, %g3
602 and %g3, 0x3ff, %g7 ! Paranoia
603 sllx %g7, SFSTAT_UDBL_SHIFT, %g7
604 or %g4, %g7, %g4
605 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE
606 be,pn %xcc, 1f
607 nop
608 mov 0x18, %g7
609 stxa %g3, [%g7] ASI_UDB_ERROR_W
610 membar #Sync
611
6121: /* Ok, now that we've latched the error state,
613 * clear the sticky bits in the AFSR.
614 */
615 stxa %g4, [%g0] ASI_AFSR
616 membar #Sync
617
618 rdpr %tl, %g2
619 cmp %g2, 1
620 rdpr %pil, %g2
621 bleu,pt %xcc, 1f
622 wrpr %g0, 15, %pil
623
624 ba,pt %xcc, etraptl1
625 rd %pc, %g7
626
627 ba,pt %xcc, 2f
628 nop
629
6301: ba,pt %xcc, etrap_irq
631 rd %pc, %g7
632
6332: mov %l4, %o1
634 mov %l5, %o2
635 call spitfire_access_error
636 add %sp, PTREGS_OFF, %o0
637 ba,pt %xcc, rtrap
638 clr %l6
639
640 /* This is the trap handler entry point for ECC correctable
641 * errors. They are corrected, but we listen for the trap
642 * so that the event can be logged.
643 *
644 * Disrupting errors are either:
645 * 1) single-bit ECC errors during UDB reads to system
646 * memory
647 * 2) data parity errors during write-back events
648 *
649 * As far as I can make out from the manual, the CEE trap
650 * is only for correctable errors during memory read
651 * accesses by the front-end of the processor.
652 *
653 * The code below is only for trap level 1 CEE events,
654 * as it is the only situation where we can safely record
655 * and log. For trap level >1 we just clear the CE bit
656 * in the AFSR and return.
657 *
658 * This is just like __spiftire_access_error above, but it
659 * specifically handles correctable errors. If an
660 * uncorrectable error is indicated in the AFSR we
661 * will branch directly above to __spitfire_access_error
662 * to handle it instead. Uncorrectable therefore takes
663 * priority over correctable, and the error logging
664 * C code will notice this case by inspecting the
665 * trap type.
666 */
667 .globl __spitfire_cee_trap
668__spitfire_cee_trap:
669 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
670 mov 1, %g3
671 sllx %g3, SFAFSR_UE_SHIFT, %g3
672 andcc %g4, %g3, %g0 ! Check for UE
673 bne,pn %xcc, __spitfire_access_error
674 nop
675
676 /* Ok, in this case we only have a correctable error.
677 * Indicate we only wish to capture that state in register
678 * %g1, and we only disable CE error reporting unlike UE
679 * handling which disables all errors.
680 */
681 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
682 andn %g3, ESTATE_ERR_CE, %g3
683 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
684 membar #Sync
685
686 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
687 ba,pt %xcc, __spitfire_cee_trap_continue
688 mov UDBE_CE, %g1
689
690 .globl __spitfire_data_access_exception
691 .globl __spitfire_data_access_exception_tl1
692__spitfire_data_access_exception_tl1:
1da177e4
LT		 693 rdpr %pstate, %g4
694 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
695 mov TLB_SFSR, %g3
696 mov DMMU_SFAR, %g5
697 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
698 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
699 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
700 membar #Sync
bde4e4ee
DM		 701 rdpr %tt, %g3
702 cmp %g3, 0x80 ! first win spill/fill trap
703 blu,pn %xcc, 1f
704 cmp %g3, 0xff ! last win spill/fill trap
705 bgu,pn %xcc, 1f
706 nop
1da177e4
LT		 707 ba,pt %xcc, winfix_dax
708 rdpr %tpc, %g3
bde4e4ee
DM		 7091: sethi %hi(109f), %g7
710 ba,pt %xcc, etraptl1
711109: or %g7, %lo(109b), %g7
712 mov %l4, %o1
713 mov %l5, %o2
6c52a96e 714 call spitfire_data_access_exception_tl1
bde4e4ee
DM		 715 add %sp, PTREGS_OFF, %o0
716 ba,pt %xcc, rtrap
717 clr %l6
718
6c52a96e 719__spitfire_data_access_exception:
1da177e4
LT		 720 rdpr %pstate, %g4
721 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
722 mov TLB_SFSR, %g3
723 mov DMMU_SFAR, %g5
724 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
725 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
726 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
727 membar #Sync
728 sethi %hi(109f), %g7
729 ba,pt %xcc, etrap
730109: or %g7, %lo(109b), %g7
731 mov %l4, %o1
732 mov %l5, %o2
6c52a96e 733 call spitfire_data_access_exception
1da177e4
LT		 734 add %sp, PTREGS_OFF, %o0
735 ba,pt %xcc, rtrap
736 clr %l6
737
6c52a96e
DM		 738 .globl __spitfire_insn_access_exception
739 .globl __spitfire_insn_access_exception_tl1
740__spitfire_insn_access_exception_tl1:
1da177e4
LT		 741 rdpr %pstate, %g4
742 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
743 mov TLB_SFSR, %g3
5ea68e02
DM		 744 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
745 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
1da177e4
LT		 746 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
747 membar #Sync
748 sethi %hi(109f), %g7
749 ba,pt %xcc, etraptl1
750109: or %g7, %lo(109b), %g7
751 mov %l4, %o1
752 mov %l5, %o2
6c52a96e 753 call spitfire_insn_access_exception_tl1
1da177e4
LT		 754 add %sp, PTREGS_OFF, %o0
755 ba,pt %xcc, rtrap
756 clr %l6
757
6c52a96e 758__spitfire_insn_access_exception:
1da177e4
LT		 759 rdpr %pstate, %g4
760 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
761 mov TLB_SFSR, %g3
5ea68e02
DM		 762 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
763 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
1da177e4
LT		 764 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
765 membar #Sync
766 sethi %hi(109f), %g7
767 ba,pt %xcc, etrap
768109: or %g7, %lo(109b), %g7
769 mov %l4, %o1
770 mov %l5, %o2
6c52a96e 771 call spitfire_insn_access_exception
1da177e4
LT		 772 add %sp, PTREGS_OFF, %o0
773 ba,pt %xcc, rtrap
774 clr %l6
775
1da177e4
LT		 776 /* These get patched into the trap table at boot time
777 * once we know we have a cheetah processor.
778 */
779 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
780cheetah_fecc_trap_vector:
781 membar #Sync
782 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
783 andn %g1, DCU_DC | DCU_IC, %g1
784 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
785 membar #Sync
786 sethi %hi(cheetah_fast_ecc), %g2
787 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
788 mov 0, %g1
789cheetah_fecc_trap_vector_tl1:
790 membar #Sync
791 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
792 andn %g1, DCU_DC | DCU_IC, %g1
793 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
794 membar #Sync
795 sethi %hi(cheetah_fast_ecc), %g2
796 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
797 mov 1, %g1
798 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
799cheetah_cee_trap_vector:
800 membar #Sync
801 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
802 andn %g1, DCU_IC, %g1
803 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
804 membar #Sync
805 sethi %hi(cheetah_cee), %g2
806 jmpl %g2 + %lo(cheetah_cee), %g0
807 mov 0, %g1
808cheetah_cee_trap_vector_tl1:
809 membar #Sync
810 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
811 andn %g1, DCU_IC, %g1
812 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
813 membar #Sync
814 sethi %hi(cheetah_cee), %g2
815 jmpl %g2 + %lo(cheetah_cee), %g0
816 mov 1, %g1
817 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
818cheetah_deferred_trap_vector:
819 membar #Sync
820 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
821 andn %g1, DCU_DC | DCU_IC, %g1;
822 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
823 membar #Sync;
824 sethi %hi(cheetah_deferred_trap), %g2
825 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
826 mov 0, %g1
827cheetah_deferred_trap_vector_tl1:
828 membar #Sync;
829 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
830 andn %g1, DCU_DC | DCU_IC, %g1;
831 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
832 membar #Sync;
833 sethi %hi(cheetah_deferred_trap), %g2
834 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
835 mov 1, %g1
836
837 /* Cheetah+ specific traps. These are for the new I/D cache parity
838 * error traps. The first argument to cheetah_plus_parity_handler
839 * is encoded as follows:
840 *
841 * Bit0: 0=dcache,1=icache
842 * Bit1: 0=recoverable,1=unrecoverable
843 */
844 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
845cheetah_plus_dcpe_trap_vector:
846 membar #Sync
847 sethi %hi(do_cheetah_plus_data_parity), %g7
848 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
849 nop
850 nop
851 nop
852 nop
853 nop
854
855do_cheetah_plus_data_parity:
856 ba,pt %xcc, etrap
857 rd %pc, %g7
858 mov 0x0, %o0
859 call cheetah_plus_parity_error
860 add %sp, PTREGS_OFF, %o1
861 ba,pt %xcc, rtrap
862 clr %l6
863
864cheetah_plus_dcpe_trap_vector_tl1:
865 membar #Sync
866 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
867 sethi %hi(do_dcpe_tl1), %g3
868 jmpl %g3 + %lo(do_dcpe_tl1), %g0
869 nop
870 nop
871 nop
872 nop
873
874 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
875cheetah_plus_icpe_trap_vector:
876 membar #Sync
877 sethi %hi(do_cheetah_plus_insn_parity), %g7
878 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
879 nop
880 nop
881 nop
882 nop
883 nop
884
885do_cheetah_plus_insn_parity:
886 ba,pt %xcc, etrap
887 rd %pc, %g7
888 mov 0x1, %o0
889 call cheetah_plus_parity_error
890 add %sp, PTREGS_OFF, %o1
891 ba,pt %xcc, rtrap
892 clr %l6
893
894cheetah_plus_icpe_trap_vector_tl1:
895 membar #Sync
896 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
897 sethi %hi(do_icpe_tl1), %g3
898 jmpl %g3 + %lo(do_icpe_tl1), %g0
899 nop
900 nop
901 nop
902 nop
903
904 /* If we take one of these traps when tl >= 1, then we
905 * jump to interrupt globals. If some trap level above us
906 * was also using interrupt globals, we cannot recover.
907 * We may use all interrupt global registers except %g6.
908 */
909 .globl do_dcpe_tl1, do_icpe_tl1
910do_dcpe_tl1:
911 rdpr %tl, %g1 ! Save original trap level
912 mov 1, %g2 ! Setup TSTATE checking loop
913 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
9141: wrpr %g2, %tl ! Set trap level to check
915 rdpr %tstate, %g4 ! Read TSTATE for this level
916 andcc %g4, %g3, %g0 ! Interrupt globals in use?
917 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
918 wrpr %g1, %tl ! Restore original trap level
919 add %g2, 1, %g2 ! Next trap level
920 cmp %g2, %g1 ! Hit them all yet?
921 ble,pt %icc, 1b ! Not yet
922 nop
923 wrpr %g1, %tl ! Restore original trap level
924do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
925 /* Reset D-cache parity */
926 sethi %hi(1 << 16), %g1 ! D-cache size
927 mov (1 << 5), %g2 ! D-cache line size
928 sub %g1, %g2, %g1 ! Move down 1 cacheline
9291: srl %g1, 14, %g3 ! Compute UTAG
930 membar #Sync
931 stxa %g3, [%g1] ASI_DCACHE_UTAG
932 membar #Sync
933 sub %g2, 8, %g3 ! 64-bit data word within line
9342: membar #Sync
935 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
936 membar #Sync
937 subcc %g3, 8, %g3 ! Next 64-bit data word
938 bge,pt %icc, 2b
939 nop
940 subcc %g1, %g2, %g1 ! Next cacheline
941 bge,pt %icc, 1b
942 nop
943 ba,pt %xcc, dcpe_icpe_tl1_common
944 nop
945
946do_dcpe_tl1_fatal:
947 sethi %hi(1f), %g7
948 ba,pt %xcc, etraptl1
9491: or %g7, %lo(1b), %g7
950 mov 0x2, %o0
951 call cheetah_plus_parity_error
952 add %sp, PTREGS_OFF, %o1
953 ba,pt %xcc, rtrap
954 clr %l6
955
956do_icpe_tl1:
957 rdpr %tl, %g1 ! Save original trap level
958 mov 1, %g2 ! Setup TSTATE checking loop
959 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
9601: wrpr %g2, %tl ! Set trap level to check
961 rdpr %tstate, %g4 ! Read TSTATE for this level
962 andcc %g4, %g3, %g0 ! Interrupt globals in use?
963 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
964 wrpr %g1, %tl ! Restore original trap level
965 add %g2, 1, %g2 ! Next trap level
966 cmp %g2, %g1 ! Hit them all yet?
967 ble,pt %icc, 1b ! Not yet
968 nop
969 wrpr %g1, %tl ! Restore original trap level
970do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
971 /* Flush I-cache */
972 sethi %hi(1 << 15), %g1 ! I-cache size
973 mov (1 << 5), %g2 ! I-cache line size
974 sub %g1, %g2, %g1
9751: or %g1, (2 << 3), %g3
976 stxa %g0, [%g3] ASI_IC_TAG
977 membar #Sync
978 subcc %g1, %g2, %g1
979 bge,pt %icc, 1b
980 nop
981 ba,pt %xcc, dcpe_icpe_tl1_common
982 nop
983
984do_icpe_tl1_fatal:
985 sethi %hi(1f), %g7
986 ba,pt %xcc, etraptl1
9871: or %g7, %lo(1b), %g7
988 mov 0x3, %o0
989 call cheetah_plus_parity_error
990 add %sp, PTREGS_OFF, %o1
991 ba,pt %xcc, rtrap
992 clr %l6
993
994dcpe_icpe_tl1_common:
995 /* Flush D-cache, re-enable D/I caches in DCU and finally
996 * retry the trapping instruction.
997 */
998 sethi %hi(1 << 16), %g1 ! D-cache size
999 mov (1 << 5), %g2 ! D-cache line size
1000 sub %g1, %g2, %g1
10011: stxa %g0, [%g1] ASI_DCACHE_TAG
1002 membar #Sync
1003 subcc %g1, %g2, %g1
1004 bge,pt %icc, 1b
1005 nop
1006 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1007 or %g1, (DCU_DC | DCU_IC), %g1
1008 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1009 membar #Sync
1010 retry
1011
3c2cafaf
DM		 1012 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1013 *
1014 * %g1: (TL>=0) ? 1 : 0
1015 * %g2: scratch
1016 * %g3: scratch
1017 * %g4: AFSR
1018 * %g5: AFAR
1019 * %g6: current thread ptr
1020 * %g7: scratch
1021 */
1022__cheetah_log_error:
1023 /* Put "TL1" software bit into AFSR. */
1024 and %g1, 0x1, %g1
1025 sllx %g1, 63, %g2
1026 or %g4, %g2, %g4
1027
1028 /* Get log entry pointer for this cpu at this trap level. */
1029 BRANCH_IF_JALAPENO(g2,g3,50f)
1030 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1031 srlx %g2, 17, %g2
1032 ba,pt %xcc, 60f
1033 and %g2, 0x3ff, %g2
1034
103550: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1036 srlx %g2, 17, %g2
1037 and %g2, 0x1f, %g2
1038
103960: sllx %g2, 9, %g2
1040 sethi %hi(cheetah_error_log), %g3
1041 ldx [%g3 + %lo(cheetah_error_log)], %g3
1042 brz,pn %g3, 80f
1043 nop
1044
1045 add %g3, %g2, %g3
1046 sllx %g1, 8, %g1
1047 add %g3, %g1, %g1
1048
1049 /* %g1 holds pointer to the top of the logging scoreboard */
1050 ldx [%g1 + 0x0], %g7
1051 cmp %g7, -1
1052 bne,pn %xcc, 80f
1053 nop
1054
1055 stx %g4, [%g1 + 0x0]
1056 stx %g5, [%g1 + 0x8]
1057 add %g1, 0x10, %g1
1058
1059 /* %g1 now points to D-cache logging area */
1060 set 0x3ff8, %g2 /* DC_addr mask */
1061 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1062 srlx %g5, 12, %g3
1063 or %g3, 1, %g3 /* PHYS tag + valid */
1064
106510: ldxa [%g2] ASI_DCACHE_TAG, %g7
1066 cmp %g3, %g7 /* TAG match? */
1067 bne,pt %xcc, 13f
1068 nop
1069
1070 /* Yep, what we want, capture state. */
1071 stx %g2, [%g1 + 0x20]
1072 stx %g7, [%g1 + 0x28]
1073
1074 /* A membar Sync is required before and after utag access. */
1075 membar #Sync
1076 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1077 membar #Sync
1078 stx %g7, [%g1 + 0x30]
1079 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1080 stx %g7, [%g1 + 0x38]
1081 clr %g3
1082
108312: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1084 stx %g7, [%g1]
1085 add %g3, (1 << 5), %g3
1086 cmp %g3, (4 << 5)
1087 bl,pt %xcc, 12b
1088 add %g1, 0x8, %g1
1089
1090 ba,pt %xcc, 20f
1091 add %g1, 0x20, %g1
1092
109313: sethi %hi(1 << 14), %g7
1094 add %g2, %g7, %g2
1095 srlx %g2, 14, %g7
1096 cmp %g7, 4
1097 bl,pt %xcc, 10b
1098 nop
1099
1100 add %g1, 0x40, %g1
1101
1102 /* %g1 now points to I-cache logging area */
110320: set 0x1fe0, %g2 /* IC_addr mask */
1104 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1105 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1106 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1107 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1108
110921: ldxa [%g2] ASI_IC_TAG, %g7
1110 andn %g7, 0xff, %g7
1111 cmp %g3, %g7
1112 bne,pt %xcc, 23f
1113 nop
1114
1115 /* Yep, what we want, capture state. */
1116 stx %g2, [%g1 + 0x40]
1117 stx %g7, [%g1 + 0x48]
1118 add %g2, (1 << 3), %g2
1119 ldxa [%g2] ASI_IC_TAG, %g7
1120 add %g2, (1 << 3), %g2
1121 stx %g7, [%g1 + 0x50]
1122 ldxa [%g2] ASI_IC_TAG, %g7
1123 add %g2, (1 << 3), %g2
1124 stx %g7, [%g1 + 0x60]
1125 ldxa [%g2] ASI_IC_TAG, %g7
1126 stx %g7, [%g1 + 0x68]
1127 sub %g2, (3 << 3), %g2
1128 ldxa [%g2] ASI_IC_STAG, %g7
1129 stx %g7, [%g1 + 0x58]
1130 clr %g3
1131 srlx %g2, 2, %g2
1132
113322: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1134 stx %g7, [%g1]
1135 add %g3, (1 << 3), %g3
1136 cmp %g3, (8 << 3)
1137 bl,pt %xcc, 22b
1138 add %g1, 0x8, %g1
1139
1140 ba,pt %xcc, 30f
1141 add %g1, 0x30, %g1
1142
114323: sethi %hi(1 << 14), %g7
1144 add %g2, %g7, %g2
1145 srlx %g2, 14, %g7
1146 cmp %g7, 4
1147 bl,pt %xcc, 21b
1148 nop
1149
1150 add %g1, 0x70, %g1
1151
1152 /* %g1 now points to E-cache logging area */
115330: andn %g5, (32 - 1), %g2
1154 stx %g2, [%g1 + 0x20]
1155 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1156 stx %g7, [%g1 + 0x28]
1157 ldxa [%g2] ASI_EC_R, %g0
1158 clr %g3
1159
116031: ldxa [%g3] ASI_EC_DATA, %g7
1161 stx %g7, [%g1 + %g3]
1162 add %g3, 0x8, %g3
1163 cmp %g3, 0x20
1164
1165 bl,pt %xcc, 31b
1166 nop
116780:
1168 rdpr %tt, %g2
1169 cmp %g2, 0x70
1170 be c_fast_ecc
1171 cmp %g2, 0x63
1172 be c_cee
1173 nop
1174 ba,pt %xcc, c_deferred
1175
1da177e4
LT		 1176 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1177 * in the trap table. That code has done a memory barrier
1178 * and has disabled both the I-cache and D-cache in the DCU
1179 * control register. The I-cache is disabled so that we may
1180 * capture the corrupted cache line, and the D-cache is disabled
1181 * because corrupt data may have been placed there and we don't
1182 * want to reference it.
1183 *
1184 * %g1 is one if this trap occurred at %tl >= 1.
1185 *
1186 * Next, we turn off error reporting so that we don't recurse.
1187 */
1188 .globl cheetah_fast_ecc
1189cheetah_fast_ecc:
1190 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1191 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1192 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1193 membar #Sync
1194
1195 /* Fetch and clear AFSR/AFAR */
1196 ldxa [%g0] ASI_AFSR, %g4
1197 ldxa [%g0] ASI_AFAR, %g5
1198 stxa %g4, [%g0] ASI_AFSR
1199 membar #Sync
1200
3c2cafaf
DM		 1201 ba,pt %xcc, __cheetah_log_error
1202 nop
1da177e4 1203
3c2cafaf 1204c_fast_ecc:
1da177e4
LT		 1205 rdpr %pil, %g2
1206 wrpr %g0, 15, %pil
1207 ba,pt %xcc, etrap_irq
1208 rd %pc, %g7
1209 mov %l4, %o1
1210 mov %l5, %o2
1211 call cheetah_fecc_handler
1212 add %sp, PTREGS_OFF, %o0
1213 ba,a,pt %xcc, rtrap_irq
1214
1215 /* Our caller has disabled I-cache and performed membar Sync. */
1216 .globl cheetah_cee
1217cheetah_cee:
1218 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1219 andn %g2, ESTATE_ERROR_CEEN, %g2
1220 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1221 membar #Sync
1222
1223 /* Fetch and clear AFSR/AFAR */
1224 ldxa [%g0] ASI_AFSR, %g4
1225 ldxa [%g0] ASI_AFAR, %g5
1226 stxa %g4, [%g0] ASI_AFSR
1227 membar #Sync
1228
3c2cafaf
DM		 1229 ba,pt %xcc, __cheetah_log_error
1230 nop
1da177e4 1231
3c2cafaf 1232c_cee:
1da177e4
LT		 1233 rdpr %pil, %g2
1234 wrpr %g0, 15, %pil
1235 ba,pt %xcc, etrap_irq
1236 rd %pc, %g7
1237 mov %l4, %o1
1238 mov %l5, %o2
1239 call cheetah_cee_handler
1240 add %sp, PTREGS_OFF, %o0
1241 ba,a,pt %xcc, rtrap_irq
1242
1243 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1244 .globl cheetah_deferred_trap
1245cheetah_deferred_trap:
1246 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1247 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1248 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1249 membar #Sync
1250
1251 /* Fetch and clear AFSR/AFAR */
1252 ldxa [%g0] ASI_AFSR, %g4
1253 ldxa [%g0] ASI_AFAR, %g5
1254 stxa %g4, [%g0] ASI_AFSR
1255 membar #Sync
1256
3c2cafaf
DM		 1257 ba,pt %xcc, __cheetah_log_error
1258 nop
1da177e4 1259
3c2cafaf 1260c_deferred:
1da177e4
LT		 1261 rdpr %pil, %g2
1262 wrpr %g0, 15, %pil
1263 ba,pt %xcc, etrap_irq
1264 rd %pc, %g7
1265 mov %l4, %o1
1266 mov %l5, %o2
1267 call cheetah_deferred_handler
1268 add %sp, PTREGS_OFF, %o0
1269 ba,a,pt %xcc, rtrap_irq
1270
1271 .globl __do_privact
1272__do_privact:
1273 mov TLB_SFSR, %g3
1274 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1275 membar #Sync
1276 sethi %hi(109f), %g7
1277 ba,pt %xcc, etrap
1278109: or %g7, %lo(109b), %g7
1279 call do_privact
1280 add %sp, PTREGS_OFF, %o0
1281 ba,pt %xcc, rtrap
1282 clr %l6
1283
1284 .globl do_mna
1285do_mna:
1286 rdpr %tl, %g3
1287 cmp %g3, 1
1288
1289 /* Setup %g4/%g5 now as they are used in the
1290 * winfixup code.
1291 */
1292 mov TLB_SFSR, %g3
1293 mov DMMU_SFAR, %g4
1294 ldxa [%g4] ASI_DMMU, %g4
1295 ldxa [%g3] ASI_DMMU, %g5
1296 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1297 membar #Sync
1298 bgu,pn %icc, winfix_mna
1299 rdpr %tpc, %g3
1300
13011: sethi %hi(109f), %g7
1302 ba,pt %xcc, etrap
1303109: or %g7, %lo(109b), %g7
1304 mov %l4, %o1
1305 mov %l5, %o2
1306 call mem_address_unaligned
1307 add %sp, PTREGS_OFF, %o0
1308 ba,pt %xcc, rtrap
1309 clr %l6
1310
1311 .globl do_lddfmna
1312do_lddfmna:
1313 sethi %hi(109f), %g7
1314 mov TLB_SFSR, %g4
1315 ldxa [%g4] ASI_DMMU, %g5
1316 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1317 membar #Sync
1318 mov DMMU_SFAR, %g4
1319 ldxa [%g4] ASI_DMMU, %g4
1320 ba,pt %xcc, etrap
1321109: or %g7, %lo(109b), %g7
1322 mov %l4, %o1
1323 mov %l5, %o2
1324 call handle_lddfmna
1325 add %sp, PTREGS_OFF, %o0
1326 ba,pt %xcc, rtrap
1327 clr %l6
1328
1329 .globl do_stdfmna
1330do_stdfmna:
1331 sethi %hi(109f), %g7
1332 mov TLB_SFSR, %g4
1333 ldxa [%g4] ASI_DMMU, %g5
1334 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1335 membar #Sync
1336 mov DMMU_SFAR, %g4
1337 ldxa [%g4] ASI_DMMU, %g4
1338 ba,pt %xcc, etrap
1339109: or %g7, %lo(109b), %g7
1340 mov %l4, %o1
1341 mov %l5, %o2
1342 call handle_stdfmna
1343 add %sp, PTREGS_OFF, %o0
1344 ba,pt %xcc, rtrap
1345 clr %l6
1346
1347 .globl breakpoint_trap
1348breakpoint_trap:
1349 call sparc_breakpoint
1350 add %sp, PTREGS_OFF, %o0
1351 ba,pt %xcc, rtrap
1352 nop
1353
1354#if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1355 defined(CONFIG_SOLARIS_EMUL_MODULE)
1356 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1357 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1358 * This is complete brain damage.
1359 */
1360 .globl sunos_indir
1361sunos_indir:
1362 srl %o0, 0, %o0
1363 mov %o7, %l4
1364 cmp %o0, NR_SYSCALLS
1365 blu,a,pt %icc, 1f
1366 sll %o0, 0x2, %o0
1367 sethi %hi(sunos_nosys), %l6
1368 b,pt %xcc, 2f
1369 or %l6, %lo(sunos_nosys), %l6
13701: sethi %hi(sunos_sys_table), %l7
1371 or %l7, %lo(sunos_sys_table), %l7
1372 lduw [%l7 + %o0], %l6
13732: mov %o1, %o0
1374 mov %o2, %o1
1375 mov %o3, %o2
1376 mov %o4, %o3
1377 mov %o5, %o4
1378 call %l6
1379 mov %l4, %o7
1380
1381 .globl sunos_getpid
1382sunos_getpid:
1383 call sys_getppid
1384 nop
1385 call sys_getpid
1386 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1387 b,pt %xcc, ret_sys_call
1388 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1389
1390 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1391 .globl sunos_getuid
1392sunos_getuid:
1393 call sys32_geteuid16
1394 nop
1395 call sys32_getuid16
1396 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1397 b,pt %xcc, ret_sys_call
1398 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1399
1400 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1401 .globl sunos_getgid
1402sunos_getgid:
1403 call sys32_getegid16
1404 nop
1405 call sys32_getgid16
1406 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1407 b,pt %xcc, ret_sys_call
1408 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1409#endif
1410
1411 /* SunOS's execv() call only specifies the argv argument, the
1412 * environment settings are the same as the calling processes.
1413 */
1414 .globl sunos_execv
1415sys_execve:
1416 sethi %hi(sparc_execve), %g1
1417 ba,pt %xcc, execve_merge
1418 or %g1, %lo(sparc_execve), %g1
1419#ifdef CONFIG_COMPAT
1420 .globl sys_execve
1421sunos_execv:
1422 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1423 .globl sys32_execve
1424sys32_execve:
1425 sethi %hi(sparc32_execve), %g1
1426 or %g1, %lo(sparc32_execve), %g1
1427#endif
1428execve_merge:
1429 flushw
1430 jmpl %g1, %g0
1431 add %sp, PTREGS_OFF, %o0
1432
1433 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1434 .globl sys_sigsuspend, sys_rt_sigsuspend
1435 .globl sys_rt_sigreturn
1436 .globl sys_ptrace
1437 .globl sys_sigaltstack
1438 .align 32
1439sys_pipe: ba,pt %xcc, sparc_pipe
1440 add %sp, PTREGS_OFF, %o0
1441sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1442 add %sp, PTREGS_OFF, %o0
1443sys_memory_ordering:
1444 ba,pt %xcc, sparc_memory_ordering
1445 add %sp, PTREGS_OFF, %o1
1446sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1447 add %i6, STACK_BIAS, %o2
1448#ifdef CONFIG_COMPAT
1449 .globl sys32_sigstack
1450sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1451 mov %i6, %o2
1452 .globl sys32_sigaltstack
1453sys32_sigaltstack:
1454 ba,pt %xcc, do_sys32_sigaltstack
1455 mov %i6, %o2
1456#endif
1457 .align 32
1458sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1459 call do_sigsuspend
1460 add %o7, 1f-.-4, %o7
1461 nop
1462sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1463 add %sp, PTREGS_OFF, %o2
1464 call do_rt_sigsuspend
1465 add %o7, 1f-.-4, %o7
1466 nop
1467#ifdef CONFIG_COMPAT
1468 .globl sys32_rt_sigsuspend
1469sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1470 srl %o0, 0, %o0
1471 add %sp, PTREGS_OFF, %o2
1472 call do_rt_sigsuspend32
1473 add %o7, 1f-.-4, %o7
1474#endif
1475 /* NOTE: %o0 has a correct value already */
1476sys_sigpause: add %sp, PTREGS_OFF, %o1
1477 call do_sigpause
1478 add %o7, 1f-.-4, %o7
1479 nop
1480#ifdef CONFIG_COMPAT
1481 .globl sys32_sigreturn
1482sys32_sigreturn:
1483 add %sp, PTREGS_OFF, %o0
1484 call do_sigreturn32
1485 add %o7, 1f-.-4, %o7
1486 nop
1487#endif
1488sys_rt_sigreturn:
1489 add %sp, PTREGS_OFF, %o0
1490 call do_rt_sigreturn
1491 add %o7, 1f-.-4, %o7
1492 nop
1493#ifdef CONFIG_COMPAT
1494 .globl sys32_rt_sigreturn
1495sys32_rt_sigreturn:
1496 add %sp, PTREGS_OFF, %o0
1497 call do_rt_sigreturn32
1498 add %o7, 1f-.-4, %o7
1499 nop
1500#endif
1501sys_ptrace: add %sp, PTREGS_OFF, %o0
1502 call do_ptrace
1503 add %o7, 1f-.-4, %o7
1504 nop
1505 .align 32
15061: ldx [%curptr + TI_FLAGS], %l5
f7ceba36 1507 andcc %l5, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1da177e4
LT		 1508 be,pt %icc, rtrap
1509 clr %l6
8d8a6479 1510 add %sp, PTREGS_OFF, %o0
1da177e4 1511 call syscall_trace
8d8a6479 1512 mov 1, %o1
1da177e4
LT		 1513
1514 ba,pt %xcc, rtrap
1515 clr %l6
1516
1517 /* This is how fork() was meant to be done, 8 instruction entry.
1518 *
1519 * I questioned the following code briefly, let me clear things
1520 * up so you must not reason on it like I did.
1521 *
1522 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1523 * need it here because the only piece of window state we copy to
1524 * the child is the CWP register. Even if the parent sleeps,
1525 * we are safe because we stuck it into pt_regs of the parent
1526 * so it will not change.
1527 *
1528 * XXX This raises the question, whether we can do the same on
1529 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1530 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1531 * XXX fork_kwim in UREG_G1 (global registers are considered
1532 * XXX volatile across a system call in the sparc ABI I think
1533 * XXX if it isn't we can use regs->y instead, anyone who depends
1534 * XXX upon the Y register being preserved across a fork deserves
1535 * XXX to lose).
1536 *
1537 * In fact we should take advantage of that fact for other things
1538 * during system calls...
1539 */
1540 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1541 .globl ret_from_syscall
1542 .align 32
1543sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1544 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1545 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1546 ba,pt %xcc, sys_clone
1547sys_fork: clr %o1
1548 mov SIGCHLD, %o0
1549sys_clone: flushw
1550 movrz %o1, %fp, %o1
1551 mov 0, %o3
1552 ba,pt %xcc, sparc_do_fork
1553 add %sp, PTREGS_OFF, %o2
1554ret_from_syscall:
db7d9a4e
DM		 1555 /* Clear current_thread_info()->new_child, and
1556 * check performance counter stuff too.
1da177e4 1557 */
db7d9a4e
DM		 1558 stb %g0, [%g6 + TI_NEW_CHILD]
1559 ldx [%g6 + TI_FLAGS], %l0
1da177e4
LT		 1560 call schedule_tail
1561 mov %g7, %o0
1562 andcc %l0, _TIF_PERFCTR, %g0
1563 be,pt %icc, 1f
1564 nop
1565 ldx [%g6 + TI_PCR], %o7
1566 wr %g0, %o7, %pcr
1567
1568 /* Blackbird errata workaround. See commentary in
1569 * smp.c:smp_percpu_timer_interrupt() for more
1570 * information.
1571 */
1572 ba,pt %xcc, 99f
1573 nop
1574 .align 64
157599: wr %g0, %g0, %pic
1576 rd %pic, %g0
1577
15781: b,pt %xcc, ret_sys_call
1579 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1580sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1581 rdpr %otherwin, %g1
1582 rdpr %cansave, %g3
1583 add %g3, %g1, %g3
1584 wrpr %g3, 0x0, %cansave
1585 wrpr %g0, 0x0, %otherwin
1586 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1587 ba,pt %xcc, sys_exit
1588 stb %g0, [%g6 + TI_WSAVED]
1589
1590linux_sparc_ni_syscall:
1591 sethi %hi(sys_ni_syscall), %l7
1592 b,pt %xcc, 4f
1593 or %l7, %lo(sys_ni_syscall), %l7
1594
1595linux_syscall_trace32:
8d8a6479 1596 add %sp, PTREGS_OFF, %o0
1da177e4 1597 call syscall_trace
8d8a6479 1598 clr %o1
1da177e4 1599 srl %i0, 0, %o0
8d8a6479 1600 srl %i4, 0, %o4
1da177e4
LT		 1601 srl %i1, 0, %o1
1602 srl %i2, 0, %o2
1603 b,pt %xcc, 2f
1604 srl %i3, 0, %o3
1605
1606linux_syscall_trace:
8d8a6479 1607 add %sp, PTREGS_OFF, %o0
1da177e4 1608 call syscall_trace
8d8a6479 1609 clr %o1
1da177e4
LT		 1610 mov %i0, %o0
1611 mov %i1, %o1
1612 mov %i2, %o2
1613 mov %i3, %o3
1614 b,pt %xcc, 2f
1615 mov %i4, %o4
1616
1617
1618 /* Linux 32-bit and SunOS system calls enter here... */
1619 .align 32
1620 .globl linux_sparc_syscall32
1621linux_sparc_syscall32:
1622 /* Direct access to user regs, much faster. */
1623 cmp %g1, NR_SYSCALLS ! IEU1 Group
1624 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1625 srl %i0, 0, %o0 ! IEU0
1626 sll %g1, 2, %l4 ! IEU0 Group
1da177e4
LT		 1627 srl %i4, 0, %o4 ! IEU1
1628 lduw [%l7 + %l4], %l7 ! Load
1629 srl %i1, 0, %o1 ! IEU0 Group
1630 ldx [%curptr + TI_FLAGS], %l0 ! Load
1631
1632 srl %i5, 0, %o5 ! IEU1
1633 srl %i2, 0, %o2 ! IEU0 Group
f7ceba36 1634 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1da177e4
LT		 1635 bne,pn %icc, linux_syscall_trace32 ! CTI
1636 mov %i0, %l5 ! IEU1
1637 call %l7 ! CTI Group brk forced
1638 srl %i3, 0, %o3 ! IEU0
1639 ba,a,pt %xcc, 3f
1640
1641 /* Linux native and SunOS system calls enter here... */
1642 .align 32
1643 .globl linux_sparc_syscall, ret_sys_call
1644linux_sparc_syscall:
1645 /* Direct access to user regs, much faster. */
1646 cmp %g1, NR_SYSCALLS ! IEU1 Group
1647 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1648 mov %i0, %o0 ! IEU0
1649 sll %g1, 2, %l4 ! IEU0 Group
1da177e4
LT		 1650 mov %i1, %o1 ! IEU1
1651 lduw [%l7 + %l4], %l7 ! Load
16524: mov %i2, %o2 ! IEU0 Group
1653 ldx [%curptr + TI_FLAGS], %l0 ! Load
1654
1655 mov %i3, %o3 ! IEU1
1656 mov %i4, %o4 ! IEU0 Group
f7ceba36 1657 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %g0
1da177e4
LT		 1658 bne,pn %icc, linux_syscall_trace ! CTI Group
1659 mov %i0, %l5 ! IEU0
16602: call %l7 ! CTI Group brk forced
1661 mov %i5, %o5 ! IEU0
1662 nop
1663
16643: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1665ret_sys_call:
1da177e4
LT		 1666 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1667 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1668 sra %o0, 0, %o0
1669 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1670 sllx %g2, 32, %g2
1671
1672 /* Check if force_successful_syscall_return()
1673 * was invoked.
1674 */
db7d9a4e
DM		 1675 ldub [%curptr + TI_SYS_NOERROR], %l0
1676 brz,pt %l0, 1f
1677 nop
1da177e4 1678 ba,pt %xcc, 80f
db7d9a4e 1679 stb %g0, [%curptr + TI_SYS_NOERROR]
1da177e4
LT		 1680
16811:
1682 cmp %o0, -ERESTART_RESTARTBLOCK
1683 bgeu,pn %xcc, 1f
f7ceba36 1684 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1da177e4
LT		 168580:
1686 /* System call success, clear Carry condition code. */
1687 andn %g3, %g2, %g3
1688 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1689 bne,pn %icc, linux_syscall_trace2
1690 add %l1, 0x4, %l2 ! npc = npc+4
1691 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1692 ba,pt %xcc, rtrap_clr_l6
1693 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1694
16951:
1696 /* System call failure, set Carry condition code.
1697 * Also, get abs(errno) to return to the process.
1698 */
f7ceba36 1699 andcc %l0, (_TIF_SYSCALL_TRACE|_TIF_SECCOMP|_TIF_SYSCALL_AUDIT), %l6
1da177e4
LT		 1700 sub %g0, %o0, %o0
1701 or %g3, %g2, %g3
1702 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1703 mov 1, %l6
1704 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1705 bne,pn %icc, linux_syscall_trace2
1706 add %l1, 0x4, %l2 ! npc = npc+4
1707 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1708
1709 b,pt %xcc, rtrap
1710 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1711linux_syscall_trace2:
8d8a6479 1712 add %sp, PTREGS_OFF, %o0
1da177e4 1713 call syscall_trace
8d8a6479 1714 mov 1, %o1
1da177e4
LT		 1715 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1716 ba,pt %xcc, rtrap
1717 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1718
1719 .align 32
1720 .globl __flushw_user
1721__flushw_user:
1722 rdpr %otherwin, %g1
1723 brz,pn %g1, 2f
1724 clr %g2
17251: save %sp, -128, %sp
1726 rdpr %otherwin, %g1
1727 brnz,pt %g1, 1b
1728 add %g2, 1, %g2
17291: sub %g2, 1, %g2
1730 brnz,pt %g2, 1b
1731 restore %g0, %g0, %g0
17322: retl
1733 nop
Linux kernel - Deliverables
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